Access Arbitrator, Data Sharing Module and System for Multicore Heterogeneous Data Sharing

Abstract

The present invention discloses an access arbiter, a data sharing module and a system for multi-core heterogeneous data sharing. Each first AXI interface is used to transmit first data and second data to a data exchange bridge. The first data is the information data to be transmitted received by this interface, and the second data is the control signal data sent by this interface. Each data exchange bridge is used to receive a plurality of first data and a plurality of second data, and under the action of each second data, match the corresponding first data with the data transmission interface of the corresponding memory for connection. The beneficial effects of the present invention are as follows: by setting an access arbiter with a data exchange bridge, the efficiency of data sharing and interaction is increased; it is realized to support data sharing and interaction between core devices at the hardware level; it is realized to support high-speed interfaces for multiple FPGAs and multiple processor standards; the problem of data consistency caused by simultaneous access of multiple devices is solved; and the hardware requirements are optional.

Description

Technical Field

[0001] The present invention relates to the technical field of data information interaction, and more particularly, to an access arbiter, a data sharing module, and a system for multi-core heterogeneous data sharing. Background Art

[0002] Multi-core heterogeneous data sharing is applied to the design of electronic devices in various industries. Due to the strong program portability, convenient trimming, low development threshold, and customizability of the CPU, the multi-core heterogeneous design scheme of FPGA+CPU is widely adopted in many electronic devices such as supercomputer nodes, communication nodes, special equipment, and military products. In the industry, at the present stage, the multi-core heterogeneous design scheme of FPGA+CPU does not have a dedicated data sharing mechanism for core devices, nor a dedicated design scheme for shared data memories of core devices. Such a design will result in inconvenient use of data sharing among core devices, complex software design, low efficiency of data interaction and sharing among multiple core devices, causing problems such as high software development complexity, long development cycle, and limited data sharing and interaction bandwidth; it is impossible to achieve high-speed data sharing and data interaction among core devices.

[0003] In view of this, the present application is specifically proposed. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that in the existing data sharing, the data interaction design among multiple core devices is cumbersome and complex, and the sharing efficiency is low. The purpose is to provide an access arbiter, a data sharing module, and a system for multi-core heterogeneous data sharing, which can achieve high-speed data sharing among multi-core devices and increase the efficiency of data sharing.

[0005] The present invention is achieved by the following technical solutions:

[0006] An access arbiter for multi-core heterogeneous data sharing, characterized in that it includes a plurality of first AXI interfaces and a plurality of data exchange bridges.

[0007] Each of the first AXI interfaces is used to transmit first data and second data to the data exchange bridge. The first data is the information data that needs to be transmitted received by this interface, and the second data is the control signal data sent by this interface.

[0008] Each of the data exchange bridges is used to receive a plurality of first data and a plurality of second data, and under the action of each of the second data, match the corresponding first data with the data transmission interface of the corresponding memory for connection.

[0009] Traditionally, in the data sharing method, it is necessary to set up multiple software to achieve data sharing between core devices. However, when using this method to share data, it often results in complex software design, low efficiency of data interaction and sharing among multiple core devices, high software development complexity, long development cycle, and limited data sharing and interaction bandwidth. The present invention provides an access arbiter for multi-core heterogeneous data sharing. By adding a data exchange bridge in the access arbiter and performing unified port processing on the interfaces for data transmission, it can achieve fast data sharing and interaction among multi-core devices, increasing the efficiency of data sharing and interaction.

[0010] Preferably, the data exchange bridge includes a multiplexer and an ID latch.

[0011] The ID latch is used to receive the second data, and under the trigger of the second data, perform a write operation and send a signal indicating successful write operation to the multiplexer.

[0012] The multiplexer is used to receive a plurality of the first data, and under the action of the signal, select the corresponding first data and, based on this first data, match the data transmission interface channel with the backend memory.

[0013] The present invention also provides a data sharing module for multi-core heterogeneous data sharing, including a data port adapter, a storage adapter, and the access arbiter as described above.

[0014] The data port adapter is used to unify various types of data interfaces and form a unified data access port to interact with the access arbiter for data information.

[0015] The access arbiter is used to arbitrate and schedule the data transmitted by the data port adapter and transmit the arbitrated and scheduled data to the memory adapter.

[0016] The storage adapter is used to perform a normalization operation on the data scheduled by the access arbiter and the corresponding memory interface.

[0017] Preferably, the data port adapter includes a first interface layer and an AXI port. The first interface layer contains several different types of interfaces, and each interface is connected to an AXI port. The AXI port is used to interact with the access arbiter for data, and each AXI port corresponds to a first AXI interface in the access arbiter.

[0018] Preferably, the storage adapter includes an AXI interface layer and a memory driver layer. The AXI interface layer is used to interact with the access arbiter for data, and the memory driver layer is used to drive the hardware chip and implement the data read / write and operation interface timing.

[0019] Preferably, a plurality of second AXI interfaces are provided in the AXI interface layer, and the data of the provided second AXI interfaces is the same as the number of data exchange bridges provided in the access arbiter, and they are provided in one-to-one correspondence.

[0020] The present invention also provides a multi-core heterogeneous data sharing system, including a core device, a storage module, and the data sharing module for multi-core heterogeneous data sharing as described above.

[0021] The core device includes a plurality of integrated circuit chips, and data sharing and data interaction are both achieved with the storage module through the data sharing module.

[0022] The data sharing module is used to achieve data sharing and data interaction with the core device.

[0023] The storage module is used to store the data that the core device needs to read, write, or run.

[0024] Preferably, the integrated circuit chip is an integrated circuit chip with multiple types of interfaces, and the multiple types of interfaces include a DDR4 interface, a DDR3 interface, a NorFlash interface, a NandFlash interface, a QSPI interface, a PCIE interface, and an SRIO interface.

[0025] Preferably, the number of interfaces provided in the first interface layer is the same as the number of interfaces on the integrated circuit chip, and they are provided in corresponding settings.

[0026] Preferably, the storage module is composed of at least one type of device among a DDR memory, an SDRAM memory, and a Flash memory, and is used to store the data that the integrated circuit chip needs to read.

[0027] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0028] 1. The access arbiter, data sharing module, and system for multi-core heterogeneous data sharing provided by the embodiments of the present invention increase the efficiency of data sharing and interaction by setting an access arbiter with a data exchange bridge.

[0029] 2. The access arbiter, data sharing module, and system for multi-core heterogeneous data sharing provided by the embodiments of the present invention support data sharing and interaction between core devices at the hardware level.

[0030] 3. The access arbiter, data sharing module, and system for multi-core heterogeneous data sharing provided by the embodiments of the present invention support high-speed interfaces for multiple FPGAs and multiple processor standards, solve the data consistency problem caused by simultaneous access of multiple devices, and the hardware requirements are optional. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0032] Figure 1 Schematic diagram of access arbiter

[0033] Figure 2 Schematic diagram of data exchange bridge

[0034] Figure 3 Schematic diagram of system

[0035] Figure 4 Schematic diagram of connection of data port adapter

[0036] Figure 5 Schematic diagram of storage adapter structure DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the embodiments and the drawings. The illustrative embodiments and descriptions thereof of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0038] In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that: the present invention does not have to employ these specific details. In other embodiments, well-known structures, circuits, materials or methods have not been specifically described in order to avoid obscuring the present invention.

[0039] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the phrases "one embodiment", "an embodiment", "an example" or "an example" appearing throughout the specification do not necessarily all refer to the same embodiment or example. Additionally, the specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Furthermore, those of ordinary skill in the art should understand that the diagrams provided herein are for illustrative purposes only and are not necessarily drawn to scale. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0040] In the description of the present invention, the orientation or positional relationship indicated by the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", "low", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the protection scope of the present invention.

[0041] Embodiment 1

[0042] This embodiment discloses an access arbiter for multi-core heterogeneous data sharing, as Figure 1 shown. The access arbiter is responsible for the arbitration scheduling of the access operations of the front-end data port adapter. A number of first AXI interfaces and a number of data exchange bridges. In the access arbiter set in this embodiment, a number of AXI interfaces are included. In Figure 1 it, the first AXI interface represents the interfaces from AXI0 to AXIn;

[0043] Each of the first AXI interfaces is used to transmit the first data and the second data to the data exchange bridge. The first data is the information data that needs to be transmitted received by this interface, that is, the information data transmitted by the chip corresponding to the interface. The second data is the control signal data sent by this interface;

[0044] That is, in this embodiment, the first data is the external data received by the interface, and this data needs to be transmitted to another interface. The second data is the control signal data sent by the interface itself. The first data and the second data transmitted by the same interface share an ID. The first data and the second data are matched with each other through the ID. Therefore, when there are multiple data in the data exchange bridge, the data is matched through the same ID.

[0045] Each of the data exchange bridges is used to receive a number of first data and a number of second data, and under the action of each of the second data, match the corresponding first data with the data transmission interface of the corresponding memory for connection.

[0046] Multiple data exchange bridges are set in the access arbiter. Each exchange bridge will receive the first data and the second data transmitted by all interfaces. However, only one interface that needs to read data can be connected to the output end of each data exchange bridge. Each data exchange bridge is equivalent to a channel, and the data channels that each channel needs to read, write, or run are different.

[0047] In this embodiment, as Figure 2As shown in the figure, the data exchange bridge includes a multiplexer and an ID latch. The ID latch is used to receive the second data, perform a write operation under the trigger of the second data, and send a signal indicating the success of the write operation to the multiplexer.

[0048] The multiplexer is used to receive a plurality of the first data, and under the action of the signal, select the corresponding first data, and based on the first data, match the data transmission interface channel with the backend memory.

[0049] In this embodiment, when implementing the data exchange bridge, it is necessary to specify the priorities of AXI0 to AXIn connected to the data port adapter. The concept of priority only takes effect when accessing the same memory adapter interface simultaneously, and does not take effect at other times. The priority of each AXI interface must be different, and there can be multiple ways to set the priority. The following is one way to set the priority: the priorities of AXI0 to AXIn are 0 to n in sequence, with 0 having the highest priority and n having the lowest priority. As long as there are no equal cases among AXI0 to AXIn. When there is a simultaneous access to the same memory adapter interface, the predefined priority is used to determine which data port adapter interface obtains the access right to the memory adapter interface. The interface with a lower priority controls the access initiator through a flow control signal and delays the access.

[0050] If the first data is the data link in the data exchange bridge and the second data is the control signal, then two signal links are designed inside the data exchange bridge, namely the data link and the control signal. All interfaces of the front-end data port adapter are connected to the multiplexer, and AXI0 to AXIn are numbered, and the numbers cannot be repeated. This number is used as the access ID. When the front-end initiates an access request, the AXI0 to AXIn interfaces of the data port adapter first send a control signal. The control signal carries its own access ID and initiates a write operation request to the ID latch. If the ID latch is not in the locked state before performing the write operation, then this write ID operation is successful. The ID latch will select and connect the corresponding data port adapter interfaces AXI0 to AXIn and the AXI of the backend memory adapter according to the ID, and maintain the path state until the ID latch is unlocked. When the AXI0 to AXIn interfaces end the data access, they send a control signal to unlock the ID latch.

[0051] The access arbiter for multi-core heterogeneous data sharing disclosed in this embodiment can achieve efficient data sharing and interaction between devices and realize fast data sharing.

[0052] Embodiment 2

[0053] This embodiment discloses a data sharing module for multi-core heterogeneous data sharing, such as Figure 3As shown, it includes a data port adapter, a storage adapter, and the access arbiter for multi-core heterogeneous data sharing provided in the first embodiment.

[0054] The data port adapter is used to unify various types of data interfaces and form a unified data access port to interact with the access arbiter for data information.

[0055] As Figure 4 shown, the data port adapter includes a first interface layer and an AXI port. The first interface layer contains several different types of interfaces, and each interface is connected to an AXI port. The AXI port is the interface from AXI0 to AXIn existing in the data port adapter. The AXI port is used to perform data interaction with the access arbiter, and each AXI port corresponds to the first AXI interface in the access arbiter.

[0056] The data port adapter unifies the data interfaces of various types of core devices to form a unified data access port to interact with the access arbiter. The data port adapter docks with the core device upward and realizes all the interfaces of the core device such as DDR4, DDR3, NorFlash, NandFlash, QSPI, PCIE, SRIO, etc. through the programmable logic software IP, that is, this interface is the interface corresponding to the first interface layer described in this embodiment. The data port adapter docks with the access arbiter downward and is interconnected by a unified AXI bus. For interfaces without flow control signals or those where flow control signals are inconvenient to use and process, such as NorFlash, QSPI, DDR3 / 4, etc., custom flow control signals can be added. If custom flow control signals are used, the hardware of the core device needs to have a custom flow control design, and the software needs to program to process this flow control signal. The flow control signal can use GPIO or other trigger signals. It should be noted that the flow control signal needs to be bound to the specified interface. After the flow control signal is bound to the specified core device interface, it is connected to the AXI interface. The AXI interface has a specific flow control mechanism. The flow control signal transmitted from the core device interface to the data port adapter is integrated with the flow control mechanism of the AXI interface, and finally forms a unified AXI interface to connect to the access arbiter at the back end.

[0057] In this embodiment, the access arbiter is used to arbitrate and schedule the data transmitted by the data port adapter and transmit the arbitrated and scheduled data to the memory adapter; the access arbiter disclosed in the first embodiment is adopted, which can realize fast data sharing and interaction and improve the efficiency between data sharing and interaction.

[0058] As Figure 5As shown, the storage adapter is used to normalize the data scheduled by the access arbiter with the corresponding memory interface. The storage adapter includes an AXI interface layer and a memory driver layer. The AXI interface layer is used for data interaction with the access arbiter, and the memory driver layer is used to drive the hardware chip and implement data read / write and operation interface timing. In this embodiment, the AXI interface refers to the interfaces from AXI_A to AXI_X. The AXI interface layer is provided with a plurality of second AXI interfaces, and the data of the second AXI interfaces provided is the same as the number of data exchange bridges provided in the access arbiter, and they are set in one-to-one correspondence.

[0059] And in the access arbiter of this embodiment, the data exchange bridges and the memory adapter interfaces are in one-to-one correspondence. For however many memory adapter interfaces there are, the corresponding number of exchange bridges needs to be implemented. The data exchange bridges are responsible for connecting to all the front-end data adapters. When multiple AXI interfaces in different data ports AXI0 to AXIn simultaneously access the back-end memory interfaces AXI_A to AXI_X, if they are not accessing the same memory interface, there is no resource competition relationship and parallel access can be achieved; if they are accessing the same memory interface, there is a resource competition relationship, and only time-division multiplexing of the memory adapter interfaces can be performed, and the data exchange bridges will flow-control the data adapter interfaces AXI0 to AXIn with lower priority.

[0060] When implementing the data exchange bridges, it is necessary to specify the priorities of AXI0 to AXIn connected to the data port adapters. The concept of priority only takes effect when simultaneously accessing the same memory adapter interface, and is not effective at other times. The priority of each AXI interface must be different, and there can be various ways to set the priority.

[0061] The data sharing module for multi-core heterogeneous data sharing disclosed in this embodiment implements multiple standard industry communication interfaces through an interface controller; uniformly manages access operations through a data access arbiter; manages the actual storage body through a storage controller, and the specially designed data exchange bridges have flow-control output signals, achieving compatibility support for multiple devices from high-speed storage devices to low-speed storage devices and from high-speed core devices to low-speed core devices.

[0062] Embodiment 3

[0063] This embodiment discloses a system for multi-core heterogeneous data sharing, as Figure 3 shown, including core devices, a storage module, and the data sharing module for multi-core heterogeneous data sharing provided in Embodiment 2.

[0064] Integrated circuit chips allow software programming in the system, and there is a need for data sharing and interaction. Data is ultimately stored through storage modules, which can be composed of one or more types of storage devices such as DDR, SDRAM, and Flash. Each CHIP in the core device is the initiator of read, write, and run operations. The data information flow can go from the core device through the data sharing module to the storage module, or from the storage module through the data sharing module to the core device; the access correspondence between the core device and the storage module can be many-to-one, one-to-many, or many-to-many.

[0065] The core device includes a number of integrated circuit chips, all of which realize data sharing and data interaction through the data sharing module and the storage module;

[0066] In this embodiment, the integrated circuit chip is an integrated circuit chip with multiple types of interfaces, and the integrated circuit chip with multiple types of interfaces includes DDR4 interface, DDR3 interface, NorFlash interface, NandFlash interface, QSPI interface, PCIE interface and SRIO interface. These interfaces are standard interfaces used in the industry and can be implemented through programmable logic software IP, or the hardware or software interface of the core device itself can be considered when selecting CPU and FPGA in the design stage. These interfaces are used for data transmission between core devices and data sharing modules. The number of interfaces set in the first interface layer set in the data port adapter is the same as the number of interfaces on the integrated circuit chip, and they are set correspondingly to each other. The data port adapter is connected to the core device upward, and all interfaces such as DDR4, DDR3, NorFlash, NandFlash, QSPI, PCIE, SRIO, etc. of the core device are realized through programmable logic software IP; the data port adapter is connected to the access arbitrator downward, and a unified AXI bus is used for interconnection.

[0067] The data sharing module is used to realize data sharing and data interaction between the core device and the data sharing module; the data sharing module adopts the data sharing module provided in the second embodiment, which can realize fast data sharing and data interaction between multi-core devices;

[0068] For interfaces without flow control signals or for which flow control signals are inconvenient to use and process, such as NorFlash, QSPI, DDR3 / 4, etc., custom flow control signals can be added. If custom flow control signals are used, the hardware of the core device needs to have a custom flow control design, and the software needs to be programmed to process the flow control signals. The flow control signals can use GPIO or other trigger signals. It should be noted that the flow control signals need to be bound to the specified interfaces. After the flow control signals are bound to the specified core device interfaces, they are connected to the AXI interface. The AXI interface has a specific flow control mechanism. The flow control signals transmitted from the core device interfaces to the data port adapter are integrated with the flow control mechanism of the AXI interface, and finally form a unified connection between the AXI interface and the backend access arbiter.

[0069] The storage module is used to store the data that the core device needs to read, write, or run.

[0070] The storage module is composed of at least one type of device among DDR memories, SDRAM memories, and Flash memories, and is used to store the data that the integrated circuit chip needs to read.

[0071] The multi-core heterogeneous data sharing system disclosed in this embodiment considers the data sharing and interaction problem from the system level. For multiple memory adapter interfaces, a one-to-one corresponding data exchange bridge is designed to support the data exchange and intercommunication between the core device and the storage device from the hardware design, support the many-to-many simultaneous access and one-to-many time-sharing access from the core device to the storage device, and improve the bandwidth utilization rate; support multiple types of core devices and storage devices, and support multiple industry standard interfaces. The data is uniformly stored in the storage module to ensure the data consistency of multi-core access.

[0072] The above specific implementation manners further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above is only the specific implementation manner of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An access arbiter for multi-core heterogeneous data sharing, characterized in that It includes several first AXI interfaces and several data exchange bridges. Each of the first AXI interfaces is used to transfer first data and second data into the data exchange bridge. The first data is the information data that needs to be transmitted received by this interface, and the second data is the control signal data sent by this interface. The first data and the second data transmitted by the same interface share the same ID, and the first data and the second data match each other through the ID. Each of the data exchange bridges is used to receive several first data and several second data, and under the action of each second data, match the corresponding first data with the data transmission interface of the corresponding memory and connect them. The data exchange bridge includes a multiplexer and an ID latch. The ID latch is used to receive the second data, and under the trigger of the second data, perform a write operation and send a signal indicating the success of the write operation to the multiplexer. The multiplexer is used to receive several of the first data, and under the action of the signal, select the corresponding first data, and based on this first data, match the data transmission interface channel with the backend memory.

2. The data sharing module for multi-core heterogeneous data sharing, characterized in that, It includes a data port adapter, a storage adapter, and the access arbiter as described in claim 1. The data port adapter is used to unify various types of data interfaces and form a unified data access port to interact with the access arbiter for data information. The access arbiter is used to arbitrate and schedule the data transmitted by the data port adapter and transmit the arbitrated and scheduled data to the storage adapter. The storage adapter is used to perform a normalization operation on the data scheduled by the access arbiter and the corresponding memory interface.

3. The data sharing module for multi-core heterogeneous data sharing according to claim 2, characterized in that, The data port adapter includes a first interface layer and an AXI port. The first interface layer contains several different types of interfaces, and each interface is connected to an AXI port. The AXI port is used to interact with the access arbiter for data. Each AXI port corresponds to the first AXI interface in the access arbiter.

4. The data sharing module for multi-core heterogeneous data sharing according to claim 3, characterized in that, The storage adapter includes an AXI interface layer and a memory driver layer. The AXI interface layer is used to interact with the access arbiter for data. The memory driver layer is used to drive the hardware chip and implement the data read / write and the operation timing of the interface.

5. The data sharing module for multi-core heterogeneous data sharing according to claim 4, characterized in that The AXI interface layer is provided with a certain number of second AXI interfaces, and the data of the second AXI interfaces provided is the same as the number of data exchange bridges provided in the access arbiter and is set in one-to-one correspondence.

6. A system for multi-core heterogeneous data sharing, characterized in that, It includes a core device, a storage module, and a data sharing module for multi-core heterogeneous data sharing as described in any one of claims 3 to 5. The core device includes several integrated circuit chips, and data sharing and data interaction are both achieved with the storage module through the data sharing module. The data sharing module is used to achieve data sharing and data interaction with the core device. The storage module is used to store the data that the core device needs to read.

7. The system for multi-core heterogeneous data sharing according to claim 6, characterized in that, The integrated circuit chip is an integrated circuit chip with multiple types of interfaces, and the multiple types of interfaces include a DDR4 interface, a DDR3 interface, a NorFlash interface, a NandFlash interface, a QSPI interface, a PCIE interface, and an SRIO interface.

8. The system for multi-core heterogeneous data sharing according to claim 7, wherein The number of interfaces set in the first interface layer is the same as the number of interfaces on the integrated circuit chip, and they are set corresponding to each other.

9. The system for multi-core heterogeneous data sharing according to claim 8, characterized in that, The storage module is composed of at least one type of device among a DDR memory, an SDRAM memory, and a Flash memory, and is used to store data that the integrated circuit chip needs to read, write, or run.

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