A front-end process migration optimization method and system for digital integrated circuits

Abstract

The present invention proposes a front-end process migration optimization method and system for digital integrated circuits. By simulating a limited number of specific circuit device size parameters as training samples for a neural network, a model of key indicators versus circuit device size parameters is constructed, and the device size parameters are quickly designed based on the model to complete the front-end process migration under the new process. The model parameters are trained using a deep neural network method to obtain the relationship between the optimization target and the device size. Compared with the brute force exhaustive method, the optimization target model can be obtained in a very short time; then the geometric programming method is used to obtain the global optimal solution in the size parameter design space. The front-end process migration of customized digital integrated circuits can be completed in the shortest possible time.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence application technology, and in particular to a front-end process migration optimization method and system for digital integrated circuits. Background Art

[0002] In recent years, for some fully customized / semi-customized digital integrated circuits, due to the characteristics of the circuits themselves or the constraints of the design goals, a considerable part of the circuits are still mainly designed manually. When it is necessary to migrate from one integrated circuit process to another integrated circuit process (it can be a different wafer manufacturer with the same process node, or a different process node of the same wafer manufacturer, or a different process node of a different foundry), due to the change of process parameters, almost all transistor size parameters in the front-end design need to be redesigned, which will consume a lot of time and manpower.

[0003] The above-mentioned process and process node refer to the minimum line width of the integrated circuit chip production process. Process migration can occur at different process nodes of the same wafer manufacturer, such as a manufacturer's 40nm process node and 28nm process node. It can also occur at different process nodes of different wafer manufacturers, such as a manufacturer's 28nm wafer process node and another manufacturer's 28nm wafer process node. The process line parameters of each wafer manufacturer are different, resulting in different circuit size parameters required to achieve the same performance. For example, if you want to design a NOR gate with a performance of 10ps based on the 28nm process node, the transistor size using the wafer manufacturer's process one and the transistor size using the wafer manufacturer's process two will be different, so each process migration is equivalent to a redesign, which is costly.

[0004] The common practice at present is to redesign under the new process, retain the circuit topology results under the original process, fix a part of the device size parameters each time, scan the size parameters of the remaining devices, and simulate the operation results under each set of size parameters through the SPICE simulation tool until the optimal size parameters corresponding to the optimization target are found; then select a part of the unoptimized devices again to scan the size parameters, and so on to complete the size parameter design of the entire circuit. In addition, there are some automated migration tools, such as WiCkeD, which first completes the migration mapping (Porting) from the old process to the new process based on the PDK of the process before and after migration and the device migration rules defined by the design engineer, and then performs SPICE simulator simulation and functional analysis, circuit performance analysis, circuit constraint checking, circuit optimization and other links to complete the device size parameter optimization under the new process.

[0005] The traditional manual dimension parameter design method is very time-consuming, and because it is impossible to exhaust all dimension parameter combinations in the design space, it is impossible to obtain a global optimal solution. The use of WiCkeD tools requires the designer to set constraints based on relevant experience in this field. If the design scope of these constraints is too narrow, it is possible that the design will only obtain a local optimal solution instead of a global optimal solution. If the design scope is too wide, it may take several days or even dozens of days to obtain a globally optimal result. Summary of the invention

[0006] The present invention solves the problem of quickly completing the front-end circuit design under a new process based on the front-end circuit design scheme under the original integrated circuit process. By using a limited number of simulation results and a neural network method, a model of key indicators relative to device size parameters is constructed, and device size parameters are quickly designed based on the model to complete the front-end process migration under the new process.

[0007] In view of the shortcomings of the prior art, the present invention proposes a front-end process migration optimization method for digital integrated circuits, which includes:

[0008] Step 1, obtaining a design toolkit for a digital integrated circuit under the original process and a target process;

[0009] Step 2: Initialize the size of the device in the digital integrated circuit according to the ratio of the minimum line width between the original process and the target process, and obtain the initial length and initial width of each device in the digital integrated circuit;

[0010] Step 3: Determine the size constraints of each device according to the initial length, the initial width and the design toolkit;

[0011] Step 4: Take multiple groups of size parameters from the set that satisfies the size constraints of all devices, perform circuit simulation on each group of size parameters, obtain the critical path delay and current value corresponding to each group of size parameters, and determine the circuit layout area under each group of size parameters according to the design rules of the integrated circuit layout under the target process and the overall layout planning;

[0012] Step 5: Using the device size corresponding to each set of size parameters as training input, and using the critical path delay, the current value, and the circuit layout area corresponding to each set of size parameters as training targets, training a digital integrated circuit process migration model based on a DNN network;

[0013] Step 6: Obtain the optimization target of process migration, substitute the digital integrated circuit process migration model into the optimization target, and combine the size constraint and use the geometric programming method to obtain the size parameters of each device corresponding to the optimization target and the target process.

[0014] The front-end process migration optimization method of the digital integrated circuit, wherein step 2 comprises:

[0015] Initial length LP of the device under the target process i The calculation process is as follows:

[0016] LP i =LS i *NL2 / NL1, (i=1,2,...M)

[0017] Among them, LP i is the initial length of the i-th device in the digital integrated circuit under the target process, LS i is the length of the i-th device in the digital integrated circuit under the original process, NL1 and NL2 are the minimum line widths corresponding to the original process and the target process respectively;

[0018] Initial device width WP under target process i The calculation process is as follows:

[0019] WP i =WS i *NL2 / NL1, (i=1,2,...M);

[0020] WP i is the initial width of the i-th device in the digital integrated circuit under the target process, WS i is the width of the i-th device in the digital integrated circuit under the original process.

[0021] The front-end process migration optimization method of the digital integrated circuit, wherein the size constraint in step 3 includes a device width constraint and a length constraint;

[0022] The length constraint is the length L of the i-th device in the digital integrated circuit i Need to meet:

[0023] (1-alpha)LP i <=L i <=(1+alpha)LP i ,

[0024] And L i >=L min , L i %G min =0

[0025] Where L min The minimum length of the device in the target process design toolkit, G min is the minimum grid point of the device in the target process design toolkit, 0 <alpha<1;

[0026] The width constraint is the length W of the i-th device in the digital integrated circuit. i Need to meet:

[0027] (1 - beta)WP i <= W i <= (1 + beta)WP i ,

[0028] and W i >= W min , W i %G min = 0

[0029] where 0 < beta < 1, and W min is the minimum width of the device in the target process design kit.

[0030] The front - end process migration optimization method for the digital integrated circuit, wherein step 4 includes a multi - group size parameter selection step, a sample delay and current value acquisition step, and a circuit layout area generation step;

[0031] The multi - group size parameter selection step includes:

[0032] Identify all critical paths in the digital integrated circuit through design experience or circuit design goals, and select K groups of size parameters from the set of {L, W} (L = {L i , i = 1, 2,... M}, W = {W i , i = 1, 2,... M}) that satisfy the constraints of step 3 as the samples to be marked, where K is a positive integer; According to the design goals and structural characteristics of the circuit, the selection of size parameters for the samples to be marked specifically includes:

[0033] If device i is designed as an inverse ratio transistor, the value - taking method for its size parameters L i , W i is:

[0034] L i = {LP i - 2S i , LP i - S i , LP i , LP i + S i , LP i + 2S i}

[0035] W i = {WP i - 2S i , WP i - S i , WP i , WP i + S i , WP i + 2Si}

[0036] Where S i is the adjustment step size of device i, and its value is the minimum grid point G min An integer multiple of ;

[0037] If device i is designed as a non-inverse ratio transistor and device i is on the critical path, then its size parameter L i , W i The value method is:

[0038] L i =LP i , W i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i}

[0039] If device i is designed as a non-inverse ratio transistor and device i is on a non-critical path, then its size parameter L i , W i The value method is: L i =LP i , then take W i ={WP i -S i ,WP i ,WP i +S i};

[0040] According to the above principles, the selection method of K group size parameters is as follows:

[0041] All size parameters select the minimum value as the first set of size parameters;

[0042] The maximum values ​​of all size parameters are selected as the second set of size parameters;

[0043] L i =LP i , W i =WP i , as the third set of size parameters;

[0044] Among all the remaining size parameter combinations, randomly select (K-3) groups of size parameters to form K groups of size parameters together with the first three groups of size parameters;

[0045] The sample delay and current value acquisition steps include:

[0046] For the K groups of size parameters, a circuit simulation tool is used to perform circuit simulation to obtain the delays D1, ..., D corresponding to the critical path. K And the current I1..., I K ;

[0047] The steps of generating the circuit layout area include:

[0048] For the selected K groups of size parameters, use the layout design tool to define the layout area model under this group of size parameters according to the design rules of the integrated circuit layout under the process and the overall layout planning:

[0049]

[0050] Among them, A ik is the layout area of ​​device i in the kth group of size parameter combinations; if device i is a reverse ratio transistor, then A ik is the device area generated by the layout design tool; if device i is a non-inverse ratio transistor, a finger threshold W is set for each type of device according to the overall layout planning. type,T , when the width W of device i i Greater than W type,T When the device is designed into a forked structure, the layout design tool is used to generate the layout area A corresponding to the forked index of this type of device when it is 1, 2, 3, ..., 10. type,f1 , A type,f2 , A type,f3 , …, A type,f10 , establish a lookup table, and obtain the device area of ​​the device i of the current non-inverse ratio tube by looking up the lookup table.

[0051] The front-end process migration optimization method of the digital integrated circuit, wherein the input layer input and output layer of the DNN network in step 5 There are n hidden layers in between.

[0052] The first hidden layer is: v1 = W1*input+b1,

[0053] The second hidden layer is: v2=W2*H1+b2,

[0054] The third hidden layer is: v3=W3*H2+b3, ......

[0055] The nth hidden layer is:

[0056] v n =W n *H n-1 +b n ,

[0057] The final output layer is:

[0058] v n+1 =W n+1 *H n +b n+1 ,

[0059] Where W i , b i are all neural network model parameters obtained through training and learning, and i is a positive integer greater than 0 and less than or equal to n+1;

[0060] The mean square error loss function is used as the loss function of the network to train the DNN network to obtain the digital integrated circuit process migration model, wherein the loss function is:

[0061]

[0062] The present invention also proposes a front-end process migration optimization system for digital integrated circuits, which includes:

[0063] An initial module, used to obtain the size of the digital integrated circuit device under the original process and the design toolkit of the target process, and initialize the size of the device in the digital integrated circuit according to the ratio of the minimum line width between the original process and the target process, and obtain the initial length and initial width of each device in the digital integrated circuit;

[0064] A simulation module, for determining the size constraints of each device according to the initial length, the initial width and the design toolkit, and taking multiple groups of size parameters from a set that satisfies the size constraints of all devices, performing circuit simulation on each group of size parameters, obtaining the critical path delay and current value corresponding to each group of size parameters, and determining the circuit layout area under each group of size parameters according to the design rules of the integrated circuit layout under the target process and the overall layout planning;

[0065] A training module is used to train a digital integrated circuit process migration model based on a DNN network, using the device size corresponding to each set of size parameters as a training input, and using the critical path delay, the current value, and the circuit layout area corresponding to each set of size parameters as training targets;

[0066] The migration module is used to obtain the optimization target of process migration, substitute the digital integrated circuit process migration model into the optimization target, and combine the size constraint and use the geometric planning system to obtain the size parameters of each device corresponding to the optimization target and the target process.

[0067] The front-end process migration optimization system of the digital integrated circuit, wherein the initial module is also used to obtain the initial length LP of the device under the target process i :

[0068] LP i =LS i *NL2 / NL1, (i=1,2,...M)

[0069] LS i is the length of the i-th device in the digital integrated circuit under the original process, NL1 and NL2 are the minimum line widths corresponding to the original process and the target process respectively;

[0070] The initial module is also used to obtain the initial width WP of the device under the target process i :

[0071] WP i =WS i *NL2 / NL1, (i=1,2,...M);

[0072] WP i is the initial width of the i-th device in the digital integrated circuit under the target process, WS i is the width of the i-th device in the digital integrated circuit under the original process.

[0073] The front-end process migration optimization system of the digital integrated circuit, wherein the size constraint includes a device width constraint and a length constraint;

[0074] The length constraint is the length L of the i-th device in the digital integrated circuit i Need to meet:

[0075] (1-alpha)LP i <=L i <=(1+alpha)LP i ,

[0076] And L i >=L min , L i %G min =0;

[0077] Where L min The minimum length of the device in the target process design toolkit, G min is the minimum grid point of the device in the target process design toolkit, 0 <alpha<1,L i %G min Indicates L i Divide by G min The remainder of

[0078] The width constraint is the length W of the i-th device in the digital integrated circuit i It is required to satisfy:

[0079] (1-beta)WP i <=W i <= (1 + beta)WP i ,

[0080] and W i >=W min , W i %G min = 0

[0081] where 0 < beta < 1, and W min is the minimum width of the device in the target process design kit

[0082] The front-end process migration optimization system of the digital integrated circuit, wherein the simulation module includes a multi-group size parameter selection module, a sample delay and current value acquisition module, and a circuit layout area generation module;

[0083] The multi-group size parameter selection module is used to identify all critical paths in the digital integrated circuit through the circuit design goal, and select K groups of size parameters from the set of {L, W} (L = {L i , i = 1, 2,... M}, W = {W i , i = 1, 2,... M}) that satisfy the constraints of step 3 as the samples to be marked, where K is a positive integer greater than or equal to 3;

[0084] The multi-group size parameter selection module is also used to obtain the size parameter value system of the samples to be marked according to the design goal and structural characteristics of the circuit, specifically:

[0085] If device i is designed as an inverse ratio transistor, its size parameters L i , W i value system is:

[0086] L i = {LP i - 2S i , LP i - S i , LP i , LP i + S i , LP i + 2S i}

[0087] W i = {WP i - 2S i , WP i - S i , WPi ,WP i +S i ,WP i +2S i}

[0088] Where S i is the adjustment step size of device i, and its value is the minimum grid point G min An integer multiple of ;

[0089] If device i is designed as a non-inverse ratio transistor and device i is on the critical path, then its size parameter L i , W i The value system is:

[0090] L i =LP i , W i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i}

[0091] If device i is designed as a non-inverse ratio transistor and is on a non-critical path, its size parameter L i , W i The value system is: L i =LP i , then take W i ={WP i -S i ,WP i ,WP i +S i};

[0092] The multiple size parameter selection modules are also used to select the size parameters L i , W i Value system, select size parameters, including:

[0093] Select the minimum value among all size parameters as the first set of size parameters;

[0094] The maximum value among all size parameters is selected as the second set of size parameters;

[0095] Select L i =LP i , W i =WP i , as the third set of size parameters;

[0096] Among all the remaining size parameter combinations, randomly select (K-3) groups of size parameters to form K groups of size parameters together with the first three groups of size parameters;

[0097] The sample delay and current value acquisition module is used to perform circuit simulation on the K group size parameters using a circuit simulation tool to obtain the delays D1, ..., D corresponding to the critical path. K And the current I1..., I K ;

[0098] The circuit layout area generation module is used to define the layout area model under the selected K group of size parameters using a layout design tool according to the design rules of the integrated circuit layout under the process and the overall layout planning as follows:

[0099]

[0100] A ik is the layout area of ​​device i in the kth group of size parameter combinations; where,

[0101] If device i is an inverse ratio tube, then A ik It is the device area generated by the layout design tool;

[0102] If device i is a non-inverse ratio transistor, according to the overall layout planning, a finger threshold W is set for each type of device. type,T , when the width W of device i i Greater than W type,T When the device is designed into a forked structure, the layout design tool is used to generate the layout area A corresponding to the forked index of this type of device when it is 1, 2, 3, ..., 10. type,f1 , A type,f2 , A type,f3 , …, A type,f10 , establish a lookup table, and obtain the device area of ​​the device i of the current non-inverse ratio tube by looking up the lookup table.

[0103] The front-end process migration optimization system of the digital integrated circuit, wherein the input layer input and output layer of the DNN network There are n hidden layers in between.

[0104] The first hidden layer is: v1 = W1*input+b1,

[0105] The second hidden layer is: v2=W2*H1+b2,

[0106] The third hidden layer is: v3=W3*H2+b3, ......

[0107] The nth hidden layer is:

[0108] v n =W n *H n-1 +b n ,

[0109] The final output layer is:

[0110] v n+1 =W n+1 *H n +b n+1 ,

[0111] Where W i , b i are all network model parameters obtained through training and learning, and i is a positive integer greater than 0 and less than or equal to n+1;

[0112] The mean square error loss function is used as the loss function of the network to train the DNN network to obtain the digital integrated circuit process migration model, wherein the loss function is:

[0113]

[0114] It can be seen from the above scheme that the advantages of the present invention are:

[0115] The deep neural network method is used to train the neural network model parameters and obtain the relationship between the optimization target and the size parameter. Compared with the brute force method, the optimization target model can be obtained in a very short time; then the geometric programming method can be used to obtain the global optimal solution in the size parameter design space. The front-end process migration of customized digital integrated circuits can be completed in the shortest possible time. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] Figure 1 is a flow chart of an embodiment of the present invention;

[0117] Figure 2 Flowchart for obtaining key metrics about device size parameter model. DETAILED DESCRIPTION

[0118] When the inventor was conducting research on process migration of customized digital integrated circuit front-end, he found that this defect in the prior art was caused by the large scale of parameter design space, long single simulation time and failure to adopt efficient parameter space search method during the process migration of customized digital integrated circuit. After studying the construction of analytical models for key indicators of the circuit (such as area, performance, power consumption, etc.), the inventor found that this defect can be solved by introducing deep learning optimization methods in the size parameter design space. By simulating a limited number of specific circuit device size parameters as training samples for the neural network, a model of key indicators versus circuit device size parameters is constructed, thereby quickly selecting circuit device size parameters that meet the design specifications in the parameter space.

[0119] The present invention includes the following key technical points:

[0120] Key point 1: A method for selecting labeled samples is proposed to obtain training data for the neural network;

[0121] Key point 2: A method for defining the layout area corresponding to a sample is proposed, which avoids the need to redesign the layout to obtain the layout area every time the size parameters are modified, and can quickly obtain the layout area corresponding to each set of size parameters;

[0122] Key point 3: By constructing a neural network, a model of key indicators relative to device size parameters is obtained, which provides a basis for subsequent parameter space search for the optimal solution.

[0123] In order to make the above features and effects of the present invention more clearly understood, the following embodiments are specifically described in detail with reference to the accompanying drawings. Figure 1 As shown, the method of the present invention comprises:

[0124] Step 1. Obtain the design toolkit of digital integrated circuits under the original process and the target process, specifically including: the minimum line width NL1 corresponding to the initial process node N1, the design parameters of all devices (transistors, diodes, resistors, capacitors, inductors, etc.) in the fully customized / semi-customized digital integrated circuits that have been optimized under the current process, including the circuit contains M devices (transistors, diodes, resistors, capacitors, inductors, etc.), the length and width of each device are LS1, WS1, ...LS M , WS M , the process node N2 to be transplanted, the minimum line width NL2 corresponding to the N2 process, and the design tool kit PDK (process design kit) corresponding to the N2 process.

[0125] Step 2: Initialize the size of the device in the digital integrated circuit according to the ratio of the minimum line width between the original process and the target process, and obtain the initial length and initial width of each device in the digital integrated circuit.

[0126] Optionally, based on the optimized device size under the original process, the size parameters of each device are initialized according to the principle of proportional reduction:

[0127] Among them, the initial length LP of the device under N2 process i The calculation process is as follows:

[0128] LP i =LS i *NL2 / NL1, (i=1,2,...M)

[0129] If LP i <L min , then LP i =L min (L min is the minimum length of the transistor / resistor specified in the new process PDK)

[0130] If LP i %G min ≠0(if LP i Divide by G min The remainder of is not 0), then (G min The minimum grid point of transistors / resistors specified in the new process PDK)

[0131] Initial device width WP under N2 process i The calculation process is as follows:

[0132] WP i =WS i *NL2 / NL1, (i=1,2,...M)

[0133] If WP i <W min , then WP i =W min (W min is the minimum length of the transistor / resistor specified in the new process PDK)

[0134] If WP i %G min ≠0, then (G min The minimum grid point of transistors / resistors specified in the new process PDK)

[0135] Step 3: Determine the size parameter constraints of each device according to the initial length, the initial width and the design toolkit. The size constraints include device width constraints and length constraints.

[0136] Device length L iNeed to meet:

[0137] (1-alpha)LP i <=L i <=(1+alpha)LP i ,

[0138] And L i >=L min , L i %G min =0

[0139] Device width W i Need to meet:

[0140] (1-beta)WP i <=W i <=(1+beta)WP i ,

[0141] And W i >=W min , W i %G min =0

[0142] Among them, alpha and beta are the first adjustment value and the second adjustment value respectively, which can be preset manually based on experience or obtained through big data analysis and machine learning, and 0 <alpha,beta<1。

[0143] L i , W i Can take all possible values ​​under the constraints

[0144] Step 4, obtain the training data set. Select K groups of size parameters according to certain rules from the set that meets the size constraints of all devices, perform circuit simulation on each group of size parameters, obtain the critical path delay and current value corresponding to each group of size parameters, and determine the circuit layout area under each group of size parameters according to the design rules of the integrated circuit layout under the target process and the overall layout planning. Including:

[0145] The size parameter selection step includes: in {L, W} (L = {L i , i=1,2,…M}, W={W i , i=1,2,…M}) to take K groups of size parameters as samples to be marked. The value of K depends on the time of simulating the circuit to be optimized using the SPICE simulation tool.

[0146] Through design experience or circuit design goals, one or more critical paths in the circuit are identified, that is, the paths with the largest combinational logic delay in the circuit, which are generally the paths with the largest number of device levels or more. According to the design goals and structural characteristics of the circuit, the selection of the size parameters of the sample to be marked follows the following principles. The case of the inverse ratio tube is applicable to 1); the case of the non-inverse ratio tube is applicable to 2), where 2) is further divided into a) and b) of whether the device i is on the critical path:

[0147] 1) If a device i is designed as an inverse ratio tube, its size parameter L i , W i The value method is:

[0148] L i = {LP i -2S i ,LP i -S i ,LP i ,LP i +S i ,LP i +2S i}

[0149] W i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i}

[0150] 2) If a device i does not need to be designed as an inverse ratio tube, its size parameter L i , W i The value method is:

[0151] L i =LP i ,

[0152] a) If device i is on the critical path, then take W i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i}

[0153] b) If device i is not on the critical path, then take W i={WP i -S i ,WP i ,WP i +S i}

[0154] Where S i is the adjustment step size of device i, and S i %G min =0, the specific value is determined according to design experience. Usually, the adjustment step size of the device on the critical path is smaller than the adjustment step size of the device on the non-critical path.

[0155] According to the above principles, the selection method of K group size parameters is as follows:

[0156] All size parameters select the minimum value as a set of size parameters;

[0157] The maximum values ​​of all size parameters are selected as the second set of size parameters;

[0158] L i =LP i , W i =WP i , as the third set of size parameters;

[0159] Among all the remaining size parameter combinations, (K-3) groups of size parameters are randomly selected to form K groups of size parameters together with the first three groups of size parameters.

[0160] The sample delay and current value acquisition step includes: for the selected K groups of size parameters, using a SPICE circuit simulation tool (such as Hspice, Virtuoso, etc.) to perform circuit simulation to obtain the delays D1, ..., D corresponding to the critical path K And the current I1..., I K .

[0161] The circuit layout area generation step includes: for the selected K groups of size parameters, using a layout design tool (such as Virtuoso, etc.), according to the design rules of the integrated circuit layout under the process and the overall layout planning, defining the layout area model under the group of size parameters:

[0162]

[0163] Among them, A ikis the layout area of ​​device i in the kth group of size parameter combinations. Design rules refer to the layout design rules that the wafer manufacturer sets for users based on its production process line parameters, such as the minimum spacing between two lines, the minimum line width of each layer of lines, etc.; the overall layout planning refers to the overall planning when designing the integrated circuit layout, such as the size of each unit, the direction of the routing, the number of metal layers occupied by the routing, etc., and the layout is designed according to the overall planning. The integrated circuit layout is the lowest level of integrated circuit design, which refers to the design of transistors, resistors and other devices of different sizes, represented by some multi-layer geometric shapes. Finally, the wafer manufacturer designs the integrated circuit chip according to the various collection shapes and connections in this layout.

[0164] In order to quickly obtain the area value of the layout, the following area calculation model is defined:

[0165] 1) If device i is a reverse ratio tube, then A ik It is the device area generated by the layout design tool;

[0166] 2) If device i is a non-inverse ratio transistor, according to the overall layout planning, set a finger threshold W for each type of device type,T (type indicates the device type, such as PMOS, NMOS, Mx RESISTOR, etc.), when the width W of device i i Greater than W type,T When the device is designed as a finger structure, the layout design tool is used to generate the layout area A corresponding to the finger index of this type of device when it is 1, 2, 3, ..., 10. type,f1 , A type,f2 , A type,f3 , …, A type,f10 , establish a lookup table and define the layout area of ​​each device i as:

[0167]

[0168] In summary, we select K groups of size parameters and the critical path delay D, area A and current I corresponding to each group of size parameters to form a training data set.

[0169] Step 5: Take each set of size parameters as training input, and take the critical path delay, current value and circuit layout area corresponding to each set of size parameters as training targets to train the digital integrated circuit process migration model based on the DNN network. Figure 2 As shown:

[0170] Step 51: construct a multi-layer deep neural network and initialize the number of training times;

[0171] Step 52: The neural network calculates forward and obtains the output

[0172] Step 53: According to With the actual value y, the output Calculate the loss function Loss with the actual value y;

[0173] Step 54, calculate the gradient of loss Loss with respect to each network parameter;

[0174] Step 55: Update the parameters of the neural network according to the gradient of Loss for each network parameter, and increase the number of training times by 1;

[0175] Step 56, determining whether the number of training times reaches the preset number of training times, if so, executing step 57, otherwise executing step 52 until the number of training times reaches the preset number of training times;

[0176] Step 57: Save the parameters of the current neural network.

[0177] Optionally, the multi-layer deep neural network is a DNN network, and the input layer input of the network is the length and width parameters L1, W1, ...L of the device. M , W M , a total of 2M, the output layer of the network It contains three nodes, namely the delay value D, area value A and current value I of the critical path, namely

[0178] There are n hidden layers between the input layer and the output layer.

[0179] The first hidden layer is: v1 = W1*input+b1,

[0180] The second hidden layer is: v2=W2*H1+b2,

[0181] The third hidden layer is: v3=W3*H2+b3, ......

[0182] The nth hidden layer is:

[0183] v n =W n *H n-1 +b n ,

[0184] The final output layer is:

[0185] v n+1 =W n+1 *H n +b n+1 ,

[0186] Where W i , b i are all neural network model parameters obtained through training and learning, and i is a positive integer greater than 0 and less than or equal to n+1;

[0187] according to Figure 2 The process shown obtains the model expressions of the critical path delay D, area value A and current value I with respect to the device size parameters.

[0188] Among them, the network loss function Loss is defined as the mean square error loss function, that is,

[0189]

[0190] represents {delay D, area A, current I} calculated using the above formula; y represents the K groups {delay D, area A, current I} obtained in step 4.

[0191] The gradient descent method is used to calculate the gradient of Loss for each neural network model parameter, and the gradient of each neural network model parameter is updated to train the DNN network. After multiple trainings, the optimization targets such as critical path delay D, area A, and current I are obtained for the circuit device size parameters {L1, W1, ...L M , W M} model:

[0192] D = f D (L1, W1, ...L M , W M )

[0193] A=f A (L1, W1, ...L M , W M )

[0194] I=f I (L1, W1, ...L M , W M )

[0195] Step 6: Obtain the optimization target of process migration. The optimization target of process migration is determined by the requirements, including: if the circuit focuses on the overall implementation performance, the optimization target can be set as: min{D}.

[0196] If the circuit is to use the smallest possible layout area, the optimization target can be set to: min{A}.

[0197] If the circuit is to achieve low power consumption, the optimization target can be set as: min{I}.

[0198] In addition, if the design goal of the circuit is a compromise between several factors, the optimization object can be set as the product of several factors. For example, if you want to optimize performance and area, you can set the optimization goal to: min{D*A}; if you want to optimize performance and power consumption, you can set the optimization goal to: min{D*I}.

[0199] Step 7: Substitute the digital integrated circuit process migration model into the optimization target, and combine it with the size constraint, using a geometric programming method to obtain the size parameters of each device corresponding to the optimization target and the target process.

[0200] Substitute the model obtained in step 5 into the optimization target set in step 6, combine it with the size parameter constraints defined in step 3, and use the geometric programming method to obtain the device size parameter set {LO1, WO1, ...LO1} corresponding to the optimization target and the target process. M , WO M}.

[0201] For each device i,

[0202] If LO i %G min ≠0, then

[0203] If WO i %G min ≠0, then

[0204] where LO i and WO i are the length and width of the device under the target process, and the LO on the right side of the equal sign i and WO i It represents the set of device size parameters calculated using the geometric programming method. However, these parameters are usually values ​​with many decimal places, and the LO that can be manufactured in the integrated circuit process is i and WO i It is not a continuous value, but should be the minimum grid point G in the process min An integer multiple of , so this formula is used here to calculate the LO i and WO i Value, converted to G min An integer multiple of .

[0205] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0206] The present invention also proposes a front-end process migration optimization system for digital integrated circuits, comprising:

[0207] An initial module, used to obtain the size of the digital integrated circuit device under the original process and the design toolkit of the target process, and initialize the size of the device in the digital integrated circuit according to the ratio of the minimum line width between the original process and the target process, and obtain the initial length and initial width of each device in the digital integrated circuit;

[0208] A simulation module, for determining the size constraints of each device according to the initial length, the initial width and the design toolkit, and taking multiple groups of size parameters from a set that satisfies the size constraints of all devices, performing circuit simulation on each group of size parameters, obtaining the critical path delay and current value corresponding to each group of size parameters, and determining the circuit layout area under each group of size parameters according to the design rules of the integrated circuit layout under the target process and the overall layout planning;

[0209] A training module is used to train a digital integrated circuit process migration model based on a DNN network, using the device size corresponding to each set of size parameters as a training input, and using the critical path delay, the current value, and the circuit layout area corresponding to each set of size parameters as training targets;

[0210] The migration module is used to obtain the optimization target of process migration, substitute the digital integrated circuit process migration model into the optimization target, and combine the size constraint and use the geometric planning system to obtain the size parameters of each device corresponding to the optimization target and the target process.

[0211] The front-end process migration optimization system of the digital integrated circuit, wherein the initial module is also used to obtain the initial length LP of the device under the target process i :

[0212] LP i =LS i *NL2 / NL1, (i=1,2,...M)

[0213] LS i is the length of the i-th device in the digital integrated circuit under the original process, NL1 and NL2 are the minimum line widths corresponding to the original process and the target process respectively;

[0214] The initial module is also used to obtain the initial width WP of the device under the target process i :

[0215] WP i =WS i *NL2 / NL1, (i=1,2,...M);

[0216] WPi is the initial width of the i-th device in the digital integrated circuit under the target process, WS i is the width of the i-th device in the digital integrated circuit under the original process.

[0217] The front-end process migration optimization system of the digital integrated circuit, wherein the size constraint includes a device width constraint and a length constraint;

[0218] The length constraint is the length L of the i-th device in the digital integrated circuit i needs to satisfy:

[0219] (1-alpha)LP i <= L i <= (1+alpha)LP i ,

[0220] and L i >= L min , L i %G min = 0;

[0221] where L min is the minimum length of the device in the target process design kit, G min is the minimum grid point of the device in the target process design kit, 0 < alpha < 1, L i %G min represents the remainder of L i divided by G min ;

[0222] The width constraint is the length W of the i-th device in the digital integrated circuit i needs to satisfy:

[0223] (1-beta)WP i <= W i <= (1+beta)WP i ,

[0224] and W i >= W min , W i %G min = 0

[0225] where, 0 < beta < 1, where W min is the minimum width of the device in the target process design kit.

[0226] The front-end process migration optimization system of the digital integrated circuit, wherein the simulation module includes a multi-group size parameter selection module, a sample delay and current value acquisition module, and a circuit layout area generation module;

[0227] The multi-group size parameter selection module is used to identify all critical paths in the digital integrated circuit according to the circuit design target, and in the {L,W} (L={L i , i=1,2,…M}, W={W i , i=1,2,…M}) set, take K groups of size parameters as samples to be labeled, where K is a positive integer greater than or equal to 3;

[0228] The multiple groups of size parameter selection modules are also used to obtain the size parameter value system of the sample to be marked according to the design objectives and structural characteristics of the circuit, specifically for:

[0229] If device i is designed as an inverse ratio tube, its size parameter L i , W i The value system is:

[0230] L i = {LP i -2S i ,LP i -S i ,LP i ,LP i +S i ,LP i +2S i}

[0231] W i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i}

[0232] Where S i is the adjustment step size of device i, and its value is the minimum grid point G min An integer multiple of ;

[0233] If device i is designed as a non-inverse ratio transistor and device i is on the critical path, then its size parameter L i , W i The value system is:

[0234] L i =LP i , W i ={WP i -2S i ,WP i -S i ,WP i ,WP i+S i ,WP i +2S i}

[0235] If device i is designed as a non-inverse ratio transistor and is on a non-critical path, its size parameter L i , W i The value system is: L i =LP i , then take W i ={WP i -S i ,WP i ,WP i +S i};

[0236] The multiple size parameter selection modules are also used to select the size parameters L i , W i Value system, select size parameters, including:

[0237] Select the minimum value among all size parameters as the first set of size parameters;

[0238] The maximum value among all size parameters is selected as the second set of size parameters;

[0239] Select L i =LP i , W i =WP i , as the third set of size parameters;

[0240] Among all the remaining size parameter combinations, randomly select (K-3) groups of size parameters to form K groups of size parameters together with the first three groups of size parameters;

[0241] The sample delay and current value acquisition module is used to perform circuit simulation on the K group size parameters using a circuit simulation tool to obtain the delays D1, ..., D corresponding to the critical path. K And the current I1..., I K ;

[0242] The circuit layout area generation module is used to define the layout area model under the selected K group of size parameters using a layout design tool according to the design rules of the integrated circuit layout under the process and the overall layout planning as follows:

[0243]

[0244] A ik is the layout area of ​​device i in the kth group of size parameter combinations; where,

[0245] If device i is an inverse ratio tube, then Aik It is the device area generated by the layout design tool;

[0246] If device i is a non-inverse ratio transistor, according to the overall layout planning, a finger threshold W is set for each type of device. type,T , when the width W of device i i Greater than W type,T When the device is designed into a forked structure, the layout design tool is used to generate the layout area A corresponding to the forked index of this type of device when it is 1, 2, 3, ..., 10. type,f1 , A type,f2 , A type,f3 , …, A type,f10 , establish a lookup table, and obtain the device area of ​​the device i of the current non-inverse ratio tube by looking up the lookup table.

[0247] The front-end process migration optimization system of the digital integrated circuit, wherein the input layer input and output layer of the DNN network There are n hidden layers in between.

[0248] The first hidden layer is: v1 = W1*input+b1,

[0249] The second hidden layer is: v2=W2*H1+b2,

[0250] The third hidden layer is: v3=W3*H2+b3, ......

[0251] The nth hidden layer is:

[0252] v n =W n *H n-1 +b n ,

[0253] The final output layer is:

[0254] v n+1 =W n+1 *H n +b n+1 ,

[0255] Where W i , b i are all network model parameters obtained through training and learning, and i is a positive integer greater than 0 and less than or equal to n+1;

[0256] The mean square error loss function is used as the loss function of the network to train the DNN network to obtain the digital integrated circuit process migration model, wherein the loss function is:

[0257]

Claims

1. A front-end process migration optimization method for digital integrated circuits, characterized in that: include: Step 1, obtaining a design toolkit for a digital integrated circuit under the original process and a target process; Step 2: Initialize the size of the device in the digital integrated circuit according to the ratio of the minimum line width between the original process and the target process, and obtain the initial length and initial width of each device in the digital integrated circuit; Step 3: Determine the size constraints of each device according to the initial length, the initial width and the design toolkit; Step 4: Take multiple groups of size parameters from the set that satisfies the size constraints of all devices, perform circuit simulation on each group of size parameters, obtain the critical path delay and current value corresponding to each group of size parameters, and determine the circuit layout area under each group of size parameters according to the design rules of the integrated circuit layout under the target process and the overall layout planning; Step 5: Using each set of size parameters as training input, and using the critical path delay, the current value, and the circuit layout area corresponding to each set of size parameters as training targets, training a digital integrated circuit process migration model based on a DNN network; Step 6: Obtain the optimization target of process migration, substitute the digital integrated circuit process migration model into the optimization target, and combine the size constraint and use the geometric programming method to obtain the size parameters of each device corresponding to the optimization target and the target process.

2. The front-end process migration optimization method of a digital integrated circuit according to claim 1, characterized in that: This step 2 includes: Initial length LP of the device under the target process i The calculation process is as follows: LP i =LS i *NL2 / NL1,(i=1,2,...M) LS i is the length of the i-th device in the digital integrated circuit under the original process, NL1 and NL2 are the minimum line widths corresponding to the original process and the target process respectively; Initial device width WP under target process i The calculation process is as follows: WP i =WS i *NL2 / NL1,(i=1,2,...M); WP i is the initial width of the i-th device in the digital integrated circuit under the target process, WS i is the width of the i-th device in the digital integrated circuit under the original process.

3. The front-end process migration optimization method of digital integrated circuit according to claim 2, characterized in that: In step 3, the size constraint includes a device width constraint and a length constraint; The length constraint is the length L of the i-th device in the digital integrated circuit i Need to meet: (1-alpha)LP i <=L i <=(1+alpha)LP i , And L i >=L min , L i %G min =0 Where L min The minimum length of the device in the target process design toolkit, G min is the minimum grid point of the device in the target process design toolkit, 0 <alpha<1,L i %G min Indicates L i Divide by G min The remainder of The width constraint is the length W of the i-th device in the digital integrated circuit. i Need to meet: (1-beta)WP i <=IN i <=(1+beta)WP i , and W i >= W min , W i %G min = 0 where 0 < beta < 1, and W min is the minimum width of the device in the target process design kit.

4. The front-end process migration optimization method of a digital integrated circuit as claimed in claim 3, characterized in that: The step 4 includes a step of selecting multiple sets of size parameters, a step of obtaining sample delay and current values, and a step of generating a circuit layout area; The steps of selecting multiple sets of size parameters include: Identify all critical paths in digital integrated circuits through circuit design goals, and then find the paths that meet the constraints of step 3: {L,W} (L = {L i , i=1,2,…M}, W={W i , i=1,2,…M}) set, as the sample to be labeled, where K is a positive integer greater than or equal to 3; according to the design objectives and structural characteristics of the circuit, the size parameters of the sample to be labeled are selected specifically including: If device i is designed as an inverse ratio tube, its size parameter L i , W i The value method is: L i ={LP i -2S i ,LP i -S i ,LP i ,LP i +S i ,LP i +2S i } IN i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i } Where S i is the adjustment step size of device i, and its value is the minimum grid point G min An integer multiple of ; If device i is designed as a non-inverse ratio transistor and is on the critical path, its size parameter L i , W i The value method is: L i =LP i ,IN i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i } If device i is designed as a non-inverse ratio transistor and device i is on a non-critical path, then its size parameter L i , W i The value method is: L i =LP i , then take W i ={WP i -S i ,WP i ,WP i +S i }; According to the above principles, the selection method of K group size parameters is as follows: All size parameters select the minimum value as the first set of size parameters; The maximum values ​​of all size parameters are selected as the second set of size parameters; L i =LP i , W i =WP i , as the third set of size parameters; Among all the remaining size parameter combinations, randomly select (K-3) groups of size parameters to form K groups of size parameters together with the first three groups of size parameters; The sample delay and current value acquisition steps include: For the K groups of size parameters, a circuit simulation tool is used to perform circuit simulation to obtain the delays D1, ..., D corresponding to the critical path. K And the current I1..., I K ; The steps of generating the circuit layout area include: For the selected K groups of size parameters, use the layout design tool to define the layout area model under this group of size parameters according to the design rules of the integrated circuit layout under the process and the overall layout planning: Among them, A ik is the layout area of ​​device i in the kth group of size parameter combinations; if device i is a reverse ratio transistor, then A ik It is the device area generated by the layout design tool; If device i is a non-inverse ratio transistor, according to the overall layout planning, a finger threshold W is set for each type of device. type,T , when the width W of device i i Greater than W type,T When the device is designed into a forked structure, the layout design tool is used to generate the layout area A corresponding to the forked index of this type of device when it is 1, 2, 3, ..., 10. type,f1 , A type,f2 , A type,f3 , …, A type,f10 , establish a lookup table, and obtain the device area of ​​the device i of the current non-inverse ratio tube by looking up the lookup table.

5. The front-end process migration optimization method of digital integrated circuit according to claim 4, characterized in that: The input layer and output layer of the DNN network in step 5 There are n hidden layers in between. The first hidden layer is: v1 = W1*input+b1, The second hidden layer is: v2=W2*H1+b2, The third hidden layer is: v3=W3*H2+b3, ...... The nth hidden layer is: v n =W n *H n-1 +b n , The final output layer is: v n+1 =W n+1 *H n +b n+1 , Where W i , b i are all network model parameters obtained through training and learning, and i is a positive integer greater than 0 and less than or equal to n+1; The mean square error loss function is used as the loss function of the network to train the DNN network to obtain the digital integrated circuit process migration model, wherein the loss function is:

6. A front-end process migration optimization system for digital integrated circuits, characterized in that: include: An initial module, used to obtain the size of the digital integrated circuit device under the original process and the design toolkit of the target process, and initialize the size of the device in the digital integrated circuit according to the ratio of the minimum line width between the original process and the target process, and obtain the initial length and initial width of each device in the digital integrated circuit; A simulation module, for determining the size constraints of each device according to the initial length, the initial width and the design toolkit, and taking multiple groups of size parameters from a set that satisfies the size constraints of all devices, performing circuit simulation on each group of size parameters, obtaining the critical path delay and current value corresponding to each group of size parameters, and determining the circuit layout area under each group of size parameters according to the design rules of the integrated circuit layout under the target process and the overall layout planning; A training module is used to train a digital integrated circuit process migration model based on a DNN network, using the device size corresponding to each set of size parameters as a training input, and using the critical path delay, the current value, and the circuit layout area corresponding to each set of size parameters as training targets; The migration module is used to obtain the optimization target of process migration, substitute the digital integrated circuit process migration model into the optimization target, and combine the size constraint and use the geometric planning system to obtain the size parameters of each device corresponding to the optimization target and the target process.

7. The front-end process migration optimization system of digital integrated circuit according to claim 6, characterized in that: The initial module is also used to obtain the initial length LP of the device under the target process. i : LP i =LS i *NL2 / NL1,(i=1,2,...M) LS i is the length of the i-th device in the digital integrated circuit under the original process, NL1 and NL2 are the minimum line widths corresponding to the original process and the target process respectively; The initial module is also used to obtain the initial width WP of the device under the target process i : WP i =WS i *NL2 / NL1,(i=1,2,...M); WP i is the initial width of the i-th device in the digital integrated circuit under the target process, WS i is the width of the i-th device in the digital integrated circuit under the original process.

8. The front-end process migration optimization system for digital integrated circuits according to claim 7, characterized in that: The size constraint includes a device width constraint and a length constraint; The length constraint is the length L of the i-th device in the digital integrated circuit i Need to meet: (1-alpha)LP i <=L i <=(1+alpha)LP i , And L i >=L min , L i %G min =0; Where L min The minimum length of the device in the target process design toolkit, G min is the minimum grid point of the device in the target process design toolkit, 0 <alpha<1,L i %G min Indicates L i Divide by G min The remainder of The width constraint is the length W of the i-th device in the digital integrated circuit. i Need to meet: (1-beta)WP i <=IN i <=(1+beta)WP i , and W i >= W min , W i %G min = 0 where 0 < beta < 1, where W min is the minimum width of the device in the target process design kit.

9. The front-end process migration optimization system of digital integrated circuit according to claim 8, characterized in that: The simulation module includes multiple groups of size parameter selection modules, sample delay and current value acquisition modules and circuit layout area generation modules; The multi-group size parameter selection module is used to identify all critical paths in the digital integrated circuit through the circuit design target, and in the {L,W} (L={L i , i=1,2,…M}, W={W i , i=1,2,…M}) set, take K groups of size parameters as samples to be labeled, where K is a positive integer greater than or equal to 3; The multiple groups of size parameter selection modules are also used to obtain the size parameter value system of the sample to be marked according to the design objectives and structural characteristics of the circuit, specifically for: If device i is designed as an inverse ratio tube, its size parameter L i , W i The value system is: L i ={LP i -2S i ,LP i -S i ,LP i ,LP i +S i ,LP i +2S i } IN i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i } Where S i is the adjustment step size of device i, and its value is the minimum grid point G min An integer multiple of ; If device i is designed as a non-inverse ratio transistor and device i is on the critical path, then its size parameter L i , W i The value system is: L i =LP i ,IN i ={WP i -2S i ,WP i -S i ,WP i ,WP i +S i ,WP i +2S i } If device i is designed as a non-inverse ratio transistor and is on a non-critical path, its size parameter L i , W i The value system is: L i =LP i , then take W i ={WP i -S i ,WP i ,WP i +S i }; The multiple size parameter selection modules are also used to select the size parameters L i , W i Value system, select size parameters, including: Select the minimum value among all size parameters as the first set of size parameters; The maximum value among all size parameters is selected as the second set of size parameters; Select L i =LP i , W i =WP i , as the third set of size parameters; Among all the remaining size parameter combinations, randomly select (K-3) groups of size parameters to form K groups of size parameters together with the first three groups of size parameters; The sample delay and current value acquisition module is used to perform circuit simulation on the K group size parameters using a circuit simulation tool to obtain the delays D1, ..., D corresponding to the critical path. K And the current I1..., I K ; The circuit layout area generation module is used to define the layout area model under the selected K group of size parameters using a layout design tool according to the design rules of the integrated circuit layout under the process and the overall layout planning as follows: A ik is the layout area of ​​device i in the kth group of size parameter combinations; where, If device i is an inverse ratio tube, then A ik It is the device area generated by the layout design tool; If device i is a non-inverse ratio transistor, according to the overall layout planning, a finger threshold W is set for each type of device. type,T , when the width W of device i i Greater than W type,T When the device is designed into a forked structure, the layout design tool is used to generate the layout area A corresponding to the forked index of this type of device when it is 1, 2, 3, ..., 10. type,f1 , A type,f2 , A type,f3 , …, A type,f10 , establish a lookup table, and obtain the device area of ​​the device i of the current non-inverse ratio tube by looking up the lookup table.

10. The front-end process migration optimization system of digital integrated circuit according to claim 9, characterized in that: The input layer and output layer of the DNN network There are n hidden layers in between. The first hidden layer is: v1 = W1*input+b1, The second hidden layer is: v2=W2*H1+b2, The third hidden layer is: v3=W3*H2+b3, ...... The nth hidden layer is: v n =W n *H n-1 +b n , The final output layer is: v n+1 =W n+1 *H n +b n+1 , Where W i , b i are all network model parameters obtained through training and learning, and i is a positive integer greater than 0 and less than or equal to n+1; The mean square error loss function is used as the loss function of the network to train the DNN network to obtain the digital integrated circuit process migration model, wherein the loss function is:

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