State detection method and state detection device

Abstract

The present invention provides a state detection method and a state detection device for detecting the state of a memory storage device. The method comprises: establishing a connection with the memory storage device; executing a first detection program on the memory storage device to perform initial error classification on the memory storage device; executing a second detection program on the memory storage device according to the classification result of the initial error classification; and providing detection data according to the detection result of the second detection program, wherein the detection data reflects the defect state of the memory storage device. In this way, the state detection efficiency of the memory storage device can be effectively improved.

Description

Technical Field

[0001] The present invention relates to a defect detection technology, and in particular to a state detection method and a state detection device. Background Art

[0002] Some types of memory storage devices (such as USB flash drives) are mainly produced through packaging procedures, and the packaging procedures may include system in package (SIP) packaging. However, the devices produced by SIP packaging are in a closed state after forming, and developers or testers cannot directly measure and analyze the electrical properties of the product surface. Therefore, when these types of memory storage devices encounter problems and become defective products during processing and verification before shipment, these defective products often cannot be directly analyzed for errors in the processing and verification factory, and the defective products must be shipped back to the original factory for manual analysis and error handling by the original factory engineers. However, the transportation of defective products often takes a lot of time, and even in the case of a large number of defective products, it may cause product shipment delays. Summary of the invention

[0003] In view of this, the present invention provides a state detection method and a state detection device, which can effectively improve the state detection efficiency of a memory storage device.

[0004] An embodiment of the present invention provides a state detection method for detecting a defect state of a memory storage device. The state detection method comprises: establishing a connection with the memory storage device; executing a first detection procedure on the memory storage device to perform an initial error classification on the memory storage device; executing a second detection procedure on the memory storage device according to the classification result of the initial error classification; and providing detection data according to the detection result of the second detection procedure, wherein the detection data reflects the defect state of the memory storage device.

[0005] An embodiment of the present invention further provides a state detection device for detecting a defect state of a memory storage device. The state detection device includes a connection interface circuit and a processor. The connection interface circuit is used to connect to the memory storage device. The processor is connected to the connection interface circuit. The processor is used to: establish a connection between the state detection device and the memory storage device via the connection interface circuit; execute a first detection program on the memory storage device to perform an initial error classification on the memory storage device; execute a second detection program on the memory storage device according to the classification result of the initial error classification; and provide detection data according to the detection result of the second detection program, wherein the detection data reflects the defect state of the memory storage device.

[0006] Based on the above, after establishing a connection with the memory storage device, the first detection procedure can be first executed on the memory storage device to perform an initial error classification on the memory storage device. Later, based on the classification result of the initial error classification, the second detection procedure can be automatically executed on the memory storage device. Based on the detection result of the second detection procedure, detection data can also be automatically provided to reflect the defect status of the memory storage device. In this way, the efficiency of the status detection of the memory storage device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a state detection system according to an embodiment of the present invention;

[0008] Figure 2 FIG. 4 is a flow chart of a state detection method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0010] Figure 1 is a schematic diagram of a state detection system according to an embodiment of the present invention. Figure 1 The state detection system (also referred to as the state detection system) 10 may include a state detection device (also referred to as a defect state detection device) 11 and a memory storage device 12. For example, the state detection device 11 may be a tablet computer, a notebook computer, a personal computer, an industrial computer, or a server, and other electronic devices that can be connected to the memory storage device 12 and access the memory storage device 12. In addition, the memory storage device 12 may be a USB flash drive, a memory card, or a solid state drive (SSD) and other memory storage devices for storing data.

[0011] In one embodiment, the memory storage device 12 may include one or more controllers and one or more memory modules. The controller is used to control or access the memory modules. Each memory module may include a rewritable non-volatile memory module. For example, each memory module may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules or other memory modules with the same characteristics.

[0012] After establishing the connection between the state detection device 11 and the memory storage device 12, the state detection device 11 can automatically detect the defect state of the memory storage device 12. For example, the state detection device 11 can automatically perform various detection procedures such as software state detection, hardware state detection, process defect detection and / or wear state detection on the memory module inside the memory storage device 12. After completing the relevant detection procedures, the state detection device 11 can automatically provide detection data related to the memory storage device 12. This detection data can reflect the defect state of the memory storage device 12, such as software defects, hardware defects, process defects and / or wear state of the memory module inside the memory storage device 12, and other information related to the health of the memory storage device 12 itself and / or software / hardware defects.

[0013] The state detection device 11 includes a storage circuit 101, a connection interface circuit 102 and a processor 103. The storage circuit 101 is used to store data. For example, the storage circuit 101 may include a volatile storage circuit and a non-volatile storage circuit. The volatile storage circuit is used to store data volatilely. For example, the volatile storage circuit may include a random access memory (RAM) or a similar volatile storage medium. The non-volatile storage circuit is used to store data non-volatilely. For example, the non-volatile storage circuit may include a read-only memory (ROM), a solid state drive and / or a traditional hard disk (HDD) or a similar non-volatile storage medium.

[0014] The connection interface circuit 102 is used to connect the state detection device 11 to the memory storage device 12 . For example, the connection interface circuit 102 may be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Peripheral Component Interconnect Express (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards.

[0015] The processor 103 is connected to the storage circuit 101 and the connection interface circuit 102. The processor 103 can access the memory storage device 12 or communicate with the memory storage device 12 via the connection interface circuit 102. For example, the processor 103 can issue data access instructions such as write, read or delete via the connection interface circuit 102 to instruct the memory storage device 12 to access the memory module inside the memory storage device 12. In addition, the processor 103 can receive data returned by the memory storage device 12 via the connection interface circuit 102. For example, the processor 103 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (Digital Signal Processor, DSP), programmable controllers, application specific integrated circuits (Application Specific Integrated Circuits, ASIC), programmable logic devices (Programmable Logic Device, PLD) or other similar devices or combinations of these devices.

[0016] Figure 2 FIG. 1 is a flow chart of a state detection method according to an embodiment of the present invention. Figure 1 and Figure 2 In step S201, the processor 103 establishes a connection between the state detection device 11 and the memory storage device 12 via the connection interface circuit 102. For example, the processor 103 may perform at least one handshake procedure with the memory storage device 12 via the connection interface circuit 102 to establish the connection.

[0017] In step S202, the processor 103 may execute at least one detection procedure (also referred to as a first detection procedure) on the memory storage device 12 to perform error classification (also referred to as initial error classification) on the memory storage device 12. For example, Table 1 below presents detection items that may be included in the first detection procedure in some embodiments, and the detection items that may be included in the first detection procedure are not limited thereto. In step S202, at least some of the detection items listed in Table 1 below may be executed.

[0018] Table 1

[0019]

[0020] For example, in detection item 1-1, the processor 103 may issue a read instruction to the memory storage device 12 to instruct the memory storage device 12 to read the device identification code stored inside the memory storage device 12. For example, this device identification code may reflect the device identification code of a specific circuit module (such as a controller or a memory module) inside the memory storage device 12. Then, the processor 103 may verify the device identification code returned by the memory storage device 12.

[0021] In detection item 1-2, the processor 103 may issue a control instruction to the memory storage device 12 to instruct the memory storage device 12 to adjust its connection interface parameters. For example, according to the control instruction, the memory storage device 12 may switch the input and output (IO) interface for connecting to the state detection device 11, for example, from IO interface 1 to IO interface 2. Then, the processor 103 may detect whether the IO interface of the memory storage device 12 can be switched normally.

[0022] In detection items 1-3, the processor 103 may analyze or depict the eye diagram information of the data signal transmitted between the state detection device 11 and the memory storage device 12. This eye diagram information may reflect the quality of the data signal. For example, when the eye diagram information shows that the larger the eye width and / or eye height of the data signal is, the better the quality of the data signal is. In addition, the eye diagram information may also carry information such as the jitter amount of the data signal.

[0023] In detection items 1-4, the processor 103 may issue a read instruction to the memory storage device 12 to instruct the memory storage device 12 to report the device type (e.g., USB 3.0, USB 2.0, or USB 1.0, etc.) of the memory storage device 12. Then, the processor 103 may verify the device type reported by the memory storage device 12.

[0024] In test items 1-5, the processor 103 may issue a read instruction and / or a write instruction to the memory storage device 12 to instruct the memory storage device 12 to perform a simple read and write test on its internal memory module. For example, in this read and write test, the processor 103 may verify the correctness of the read and / or written data of the memory storage device 12.

[0025] In step S202, according to the detection result of the first detection procedure, the processor 103 may perform initial error classification on the memory storage device 12. For example, according to different detection results of the memory storage device 12 by different detection items in Table 1 above, the memory storage device 12 may be classified into one of multiple error classifications.

[0026] In step S203, the processor 103 can perform a further detection program (also referred to as the second detection program) to the memory storage device according to the classification result of the initial error classification. For example, in one embodiment, the processor 103 can automatically select at least one detection item associated with the classification result from a plurality of candidate detection items according to the classification result of the initial error classification. For example, in response to the classification result of the initial error classification being the first classification result, the processor 103 can automatically select at least one detection item (also referred to as the first detection item) associated with the first classification result from the plurality of candidate detection items. Or, in response to the classification result of the initial error classification being the second classification result, the processor 103 can automatically select at least one detection item (also referred to as the second detection item) associated with the second classification result from the plurality of candidate detection items. In particular, the project composition of the first detection item may be different from the project composition of the second detection item. Then, in the second detection program, the processor 103 can detect the memory storage device 12 according to the selected at least one detection item.

[0027] For example, Table 2 below presents the detection items (ie, the candidate detection items) that may be included in the second detection procedure in some embodiments, and the detection items that may be included in the second detection procedure are not limited thereto. In step S203, at least some of the detection items listed in Table 2 below may be executed.

[0028] Table 2

[0029]

[0030] For example, in detection item 2-1, the processor 103 may change the ambient temperature of the environment in which the memory storage device 12 is located through a temperature control device. Alternatively, the processor 103 may increase or decrease the temperature of the memory storage device 12 itself through a specific temperature control mechanism. For example, the processor 103 may adjust the temperature of the memory storage device 12 by adjusting the clock frequency of the memory storage device 12. Then, the processor 103 may detect the state (e.g., read / write stability) of the memory storage device 12 when the temperature undergoes a high temperature and low temperature cycle.

[0031] In detection item 2-2, the processor 103 may perform surface etching on the memory storage device 12 via a process device (e.g., an etching machine). This surface etching may form an exposed area on the originally closed surface of the memory storage device 12 by etching. Part of the objects inside the memory storage device 12 that were originally covered by the outer shell may be exposed in this exposed area. Then, the processor 103 may detect the exposed objects.

[0032] In detection item 2-3, the processor 103 may perform an optical penetration test on the memory storage device 12 via an optical detection device (eg, an X-ray machine). The optical penetration test may detect the portion of the memory storage device 12 that is enclosed in the housing and not exposed in a non-destructive manner.

[0033] In detection item 2-4, the processor 103 may perform an ultrasonic scan on the memory storage device 12 via an ultrasonic scanning device. The ultrasonic scan may also detect the part of the memory storage device 12 that is enclosed in the housing and not exposed in a non-destructive manner.

[0034] In test items 2-5, the processor 103 can perform electronic data testing on various electronic data such as resistance, capacitance, current or voltage of the memory storage device 12 via an electronic data testing instrument (such as an oscilloscope). This electronic data testing can reflect the electrical status of some electronic components in the memory storage device 12.

[0035] In test item 2-6, the processor 103 may perform an appearance integrity test on the memory storage device 12 via an image acquisition device (e.g., a camera). This appearance integrity test may be used to detect whether the appearance of the memory storage device 12 has specific defects (e.g., damage or abnormal welding points, etc.).

[0036] In other words, compared to the first detection procedure, in step S203, the second detection procedure executed may include using more specialized detection instruments to perform destructive or non-destructive detection on the inside and / or outside of the memory storage device 12 and / or change the detection environment of the memory storage device 12 (for example, adjusting the temperature of the memory storage device 12).

[0037] In step S204, the processor 103 may provide detection data according to the detection result of the second detection program. The detection data may reflect the defect status of the memory storage device 12. For example, according to the detection result of at least one detection item in Table 2 above on the memory storage device 12, the processor 103 may automatically generate the detection data. For example, the detection data may be presented in the form of a report.

[0038] In one embodiment, the detection data may present at least one of software error information of the memory storage device 12, hardware error information of the memory storage device 12, process defect information of the memory storage device 12, and wear status information of a memory module inside the memory storage device 12. For example, the software error information may present information related to errors and / or defects of specific software inside the memory storage device 12. For example, the hardware error information may present information related to errors and / or defects of specific hardware inside the memory storage device 12. For example, the process defect information may present information related to process defects of specific components inside or outside the memory storage device 12. For example, the wear status information of the memory module may present information related to the degree of wear (e.g., P / E cycles) of at least some memory modules inside the memory storage device 12.

[0039] In one embodiment, based on the detection data, the person currently operating the state detection device 11 to detect the memory storage device 12 can easily and intuitively know the problem points corresponding to the errors or defects that may exist in the memory storage device 12 and correct them or record the problem points. Compared with the traditional method of sending the memory storage device 12 back to the original factory for detection when the memory storage device 12 is detected as a defective product, the state detection device 11 and the state detection method proposed in the embodiment of the present invention can effectively improve the detection efficiency of the memory storage device 12.

[0040] In summary, the embodiment of the present invention proposes that after establishing the connection between the state detection device and the memory storage device, the first detection program can be used to perform a preliminary detection on the memory storage device and perform an initial error classification on the memory storage device according to the detection result. Later, according to the classification result, a more in-depth second detection program is automatically performed on the memory storage device and corresponding detection data is provided to specifically reflect the defect state of the memory storage device. In this way, the state detection efficiency of the memory storage device can be effectively improved.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A state detection method, characterized in that: For detecting a defect state of a memory storage device, the state detection method comprises: establishing a connection with the memory storage device; executing a first detection procedure on the memory storage device to perform initial error classification on the memory storage device; According to the classification result of the initial misclassification, automatically selecting at least one detection item associated with the classification result from a plurality of candidate detection items; Execute a second detection procedure on the memory storage device according to the at least one detection item; and providing test data according to the test result of the second test program, wherein the test data reflects the defect state of the memory storage device, The step of automatically selecting the at least one detection item associated with the classification result from the plurality of candidate detection items according to the classification result of the initial misclassification comprises: In response to the classification result of the initial misclassification being a first classification result, automatically selecting at least one first detection item associated with the first classification result from the plurality of candidate detection items; and In response to the classification result of the initial misclassification being a second classification result, automatically selecting at least one second detection item associated with the second classification result from the plurality of candidate detection items, The project composition of the at least one first detection item is different from the project composition of the at least one second detection item.

2. The state detection method according to claim 1, wherein the first detection procedure comprises executing at least one of the following multiple detection items: Reading and verifying the device identification code reported by the memory storage device; Performing an adjustment test of connection interface parameters of the memory storage device; analyzing eye diagram information of a data signal of the memory storage device; reading and verifying the device type reported by the memory storage device; as well as A read and write test is performed on the memory modules of the memory storage device.

3. The state detection method according to claim 1, wherein the second detection procedure comprises executing at least one of the following multiple detection items: performing a temperature variation test on the memory storage device; performing a surface etching on the memory storage device; performing optical penetration testing on the memory storage device; performing an ultrasonic scan of the memory storage device; performing electronic data detection on the memory storage device; as well as A visual integrity test is performed on the memory storage device.

4. The status detection method according to claim 1, wherein the detection data presents at least one of software error information of the memory storage device, hardware error information of the memory storage device, process defect information of the memory storage device, and wear status information of a memory module inside the memory storage device.

5. A state detection device, characterized in that: Used to detect the defect state of a memory storage device, the state detection device comprises: A connection interface circuit for connecting to the memory storage device; and a processor connected to the connection interface circuit, The processor is used to: establishing a connection between the state detection device and the memory storage device via the connection interface circuit; executing a first detection procedure on the memory storage device to perform initial error classification on the memory storage device; According to the classification result of the initial misclassification, automatically selecting at least one detection item associated with the classification result from a plurality of candidate detection items; Execute a second detection procedure on the memory storage device according to the at least one detection item; and providing test data according to the test result of the second test program, wherein the test data reflects the defect state of the memory storage device, Wherein, according to the classification result of the initial error classification, the operation of automatically selecting the at least one detection item associated with the classification result from the plurality of candidate detection items comprises: In response to the classification result of the initial misclassification being a first classification result, automatically selecting at least one first detection item associated with the first classification result from the plurality of candidate detection items; and In response to the classification result of the initial misclassification being a second classification result, automatically selecting at least one second detection item associated with the second classification result from the plurality of candidate detection items, The project composition of the at least one first detection item is different from the project composition of the at least one second detection item.

6. The state detection device according to claim 5, wherein the first detection procedure comprises executing at least one of the following multiple detection items: Reading and verifying the device identification code reported by the memory storage device; Performing an adjustment test of connection interface parameters of the memory storage device; analyzing eye diagram information of a data signal of the memory storage device; reading and verifying the device type reported by the memory storage device; as well as A read and write test is performed on the memory modules of the memory storage device.

7. The state detection device according to claim 5, wherein the second detection procedure comprises executing at least one of the following multiple detection items: performing a temperature variation test on the memory storage device; performing a surface etching on the memory storage device; performing optical penetration testing on the memory storage device; performing an ultrasonic scan of the memory storage device; performing electronic data detection on the memory storage device; as well as A visual integrity test is performed on the memory storage device.

8. The status detection device according to claim 5, wherein the detection data presents at least one of software error information of the memory storage device, hardware error information of the memory storage device, process defect information of the memory storage device, and wear status information of a memory module inside the memory storage device.

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