A process for improving metal grid grinding depression

Abstract

The present invention provides a process method for improving the grinding depression of a metal gate, providing a gate oxide layer located on a substrate, sequentially forming a polysilicon layer and a stack located on the polysilicon layer on the substrate; the polysilicon layer and the stack cover the gate oxide layer; etching the stack and the polysilicon layer to form a pseudo gate; depositing an interlayer dielectric layer covering the pseudo gate and the upper surface of the substrate; then removing the pseudo gate to form a groove; filling the groove with metal, and forming a metal gate in the groove after the metal is filled; etching the metal in the groove to form a plurality of narrow grooves isolated from each other by metal strips; and etching stays on the metal so that the gate oxide layer under the metal is not exposed; filling the narrow groove with oxide; grinding the upper surface of the substrate after the oxide is filled, so that the surface of the metal gate is flat. The present invention plays a role in preventing depression in the metal gate grinding process, and there is no need to etch through the polysilicon, the gate oxide layer will not be exposed, effectively eliminating various possible defect sources introduced by subsequent processes, and improving device reliability.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a process method for improving metal gate grinding depression. Background Art

[0002] When the technology node enters below 28nm, the logic devices become very small, and quantum effects become more prominent. The original traditional polysilicon gate and silicon oxide dielectric layer can no longer meet the high performance requirements of the device, so high-K materials and metal gates are introduced. In the traditional polysilicon gate process, polysilicon is directly connected to the contact hole as the gate, while in the metal gate process, after the metal gate is filled, there will be a chemical mechanical polishing (CMP) to remove excess metal. In the CMP process, the middle part of the large metal gate will be ground quickly, and the edge part will be ground slowly, which is very easy to form a dishing, which has a serious impact on the quality of the metal gate. Especially in HV devices, the channel area is large, and the area of ​​the metal gate is also correspondingly large. Solving the problem of metal gate grinding dishing is crucial.

[0003] The traditional approach to solving the problem of metal gate dishing is to add metal strips to polysilicon, thereby dividing the large metal gate into many small pieces. However, the gate oxide in the narrow grooves will be directly exposed to the outside, and various metal ion implantations in subsequent processes will directly contact the gate oxide, which poses a serious challenge to device reliability.

[0004] Therefore, it is necessary to develop a method that does not need to expose the gate oxide and can solve the problem of metal gate grinding depression. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a process method for improving metal gate grinding depression, so as to solve the problem of gate oxide damage due to ion implantation and metal gate grinding depression in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a process for improving metal gate grinding depression, which at least comprises:

[0007] Step 1: providing a gate oxide layer on a substrate, and sequentially forming a polysilicon layer and a stacked layer on the polysilicon layer on the substrate; the polysilicon layer and the stacked layer cover the gate oxide layer;

[0008] Step 2: etching the stack and the polysilicon layer to form a dummy gate;

[0009] Step 3: depositing an interlayer dielectric layer covering the dummy gate and the upper surface of the substrate; then removing the dummy gate to form a groove;

[0010] Step 4, filling the groove with metal, and the groove filled with the metal forms a metal gate;

[0011] Step 5: etching the metal in the groove to form a plurality of narrow grooves isolated from each other by metal strips; and etching stops on the metal so that the gate oxide layer under the metal is not exposed;

[0012] Step 6: Filling the slot with oxide;

[0013] Step seven: grinding the upper surface of the substrate after filling with oxide to make the surface of the metal gate flat.

[0014] Preferably, a plurality of STI regions for isolating an active region of a device are formed on the substrate in step 1; and the gate oxide layer is located on the active region of the device.

[0015] Preferably, the stacked layers in step 1 are, from bottom to top, a silicon nitride layer, a PEOX layer, and an APF film layer.

[0016] Preferably, the stack in step one further comprises a NFD film layer located on the APF film layer.

[0017] Preferably, in step 2, photolithography is first performed to define a dummy gate, and then the stack and the polysilicon layer are etched according to the defined dummy gate to form the dummy gate.

[0018] Preferably, the dummy gate formed by etching in step 2 is located on the gate oxide layer, and the STI regions on both sides below the gate oxide layer are partially exposed.

[0019] Preferably, the metal formed in step 4 is aluminum.

[0020] Preferably, in step 4, the method of filling the groove with the metal is: firstly, the metal is formed on the substrate, and the metal is filled in the groove and covers the interlayer dielectric layer on both sides of the groove.

[0021] Preferably, in step five, the method for forming a plurality of narrow grooves isolated from each other by metal strips in the groove is: exposing the metal in the groove using a photomask to form a photoresist pattern; and then etching the metal in the groove according to the photoresist pattern to form a plurality of narrow grooves isolated from each other by metal strips.

[0022] Preferably, in step six, oxide is filled in the narrow groove by a FCVD method.

[0023] Preferably, in step seven, chemical mechanical polishing is used to polish the upper surface of the substrate.

[0024] As described above, the process method of improving metal gate grinding depression of the present invention has the following beneficial effects: the method of the present invention divides polysilicon into a spacer structure in the metal gate process, and after the metal filling is completed, a new metal etching process is added to form a narrow groove morphology at the large area metal gate, and then backfilled with oxide. The formed oxide spacer structure plays a role in preventing depression in the subsequent metal gate CMP process. Compared with the existing polysilicon segmentation scheme, the present invention does not need to etch through the polysilicon, the gate oxide layer will not be exposed, and various possible defect sources introduced by the subsequent process are effectively eliminated, and the device reliability will be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It shows a schematic diagram of the structure of the gate oxide layer, the polysilicon layer and the stacked layer located on the substrate in the present invention;

[0026] Figure 2 It is a schematic diagram of the structure after etching the stacked layers and the polysilicon layer to form a pseudo gate in the present invention;

[0027] Figure 3 The middle part is a structure after the pseudo gate is etched to remove the stacked layers and the polysilicon layer is exposed;

[0028] Figure 4 Shown is a schematic diagram of the structure after the dummy gate is removed to form a groove;

[0029] Figure 5 It is a schematic diagram of the structure after the metal gate is formed in the present invention;

[0030] Figure 6 It is a schematic diagram showing the structure after the metal gate is etched into a plurality of narrow grooves isolated from each other by metal strips in the present invention;

[0031] Figure 7 It is a schematic diagram of the structure after the narrow groove is filled with oxide in the present invention;

[0032] Figure 8 It is a schematic diagram showing the structure of the metal gate after grinding and filling oxide in the present invention;

[0033] Fig. 9 It is a flow chart of the process method for improving metal gate grinding recess of the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0036] The present invention provides a process for improving the grinding depression of metal gate, such as Fig. 9 As shown, Fig. 9 The flowchart of the process method for improving metal gate grinding recess of the present invention is shown, and the method at least comprises the following steps:

[0037] Step 1: providing a gate oxide layer on a substrate, and sequentially forming a polysilicon layer and a stacked layer on the polysilicon layer on the substrate; wherein the polysilicon layer and the stacked layer cover the gate oxide layer; Figure 1 As shown, Figure 1 The schematic diagram of the structure of the gate oxide layer, polysilicon layer and stacked layer on the substrate in the present invention is shown. In step 1, a gate oxide layer GOX is provided on the substrate, and a polysilicon layer 01 and a stacked layer on the polysilicon layer 01 are sequentially formed on the substrate; the polysilicon layer and the stacked layer cover the gate oxide layer GOX.

[0038] In the present invention, further, in step 1 of this embodiment, a plurality of STI regions (STI) for isolating the active region of the device are formed on the substrate; and the gate oxide layer GOX is located on the active region of the device.

[0039] In the present invention, the stacked layers in step 1 of this embodiment are silicon nitride layer 02, PEOX layer 03, and APF film layer 04 from bottom to top.

[0040] Furthermore, in the present invention, the stack in step 1 of this embodiment further includes a NFD film layer 05 located on the APF film layer 04 .

[0041] Step 2: etching the stack and the polysilicon layer to form a dummy gate; Figure 2 As shown, Figure 2 The structure schematic diagram after etching the stacked layer and the polysilicon layer to form a dummy gate in the present invention is shown. In step 2, the stacked layer and the polysilicon layer are etched to form a dummy gate 06.

[0042] In the present invention, in step 2 of this embodiment, photolithography is first performed to define a dummy gate, and then the stack and the polysilicon layer are etched according to the defined dummy gate to form the dummy gate 06 .

[0043] In the present invention, further, the dummy gate formed by etching in step 2 of this embodiment is located on the gate oxide layer GOX, and the STI regions on both sides below the gate oxide layer GOX are partially exposed.

[0044] Step 3: depositing an interlayer dielectric layer covering the dummy gate and the upper surface of the substrate; then removing the dummy gate to form a groove; Figure 3 As shown, Figure 3 It is a schematic diagram of the structure after forming an interlayer dielectric layer on the substrate in the present invention. In step 3, an interlayer dielectric layer ILD0 is deposited to cover the dummy gate 06 and the upper surface of the substrate; then the dummy gate is removed to form a groove; in the process of removing the dummy gate in step 3, the stack is first removed, and then the polysilicon layer 01 under the stack is exposed. Figure 3 The structure shown in FIG. 1 is a structure after the pseudo gate is etched to remove the stacked layers and the polysilicon layer is exposed. Figure 4 As shown, Figure 4 The schematic diagram of the structure after removing the dummy gate to form a groove is shown. In step three, the polysilicon layer in the dummy gate is removed to form a groove. Figure 4 in the groove 07.

[0045] Step 4: fill the groove with metal to form a metal gate; Figure 5 As shown, Figure 5 The structure diagram after the metal gate is formed in the present invention is shown. In step 4, the groove is filled with metal 08, and the groove filled with the metal forms a metal gate.

[0046] According to the present invention, the metal 08 formed in step 4 of this embodiment is aluminum.

[0047] The present invention further provides a method for filling the groove with the metal in step 4 of this embodiment as follows: first, the metal is formed on the substrate, the metal is filled in the groove, and simultaneously covers the interlayer dielectric layer on both sides of the groove.

[0048] Step 5: etching the metal in the groove to form a plurality of narrow grooves isolated from each other by metal strips; and etching stops on the metal so that the gate oxide layer under the metal is not exposed; Figure 6 As shown, Figure 6 It is a schematic diagram of the structure after the metal gate is etched into a plurality of narrow grooves isolated from each other by metal strips in the present invention. In step five, the metal 08 in the groove is etched to form a plurality of narrow grooves 09 isolated from each other by metal strips 10. The bottom of the narrow groove finally formed by etching the metal in step five is still metal, and the gate oxide layer is not exposed, so the gate oxide layer will be protected in the subsequent process.

[0049] The present invention further provides that in step five of this embodiment, the method for forming a plurality of narrow grooves isolated from each other by metal strips in the groove is: using a photomask to expose the metal in the groove to form a photoresist pattern; then etching the metal in the groove according to the photoresist pattern to form a plurality of narrow grooves isolated from each other by metal strips.

[0050] Step 6: Fill the slot with oxide; Figure 7 As shown, Figure 7 The schematic diagram of the structure after the narrow groove is filled with oxide in the present invention is shown. In step six, the oxide 11 is filled in the narrow groove 09 .

[0051] The present invention further comprises filling oxide in the narrow groove by FCVD method in step six of this embodiment.

[0052] Step 7: Grind the upper surface of the substrate after filling with oxide to make the surface of the metal gate flat. Figure 8 As shown, Figure 8 The schematic diagram of the structure after grinding the metal gate filled with oxide in the present invention is shown. In this step, the upper surface of the substrate filled with oxide 11 is ground to make the surface of the metal gate flat.

[0053] According to the present invention, in step seven of this embodiment, chemical mechanical polishing (CMP) is used to polish the upper surface of the substrate.

[0054] In summary, the method of the present invention divides polysilicon into a spacer structure in the metal gate process, and after the metal filling is completed, a new metal etching process is added to form a narrow groove morphology at the large-area metal gate, and then backfilled with oxide. The formed oxide spacer structure plays a role in preventing depression in the subsequent metal gate CMP process. Compared with the existing polysilicon segmentation scheme, the present invention does not need to etch through the polysilicon, the gate oxide layer will not be exposed, and various possible defect sources introduced by the subsequent process are effectively eliminated, and the device reliability will be improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A process for improving metal gate grinding depression, characterized in that: At least: Step 1: providing a gate oxide layer on a substrate, and sequentially forming a polysilicon layer and a stacked layer on the polysilicon layer on the substrate; the polysilicon layer and the stacked layer cover the gate oxide layer; Step 2: etching the stack and the polysilicon layer to form a dummy gate; Step 3: depositing an interlayer dielectric layer covering the dummy gate and the upper surface of the substrate; then removing the dummy gate to form a groove; Step 4, filling the groove with metal, and the groove filled with the metal forms a metal gate; Step 5: etching the metal in the groove to form a plurality of narrow grooves isolated from each other by metal strips; and etching stops on the metal so that the gate oxide layer under the metal is not exposed; Step 6: Filling the slot with oxide; Step seven: grinding the upper surface of the substrate after filling with oxide to make the surface of the metal gate flat.

2. The process for improving metal gate grinding depression according to claim 1, characterized in that: In step 1, a plurality of STI regions for isolating the active region of the device are formed on the substrate; and the gate oxide layer is located on the active region of the device.

3. The process for improving metal gate grinding depression according to claim 1, characterized in that: The stacked layers in step 1 are, from bottom to top, a silicon nitride layer, a PEOX layer, and an APF film layer.

4. The process for improving metal gate grinding depression according to claim 3, characterized in that: The stack in step one further includes a NFD film layer located on the APF film layer.

5. The process for improving metal gate grinding depression according to claim 1, characterized in that: In step 2, photolithography is first performed to define a dummy gate, and then the stack and the polysilicon layer are etched according to the defined dummy gate to form the dummy gate.

6. The process for improving metal gate grinding depression according to claim 2, characterized in that: The dummy gate formed by etching in step 2 is located on the gate oxide layer, and the STI regions on both sides below the gate oxide layer are partially exposed.

7. The process for improving metal gate grinding depression according to claim 1, characterized in that: The metal formed in step 4 is aluminum.

8. The process for improving metal gate grinding depression according to claim 1, characterized in that: The method of filling the groove with the metal in step 4 is: first, the metal is formed on the substrate, the metal is filled in the groove, and at the same time, it covers the interlayer dielectric layer located on both sides of the groove.

9. The process for improving metal gate grinding depression according to claim 1, characterized in that: In step five, the method for forming multiple narrow grooves isolated from each other by metal strips in the groove is: using a mask to expose the metal in the groove to form a photoresist pattern; then etching the metal in the groove according to the photoresist pattern to form multiple narrow grooves isolated from each other by metal strips.

10. The process for improving metal gate grinding depression according to claim 1, characterized in that: In step six, oxide is filled in the narrow groove by FCVD method.

11. The process for improving metal gate grinding recess according to claim 1, characterized in that: In step seven, the upper surface of the substrate is polished by chemical mechanical polishing.

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