A semiconductor structure and a preparation method thereof, three-dimensional memory

Abstract

The application discloses a semiconductor structure and a preparation method thereof and a three-dimensional memory, and relates to the technical field of three-dimensional memory devices, and aims to provide a technical scheme of a step structure which can reduce the number of photoetchings and has a better step sidewall appearance. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; sequentially forming N stack structures arranged in a stack on the substrate; sequentially performing m photoetchings and etchings on the N stack structures to obtain a target step structure with N steps; wherein N is greater than m, and the N and m satisfy a preset relationship. The semiconductor structure is prepared according to the preparation method of the semiconductor structure. The three-dimensional memory comprises the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional storage device technology, and in particular to a semiconductor structure and its fabrication method, and a three-dimensional memory. Background Technology

[0002] In recent years, flash memory has developed particularly rapidly. To further improve the bit density of flash memory while reducing bit cost, 3D NAND technology has been rapidly developed. Meanwhile, other 3D storage devices share essentially the same integration requirements.

[0003] In existing 3D structures, stepped regions need to be formed around the stacked structure to facilitate subsequent etching of contact holes and connection of control polarity lines. During the step formation process, photoresist is used as a mask layer. After lateral etching of the photoresist, the stacked structure is then etched. Because there are many step layers, to reduce the number of lithography steps and lower costs, a lateral trimming process for the photoresist is mostly adopted. This allows multiple steps to be formed in a single lithography step. However, lateral etching of the photoresist layer also causes vertical etching, consuming the photoresist layer. Therefore, a thicker photoresist layer is required; otherwise, excessive photoresist consumption can damage the step layers. Furthermore, lateral etching easily generates rough sidewalls, resulting in high sidewall roughness when the photoresist mask pattern is transferred downwards to the lower thin film, thus affecting the accuracy of the step dimensions. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor structure and its fabrication method, and a three-dimensional memory, which provides a technical solution for a stepped structure that can reduce the number of photolithography steps and has a better step sidewall morphology.

[0005] In a first aspect, the present invention provides a method for fabricating a semiconductor structure, comprising the following steps: providing a substrate; sequentially forming N stacked structures on the substrate; sequentially performing photolithography and etching on the N stacked structures m times to obtain a target stepped structure with N steps; wherein, N is greater than m, and N and m satisfy a preset relationship.

[0006] Compared with existing technologies, the semiconductor structure fabrication method provided by this invention involves performing m photolithography and etching processes sequentially on N stacked structures to obtain a target stepped structure with N steps. It is evident that this invention forms each step in the target stepped structure through direct photolithography and etching. In contrast, existing technologies using photoresist lateral trim processes easily produce rough sidewalls, resulting in high sidewall roughness when the photoresist mask pattern is transferred downwards to the lower thin film, thus affecting the accuracy of step dimensions. This invention forms steps through etching after photolithography, thus allowing for precise control of the step morphology and dimensions.

[0007] Furthermore, in this invention, the number of steps in the target step structure is greater than the number of photolithography steps, thus reducing the number of photolithography steps.

[0008] Preferably, the preset relationship is:

[0009] N=2 m-1 .

[0010] Preferably, each of the stacked structures includes a first sacrificial layer and a first insulating layer stacked from bottom to top;

[0011] Alternatively, each of the stacked structures includes a first metal layer and a first insulating layer stacked from bottom to top.

[0012] Preferably, each step in the target step structure is formed by one or more photolithography and etching processes from the corresponding stacked structure.

[0013] Preferably, each step includes at least a second sacrificial layer, which is formed by one or more photolithography and etching processes from the first sacrificial layer in the corresponding stacked structure;

[0014] Alternatively, each step may include at least a second metal layer in the corresponding stacked structure, the second metal layer being formed by one or more photolithography and etching processes from the first metal layer in the corresponding stacked structure.

[0015] Preferably, when each step includes at least a second sacrificial layer in the corresponding stacked structure, the method for fabricating the semiconductor structure further includes:

[0016] Remove the second sacrificial layer from the target step structure;

[0017] A third metal layer is formed in the region where the second sacrificial layer is located, resulting in a new target step structure.

[0018] Preferably, the step of sequentially performing m photolithographic etchings on the N stacked structures to obtain a target step structure with N steps includes:

[0019] A first photolithographic pattern is formed on the N stacked structures. Using the first photolithographic pattern as a mask, the top insulating layer of a predetermined region of the N stacked structures is removed to expose the sacrificial layer or metal layer under the top insulating layer of the N stacked structures, thereby obtaining a first step structure. The predetermined region corresponds to the region where the target step structure is located.

[0020] A second photolithographic pattern is formed on the first step structure. Using the second photolithographic pattern as a mask, the first step structure is etched in a bottom-up direction to obtain the second step structure.

[0021] A third photolithographic pattern is formed on the second step structure. Using the third photolithographic pattern as a mask, the second step structure is etched in a bottom-up direction to obtain the third step structure. The number of steps in the third step structure is twice the number of steps in the second step structure.

[0022] A (p+1)th photolithographic pattern is formed on the p-th step structure. Using the (p+1)th photolithographic pattern as a mask, the p-th step structure is etched in a bottom-up direction to obtain the (p+1)th step structure. The number of steps in the (p+1)th step structure is twice the number of steps in the p-th step structure.

[0023] Until the m-1th step structure forms the m-th lithographic pattern, the m-th lithographic pattern is used as a mask to etch the m-1th step structure in a bottom-up direction to obtain the target step structure; wherein the number of steps in the target step structure is twice the number of steps in the m-1th step structure; wherein p+1 is less than or equal to m-1.

[0024] Preferably, the p+1th lithographic pattern is formed on the target area of ​​each step of the p-th step structure; wherein, the target area is the part of the step that connects to the previous step.

[0025] Secondly, the present invention also provides a semiconductor structure prepared according to the above-described method for preparing a semiconductor structure.

[0026] Thirdly, the present invention also provides a three-dimensional memory, including the above-described semiconductor structure.

[0027] Compared with the prior art, the beneficial effects of the second and third aspects of the present invention are the same as the beneficial effects of the semiconductor structure provided in the first aspect, and will not be repeated here. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0029] Figure 1 This is a schematic diagram of a substrate structure provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of an N-stacked structure provided in an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0032] Figures 4-11 The diagram shows the structural schematics of each stage of a semiconductor structure fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0033] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0036] In recent years, flash memory has developed particularly rapidly. To further improve the bit density of flash memory while reducing bit cost, 3D NAND technology has been rapidly developed. Meanwhile, other 3D storage devices share essentially the same integration requirements.

[0037] In existing 3D structures, stepped regions need to be formed around the stacked structure to facilitate subsequent etching of contact holes and connection of control polarity lines. During the step formation process, photoresist is used as a mask layer. After lateral etching of the photoresist, the stacked structure is then etched. Because there are many step layers, to reduce the number of lithography steps and lower costs, a lateral trimming process for the photoresist is mostly adopted. This allows multiple steps to be formed in a single lithography step. However, lateral etching of the photoresist layer also causes vertical etching, consuming the photoresist layer. Therefore, a thicker photoresist layer is required; otherwise, excessive photoresist consumption can damage the step layers. Furthermore, lateral etching easily generates rough sidewalls, resulting in high sidewall roughness when the photoresist mask pattern is transferred downwards to the lower thin film, thus affecting the accuracy of the step dimensions.

[0038] Based on this, in a first aspect, embodiments of the present invention disclose a method for preparing a semiconductor structure, comprising the following steps:

[0039] Reference Figure 1 Substrate 10 is provided.

[0040] To reduce the manufacturing cost of the semiconductor structure, the substrate 10 can be a semiconductor substrate such as a silicon substrate or a germanium-silicon substrate. Without considering cost, the substrate 10 can also be an SOI (Silicon-On-Insulator) substrate; this embodiment of the invention does not impose specific limitations on this.

[0041] Reference Figure 2 N stacked structures 20 are sequentially formed on the substrate 10.

[0042] Each stacked structure 20 includes a first sacrificial layer and a first insulating layer stacked from bottom to top. Alternatively, each stacked structure includes a first metal layer and a first insulating layer stacked from bottom to top. (See reference...) Figure 2 201 can be either the first sacrificial layer or the first metal layer. 202 is the first insulating layer.

[0043] The first metal layer can be a word line metal layer. This word line metal layer is used to form steps, which are then etched to form etched contact holes. These contact holes are used to bring out the control word lines to realize the function of the three-dimensional memory device.

[0044] Reference Figure 3 The N stacked structures are sequentially subjected to m photolithography and etching processes to obtain a target step structure 30 with N steps; wherein N is greater than m, and N and m satisfy a preset relationship.

[0045] Reference Figure 3 As can be seen, each step includes at least a second sacrificial layer, which is formed by one or more photolithography and etching processes of the first sacrificial layer in the corresponding stacked structure. Each step also includes a second insulating layer, which can be formed by photolithography and etching of the first insulating layer in the lower stacked structure adjacent to the stacked structure.

[0046] Alternatively, each step may include at least a second metal layer in the corresponding stacked structure, the second metal layer being formed by one or more photolithography and etching processes of the first metal layer in the corresponding stacked structure. Each step may also include a second insulating layer, which may be formed by photolithography and etching of the first insulating layer in the lower stacked structure adjacent to the stacked structure.

[0047] Furthermore, when each step includes at least a second sacrificial layer in the corresponding stacked structure, the method for fabricating the semiconductor structure further includes:

[0048] Remove the second sacrificial layer in the target step structure; wherein, since the thickness of the second sacrificial layer is very small in the semiconductor structure, in practice, the second sacrificial layer in the target step structure can be removed by dry etching.

[0049] A third metal layer is formed in the region where the second sacrificial layer is located, resulting in a new target step structure. It should be understood that this new target step structure is the final desired step structure.

[0050] In a preferred embodiment, the preset relationship satisfied by N and m can be N = 2. m-1 .

[0051] As can be seen, when the target stepped structure has 8 steps, the embodiments of the present invention require 4 photolithography and etching processes. Similarly, the embodiments of the present invention can form a stepped structure with 16 steps in 5 photolithography processes; a stepped structure with 32 steps in 6 photolithography processes; a stepped structure with 64 steps in 7 photolithography processes; a stepped structure with 128 steps in 8 photolithography processes; and a stepped structure with 256 steps in 9 photolithography processes. This significantly reduces the number of photolithography processes and simplifies the fabrication process. Especially for stepped structures with a large number of steps, the semiconductor structure fabrication method provided by the embodiments of the present invention exhibits superior process simplification.

[0052] The following describes in detail the method for fabricating the semiconductor structure provided in this embodiment of the invention, taking the fabrication of an 8-layer target stepped structure as an example:

[0053] Reference Figure 4 A first photolithographic pattern 401 is formed on N stacked structures. The process of forming the first photolithographic pattern may include: forming a first photoresist on the N stacked structures, and performing operations such as exposure and development on the first photoresist to obtain the first photolithographic pattern 401. This first photolithographic pattern needs to expose the areas in the N stacked structures where the target step structure will subsequently be formed.

[0054] Reference Figure 5 Using the first photolithographic pattern as a mask, the top insulating layer of a preset region of the N stacked structures is removed, exposing the sacrificial layer or metal layer beneath the top insulating layer of the N stacked structures. Then, the first photolithographic pattern is removed to obtain the first step structure 501. The preset region corresponds to the region where the target step structure is located.

[0055] Reference Figure 6 A second photolithographic pattern 402 is formed on the first step structure 501. The process of forming the second photolithographic pattern 402 may include: forming a second photoresist on the first step structure 501, and then performing operations such as exposure and development on the second photoresist to obtain the second photolithographic pattern 402. This second photolithographic pattern 402 needs to expose the area in the first step structure where the step needs to be formed by the current photolithographic etching.

[0056] Reference Figure 7 Using the second photolithographic pattern 402 as a mask, the first step structure is etched from bottom to top. Then, the second photolithographic pattern 402 is removed to obtain the second step structure 502. The second step structure has two step layers.

[0057] Reference Figure 8A third photolithographic pattern 403 is formed on the second step structure 502. The process of forming the third photolithographic pattern 403 may include: forming a third photoresist on the second step structure 502, and then performing exposure and development operations on the third photoresist to obtain the third photolithographic pattern 403. This third photolithographic pattern 403 needs to expose the area in the second step structure 502 where the step needs to be formed by this photolithographic etching.

[0058] Reference Figure 9 Using the third photolithographic pattern 403 as a mask, the second step structure is etched from bottom to top. Then, the third photolithographic pattern 403 is removed to obtain the third step structure 503. The number of steps in the third step structure 503 is twice the number of steps in the second step structure. It can be seen that the third step structure 503 has four step layers.

[0059] Reference Figure 10 A fourth photolithographic pattern 404 is formed on the third step structure 503. The process of forming the fourth photolithographic pattern 404 may include: forming a fourth photoresist on the third step structure 503, and performing exposure and development operations on the fourth photoresist to obtain the fourth photolithographic pattern 404. This fourth photolithographic pattern 404 needs to expose the area in the third step structure 503 where the step needs to be formed by this photolithographic etching.

[0060] Reference Figure 11 Using the fourth photolithographic pattern 404 as a mask, the third step structure is etched from bottom to top. Then, the fourth photolithographic pattern 404 is removed to obtain the fourth step structure 504. The number of steps in the fourth step structure 504 is twice the number of steps in the third step structure. It can be seen that the fourth step structure has eight step layers.

[0061] Thus, this embodiment of the invention has obtained a target step structure with 8 steps through four photolithography and etching processes.

[0062] It should be understood that, in practice, when multiple photolithography steps are required to obtain the desired number of layers in a target stepped structure, the intermediate steps can be performed using the following method:

[0063] A (p+1)th photolithographic pattern is formed on the p-th step structure. The process of forming the (p+1)th photolithographic pattern may include: forming a (p+1)th photoresist on the p-th step structure, and performing operations such as exposure and development on the (p+1)th photoresist to obtain the (p+1)th photolithographic pattern. This (p+1)th photolithographic pattern needs to expose the area in the p-th step structure where the step needs to be formed by the current photolithographic etching.

[0064] Using the p+1th lithographic pattern as a mask, the p-th step structure is etched in a bottom-up direction. Then, the p+1 lithographic pattern is removed to obtain the p+1th step structure. The number of steps in the p+1th step structure is twice the number of steps in the p-th step structure.

[0065] Then, the step structure is photolithographically etched in the manner described above until the m-1th step structure is formed with a photolithographic pattern. Using the m-th photolithographic pattern as a mask, the m-1th step structure is etched from bottom to top to obtain the target step structure. The number of steps in the target step structure is twice the number of steps in the m-1th step structure. At this point, the target step structure for the required layer step is obtained. Here, p+1 is less than or equal to m-1.

[0066] It is worth noting that during the fabrication of the semiconductor structure, the p+1th photolithographic pattern is formed on the target region of each step of the p-th step structure; wherein, the target region is the portion of the step that connects to the previous step. This ensures that after the corresponding insulating layer is removed to expose the metal layer or sacrificial layer, a downwardly extending step structure can be formed. In other words, based on this, the height of the intermediate steps in the subsequently formed target step structure can be higher than the next step and lower than the previous step, thus ensuring the readiness of the fabrication process for the step structure.

[0067] Based on this, the semiconductor structure fabrication method provided in this embodiment of the invention performs m photolithography and etching processes sequentially on N stacked structures to obtain a target stepped structure with N steps. It can be seen that this embodiment of the invention forms each step in the target stepped structure through direct photolithography and etching. Compared to the prior art, where the photoresist lateral trim process easily produces rough sidewalls, resulting in high sidewall roughness when the photoresist mask pattern is transferred downwards to the lower thin film, thus affecting the accuracy of the step dimensions, this embodiment of the invention forms steps by etching after photolithography, thus allowing for precise control of the step morphology and dimensions.

[0068] Furthermore, in the embodiments of the present invention, the number of steps in the target step structure is greater than the number of photolithography steps, thus reducing the number of photolithography steps.

[0069] In a second aspect, embodiments of the present invention also disclose a semiconductor structure prepared according to the semiconductor structure preparation method in the first aspect.

[0070] The beneficial effects of the semiconductor structure in the embodiments of the present invention are the same as those of the semiconductor structure preparation method in the first aspect, and will not be repeated here.

[0071] Thirdly, embodiments of the present invention also disclose a three-dimensional memory, including the semiconductor structure provided in the second aspect.

[0072] The beneficial effects of the three-dimensional memory in this embodiment of the invention are the same as those of the semiconductor structure in the second aspect, and will not be repeated here.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for preparing the semiconductor structure includes the following steps: Provide substrate; N stacked structures are sequentially formed on the substrate; The N stacked structures are sequentially subjected to m photolithography and etching processes to obtain a target stepped structure with N steps; wherein N is greater than m, and N and m satisfy a preset relationship. The step of performing photolithography and etching m times sequentially on the N stacked structures to obtain a target stepped structure with N steps includes: A first photolithographic pattern is formed on the N stacked structures. Using the first photolithographic pattern as a mask, the top insulating layer of a predetermined region of the N stacked structures is removed to expose the sacrificial layer or metal layer under the top insulating layer of the N stacked structures, thereby obtaining a first step structure. The predetermined region corresponds to the region where the target step structure is located. A second photolithographic pattern is formed on the first step structure. Using the second photolithographic pattern as a mask, the first step structure is etched in a bottom-up direction to obtain the second step structure. A third photolithographic pattern is formed on the second step structure. Using the third photolithographic pattern as a mask, the second step structure is etched in a bottom-up direction to obtain the third step structure. The number of steps in the third step structure is twice the number of steps in the second step structure. A (p+1)th photolithographic pattern is formed on the p-th step structure. Using the (p+1)th photolithographic pattern as a mask, the p-th step structure is etched in a bottom-up direction to obtain the (p+1)th step structure. The number of steps in the (p+1)th step structure is twice the number of steps in the p-th step structure. Until the m-1th step structure forms the m-th photolithographic pattern, the m-th photolithographic pattern is used as a mask to etch the m-1th step structure in a bottom-up direction to obtain the target step structure; wherein the number of steps in the target step structure is twice the number of steps in the m-1th step structure; Wherein, p+1 is less than or equal to m-1; the p+1th lithographic pattern is formed on the target area of ​​each step of the pth step structure; wherein, the target area is the part of the step that connects to the previous step.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The preset relationship is as follows: 。 3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Each of the stacked structures includes a first sacrificial layer and a first insulating layer stacked from bottom to top; Alternatively, each of the stacked structures includes a first metal layer and a first insulating layer stacked from bottom to top.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, Each step in the target step structure is formed by at least one or more photolithography and etching processes from the corresponding stacked structure.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, Each step includes at least a second sacrificial layer, which is formed by one or more photolithography and etching processes from the first sacrificial layer in the corresponding stacked structure. Alternatively, each step may include at least a second metal layer in the corresponding stacked structure, the second metal layer being formed by one or more photolithography and etching processes from the first metal layer in the corresponding stacked structure.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, When each step includes at least a second sacrificial layer in the corresponding stacked structure, the method for fabricating the semiconductor structure further includes: Remove the second sacrificial layer from the target step structure; A third metal layer is formed in the region where the second sacrificial layer is located, resulting in a new target step structure.

7. A semiconductor structure, characterized in that, The semiconductor structure is prepared according to any one of claims 1-6.

8. A three-dimensional memory, characterized in that, Includes the semiconductor structure described in claim 7.

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