Semiconductor device structure and method for manufacturing the same

Abstract

Semiconductor device structure and manufacturing method thereof according to the present invention. The device structure includes: a semiconductor substrate, an active region and an isolation structure formed in the semiconductor substrate, a gate structure, and a dummy structure. The dummy structure is at least located on the isolation structure between adjacent active regions and has a spacing from the gate structure. By preparing the dummy structure on the isolation structure between adjacent active regions according to the present invention, the projection of the dummy structure on the isolation structure is located between source doping regions or between drain doping regions, and can further extend above an adjacent source doping region or drain doping region to form an overlapping region, which can block part of the ion implantation, effectively improve the breakdown voltage of the bit line memory, reduce the breakdown risk, the dummy structure can be prepared simultaneously with the gate structure without changing any process conditions and steps, the process is simple and feasible, and the dummy structure of the present invention can not additionally increase the device area.

Description

[0001] This application is a divisional application of the patent with the application date of October 15, 2020, application number 202011101325.0, and invention title "Semiconductor Device Structure and Preparation Method Thereof". Technical Field

[0002] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device structure and a preparation method thereof. Background Art

[0003] With the development of memory technology, the storage density of planar memory cells is approaching the upper limit, and three-dimensional flash memory (3D NAND) technology has emerged. The 3D NAND memory architecture can solve the density limitation in planar memory cells. Currently, a general 3D NAND structure includes a memory array and peripheral devices for controlling the signals of the memory array. The peripheral devices include bit line drivers, page buffers, etc. However, with the increase in the storage cell density in the 3D NAND architecture, the size of the peripheral device components needs to be relatively reduced. For example, the pitch between bit line driver transistors gradually decreases, resulting in a relatively high risk of punch-through (NUH / NUH punch-through risk), making it difficult to meet the required performance of the device.

[0004] Therefore, it is necessary to provide a semiconductor device structure and a preparation method to solve the above problems of the prior art. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor device structure and a preparation method thereof, which are used to solve the problems such as the relatively high breakdown risk of the bit line driver caused by the reduction of the device size in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a semiconductor device structure, which includes:

[0007] A semiconductor substrate;

[0008] A plurality of active regions and isolation structures located in the semiconductor substrate, the active regions and the isolation structures are alternately arranged at intervals along a first direction, the active regions extend along a second direction, and the first direction is perpendicular to the second direction;

[0009] At least a gate structure located on the active regions; and

[0010] At least a dummy structure located on the isolation structures, and there is a spacing between the gate structure and the dummy structure in the second direction;

[0011] The active region is further formed with source doping regions and drain doping regions located on both sides of the gate structure, and the projection of the dummy structure on the isolation structure is located between the source doping regions, and / or the projection of the dummy structure on the isolation structure is located between the drain doping regions.

[0012] Optionally, the gate structure and the dummy structure are made of the same material and have the same height.

[0013] Optionally, the gate structure includes a plurality of gate units corresponding to the active regions one by one. Each gate unit spans across the corresponding active region in the first direction, and all the gate units are electrically connected based on the same metal layer.

[0014] Optionally, there is a spacing between adjacent gate units, and the projections of the virtual structures corresponding to the two gate units of adjacent active regions and the active regions overlap in the first direction.

[0015] Optionally, the gate structure includes a strip-shaped gate that spans across each active region in the first direction.

[0016] Optionally, lightly doped drain regions are further formed on both sides of the gate structure in the active region.

[0017] Optionally, the semiconductor device structure is a bit line driver.

[0018] Optionally, in the first direction, the dummy structure extends above the source doping region to form an overlapping region, or the dummy structure extends above the drain doping region to form the overlapping region.

[0019] Optionally, in the first direction, the size of the overlapping region is between 1 / 5 and 1 / 3 of the size of the corresponding source doping region or drain doping region.

[0020] The present invention also provides a method for manufacturing a semiconductor device structure, and the manufacturing method includes the following steps:

[0021] Provide a semiconductor substrate;

[0022] Form a plurality of active regions and isolation structures in the semiconductor substrate. The active regions and the isolation structures are alternately arranged at intervals in the first direction, and the active regions extend in the second direction, and the first direction is perpendicular to the second direction;

[0023] A gate structure and a dummy structure are fabricated on the semiconductor substrate, wherein the gate structure is at least formed on the active region, the dummy structure is at least formed on the isolation structure, and there is a spacing between the gate structure and the dummy structure in the second direction;

[0024] The active region is subjected to ion implantation to form a source doping region and a drain doping region on both sides of the gate structure, and the projection of the dummy structure on the isolation structure is located between the source doping regions, and / or the projection of the dummy structure on the isolation structure is located between the drain doping regions.

[0025] Optionally, the gate structure and the dummy structure are fabricated simultaneously based on the same process.

[0026] Optionally, the gate structure includes a plurality of gate units corresponding to the active regions one by one, each gate unit straddles the corresponding active region in the first direction, and each gate unit is electrically connected based on the same metal layer; or, the gate structure includes a strip-shaped gate that straddles each of the active regions in the first direction.

[0027] Optionally, there is a spacing between adjacent gate units, and the projection of the dummy structure between the gate units corresponding to adjacent active regions and the active regions in the first direction overlaps.

[0028] Optionally, after forming the source doping region and the drain doping region, the following step is further included: ion doping the active regions on both sides of the gate structure to form lightly doped drain regions.

[0029] Optionally, in the first direction, the dummy structure extends above the source doping region to form an overlapping region, or the dummy structure extends above the drain doping region to form the overlapping region.

[0030] Optionally, in the first direction, the size of the overlapping region is between 1 / 5 and 1 / 3 of the size of the corresponding source doping region or drain doping region.

[0031] As described above, in the semiconductor device structure and its manufacturing method of the present invention, a dummy structure is fabricated on the isolation structure between adjacent active regions, the projection of the dummy structure on the isolation structure is located between the source doping regions or between the drain doping regions, and can further extend above the adjacent source doping region or drain doping region to form an overlapping region, which can block part of the ion implantation, effectively improve the breakdown voltage of the bit line memory, reduce the breakdown risk, the dummy structure and the gate structure can be fabricated simultaneously without changing any process conditions and steps, the process is simple and feasible, and the dummy structure of the present invention can not increase the device area additionally. Description of the Drawings

[0032] Figure 1 A top view showing an example of the semiconductor device structure of the present invention.

[0033] Figure 2 A top view showing another example of the semiconductor device structure of the present invention.

[0034] Figure 3 A top view showing yet another example of the semiconductor device structure of the present invention.

[0035] Figure 4 A top view showing still another example of the semiconductor device structure of the present invention.

[0036] Figure 5 A process flow chart showing the preparation of the semiconductor device structure of the present invention.

[0037] Figure 6 A schematic diagram showing the provision of a semiconductor substrate in an example of the preparation of the semiconductor device structure of the present invention.

[0038] Figure 7 A schematic diagram showing the formation of an active region and an isolation structure in an example of the preparation of the semiconductor device structure of the present invention.

[0039] Figure 8 A top view showing the formation of a gate structure and a dummy structure in an example of the preparation of the semiconductor device structure of the present invention.

[0040] Figure 9 Shown as Figure 8 A cross-sectional view taken along the AA' direction of the shown structure.

[0041] Figure 10 Shown as Figure 8 A cross-sectional view taken along the BB' direction of the shown structure.

[0042] Figure 11 A diagram showing the formation of a source doping region and a drain doping region in an example of the preparation of the semiconductor device structure of the present invention.

[0043] Figure 12 A graph showing the influence of the scheme of forming a dummy structure and the scheme of not forming a dummy structure according to the present invention on the breakdown voltage of a bit line driver.

[0044] Description of Element Numbers

[0045] 100 Semiconductor Substrate

[0046] 100a Well Region

[0047] 101 Active Region

[0048] 102 Isolation Structure

[0049] 103 Gate structure

[0050] 104 Virtual structure

[0051] 105 Source doping region

[0052] 106 Drain doping region

[0053] 107 Gate unit

[0054] 108 Metal layer

[0055] Steps S1 - S3 Detailed implementation manners

[0056] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be locally enlarged out of the general proportion, and the schematic diagrams are only examples and should not limit the protection scope of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0058] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on", etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers. Additionally, "between... and..." used in the present invention includes the two endpoint values.

[0059] In the context of the present application, the structure in which the first feature is "above" the second feature described may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0060] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0061] As Figures 1-4 shown, the present invention provides a semiconductor device structure, and the semiconductor device structure includes: a semiconductor substrate 100, a plurality of active regions 101 and isolation structures 102 located within the semiconductor substrate 100, a gate structure 103 located at least on the active regions 101, and a dummy structure 104 located at least on the isolation structures 102 between adjacent active regions.

[0062] Among them, the semiconductor substrate 100 can be a substrate for manufacturing 3D NANA memory peripheral devices. For example, a CMOS wafer substrate. The semiconductor substrate 100 can be a single-layer material layer or a stacked material layer. The material of the semiconductor substrate may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, III-V compounds, any other suitable material, or any combination thereof. In some embodiments, the semiconductor substrate 100 can be polished on both sides before manufacturing the peripheral devices. Both are polished and processed to provide a smooth surface for high-quality semiconductor devices. Among them, the peripheral devices can include any suitable semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. In semiconductor devices, p-type MOSFETs and / or n-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit designs. In addition, the peripheral device 450 can be a p-channel MOSFET or an n-channel MOSFET. In one example, a well region 100a can also be formed by ion doping in the semiconductor substrate 100, and wells are formed by n-type or p-type doping in the active device region.

[0063] The semiconductor device further includes a plurality of active regions 101 and isolation structures 102. Among them, a first direction and a second direction perpendicular to each other are defined in the plane where the semiconductor substrate 100 is located, corresponding to the y direction and the x direction in the figure respectively. The active regions 101 and the isolation structures 102 are alternately arranged at intervals along the first direction, and the active regions 102 extend along the second direction. Among them, the number of the active regions 101 and the isolation structures 102 can be set according to actual needs.

[0064] Currently, as the device size continues to shrink, the distance between adjacent active regions gradually decreases. For example, in the first direction, for the bit-line driver of the present invention, that is, the semiconductor device structure serves as a bit-line driver. In a 3D NAND structure, it includes a memory array and peripheral devices for controlling the signals of the memory array, and the peripheral devices include a bit-line driver. In the current 3D-NAND device design, the bit-line driver (BL driver device) is a high-voltage hybrid NMOS (UHVN hybrid NMOS) array structure. During the erase (Cell Erase) and program (Program) processes, the adjacent transistors of the bit-line driver need to withstand a voltage difference of ~2.4V, while the spacing (spacing) between adjacent transistors (as shown by the dashed line in the figure) is only 0.386um. Therefore, the risk of punch-through between the two transistors of the bit-line memory (NUH / NUH punch-through risk) is relatively high.

[0065] Furthermore, a gate structure 103 and a dummy structure 104 are also fabricated on the semiconductor device structure of the present invention. Among them, the gate structure 103 is at least disposed on the active region 101 and serves as the gate of the device.

[0066] The semiconductor device structure includes a dummy structure 104, and there is a spacing between the gate structure 103 and the dummy structure 104, that is, they do not contact each other. In the present invention, the dummy structure 104 is at least disposed on the isolation structure 102. The dummy structure 104 disposed on the isolation structure 102 can block part of the LDD ion implantation and source-drain implantation (NP implantation), reduce the implanted ions injected downward, thereby enhancing the isolation ability of the isolation structure, increasing the breakdown voltage between adjacent transistors, and effectively suppressing the breakdown of adjacent transistors. In addition, in the present invention, the dummy structure 104 is disposed on the isolation structure 102 and has a spacing from the gate structure 103 in the plane of the semiconductor substrate 100, without the need to additionally increase the device area.

[0067] As an example, the gate structure 103 and the dummy structure 104 are made of the same material, which is polysilicon in this example. The gate structure 103 and the dummy structure 104 have the same height. That is, in this example, the dummy structure 104 is arranged to have the same structure as the gate structure 103, and the distance s between the two is between 0.5 μm and 1 μm, such as 0.6 μm or 0.8 μm. For example, in one example, the dummy structure 104 is located between the drain doping regions of adjacent active regions, and the distance between the dummy structure 104 and the gate structure 103 is 0.7 μm. In one example, the dummy structure has the same length as the adjacent heavily doped region (the drain doping region), that is, the dummy structure and the adjacent heavily doped region have the same length along the second direction. Thus, the dummy structure 104 and the gate structure 103 can be fabricated simultaneously based on the same process, and the introduction of the dummy structure 104 does not require any change in process conditions and steps, which is simple and feasible.

[0068] As an example, as Figure 4 shown, the gate structure includes a plurality of gate units 107 corresponding one-to-one to the active regions 101. The gate units 107 span across the corresponding active regions 101 along the first direction, and each of the gate units 107 is electrically connected based on the same metal layer 108. In this example, designing the gate as multiple disconnected gate units 107 can reduce the area between the active regions covered by the gate structure, thereby increasing the threshold voltage of the field-effect transistor, improving the breakdown voltage, and enhancing the performance of the memory cell when the transistor pitch becomes smaller. In addition, designing the gate units 107 to be disconnected can further reduce the punch-through risk between adjacent devices. Thus, based on the combined action of the gate units 107 and the dummy structure 104, the problem of punch-through between adjacent transistors of the bit-line driver proposed in the present invention can be solved. In addition, in this example, the electrical connection between the gate units 107 is achieved through the metal layer, which can also reduce the series resistance and increase the transmission current of the bit-line driver.

[0069] As an example, there is a spacing between adjacent gate units 107, and the projections of the two gate units 107 corresponding to two adjacent active regions 101 and the corresponding dummy structure 104 between them in the first direction overlap. That is to say, the projections of two adjacent gate units 107 and a dummy structure 104 between them are all projected on the y-axis, and there is no gap between the projections of the three components, forming a continuous line.

[0070] As an example, refer to Figures 1-3As shown, the gate structure includes a strip-shaped gate that spans across each of the active regions in the first direction. In this example, a single strip-shaped gate is used to achieve the common-gate electrical connection for all the active regions.

[0071] As an example, source doping regions 105 and drain doping regions 106 are further formed on both sides of the gate structure 103 in the active region 101, and the dummy structure 104 is correspondingly located between the source doping regions 105 or between the drain doping regions 106 of adjacent active regions 101. Among them, the source doping region 105 and the drain doping region 106 serve as the source and drain of the device and are arranged in the second direction. The dummy structure 104 can be only arranged at the position corresponding to the drain doping region 106 of adjacent active regions 101, as Figure 1 shown. Of course, it can be arranged between adjacent source doping regions 105 and between drain doping regions 106 at the same time, as Figure 2 shown, that is, the projection of the dummy structure 104 on the isolation structure 102 is located between the source doping regions 105 and / or the projection of the dummy structure 104 on the isolation structure 102 is located between the drain doping regions 106. The distance between the dummy structure located between the drain doping regions 106 and the gate structure is s, and the distance between the dummy structure located between the source doping regions 105 and the gate structure is t. In an example, because a voltage is applied to the drain and the problem of punch-through needs to be considered, no voltage is applied to the source and the problem of punch-through does not need to be considered. The length of s is set to 0.5 - 1 μm, which can be 0.6 μm or 0.8 μm, and the length of t can be flexibly designed according to the actual situation.

[0072] In a further example, in the first direction, the dummy structure 104 also extends above the source doping regions 105 or the drain doping regions 106 of two adjacent active regions to form an overlapping region. As Figure 3As shown, taking the example where the virtual structure 104 is located between the drain doping regions 106 of adjacent active regions, the virtual structure 104 straddles the underlying isolation structure 102 and further extends to both sides. In one example, the width of the overlapping region between the extensions to both sides and the drain doping region 106 in the first direction is d. In one example, the distances from the extensions to the drain doping regions on both sides are equal, and the length of d is 0.05 - 0.2 μm. For example, it can be 0.08 μm, 0.1 μm, 0.12 μm, 0.15 μm, 0.18 μm. The virtual structure is equivalent to blocking the ion implantation of LDD, which is equivalent to reducing the LDD concentration and reducing the risk of punch-through. In one example, the doping dose of LDD is between 5e10 n / cm2 - 5e13 n / cm2. For example, it can be selected as 5e12 n / cm2; the doping dose of Np is between 1e11 n / cm2 - 5e15 n / cm2. For example, it can be selected as 1e13 n / cm2, 5e11 n / cm2, 5e15 n / cm2. Optionally, along the first direction, the size of the overlapping region is between 1 / 5 - 1 / 3 of the size of the corresponding source doping region or drain doping region. Among them, setting the virtual structure 104 on the isolation structure at the position between the drain doping regions is beneficial for blocking subsequent implanted ions (such as LDD doping ions or source / drain NP doping ions), and is beneficial for blocking some doping ions from entering structures such as the isolation structure, source doping region, and drain doping region, thereby effectively achieving isolation between adjacent transistors, increasing the breakdown voltage (punch BV), and reducing the breakdown risk (punch-through risk). Further, forming the overlapping region can be beneficial for improving the ion blocking effect, widening the width of the isolation structure in this direction, and is beneficial for improving the isolation between transistors, without affecting the channel of the device and without affecting the function of the source / drain regions of the device. And, the above solution of the present invention does not require increasing the size of the isolation structure (STI space), so there is no need to increase the chip size (chip size), and the unit cost of the device will not increase. There is no need to reduce the doping dose of the LDD doping region (LDD dose), and the BVDs of the device will not be affected due to reducing the LDD doping, and the risk of device breakdown will not increase. Nor is it necessary to increase the FLD dose, that is, ion implantation under the isolation region to increase the substrate concentration, reduce depletion, and reduce the punch-through risk of the device. The body effect of the device will not be affected thereby, resulting in a reduction in voltage transfer efficiency. The breakdown risk of the device can be reduced without making the above sacrifices. Additionally, as Figure 12 shown, a voltage-current curve graph showing an example of forming a virtual structure and not forming a virtual structure using the present invention is presented. From the TCAD simulation data in the graph, it can be seen that the punch BV has increased by 0.8 V.

[0073] As an example, LDD doped regions are further formed on both sides of the gate structure in the active region. Among them, for peripheral devices (e.g., HVNMOS), having an LDD doped region between the source / drain and the gate structure can reduce the electric field when a high voltage is applied to the drain. It should be noted that the LDD doped region is the well-known lightly doped drain region (Lightly Doped Drain) in the art.

[0074] In addition, as Figures 5-11 shown and referring to Figures 1-4 , the present invention also provides a method for manufacturing a semiconductor device structure. Among them, the semiconductor device structure in the above solution of the present invention is preferably manufactured by the method for manufacturing the semiconductor device structure of the present invention. Of course, it can also be manufactured by other methods. The manufacturing method includes the following steps:

[0075] First, as Figure 5 in S1 of Figure 6 and as shown in

[0076] , a semiconductor substrate 100 is provided. The semiconductor substrate 100 can be any semiconductor substrate described in the semiconductor device structure in this embodiment, which will not be elaborated here.

[0076] Next, as Figure 5 in S2 of Figure 7 and as shown in

[0077] , a plurality of active regions 101 and isolation structures 102 are formed in the semiconductor substrate 100. The active regions 101 and the isolation structures 102 are alternately arranged at intervals along a first direction. The active regions 101 extend along a second direction, and the first direction is perpendicular to the second direction. The active regions and the isolation structures can refer to any semiconductor substrate described in the semiconductor device structure in this embodiment, which will not be elaborated here.

[0077] In addition, in one example, ion implantation is also performed in the semiconductor substrate 100 to form a well region 100a before forming the active region 101 and the isolation structure 102. The active region 101 and the isolation structure 102 are formed in the well region 100a. Among them, the well region 100a of peripheral devices (such as bit line driver transistors) may include a p-type doped well for n-channel MOSFETs and an n-type doped well for p-channel MOSFETs, and are respectively referred to as a p-well and an n-well. The dopant distribution and concentration of the well affect the device characteristics of peripheral devices. For MOSFET devices with a low threshold voltage (Vt), the well can be doped at a lower concentration, and a low-voltage p-well or a low-voltage n-well can be formed. For MOSFETs with a high Vt, the well can be doped at a higher concentration, and a high-voltage p-well or a high-voltage n-well can be formed. In some embodiments, in order to provide electrical isolation from the p-type substrate, a deep n-well can be formed under the high-voltage p-well for n-channel MOSFETs with a high Vt (also referred to as a high-voltage nMOSFET or HV NMOS 450-3). Among them, the formation of the n-well can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. The formation of the p-well can include any suitable p-type dopant, such as boron. The incorporation of dopants can be achieved by ion implantation followed by activation annealing, or by in-situ doping of the active device region during epitaxy.

[0078] As an example, a method for forming an isolation structure 102 is provided, and the well region or substrate material around the isolation structure 102 forms an active region. Among them, the isolation structure 102 can be formed by patterning the substrate using photolithography and etching, filling an insulating material, and polishing the insulating material to form a coplanar surface on the semiconductor substrate 100, which can be STI. The insulating material for STI can include silicon oxide, silicon oxynitride, TEOS, low-temperature oxide (LTO), high-temperature oxide (HTO), silicon nitride, etc. The insulating material of STI can be deposited using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), low-voltage chemical vapor deposition (LPCVD), high-density plasma (HDP) chemical vapor deposition, rapid thermal chemical vapor deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), sputtering, thermal oxidation or nitridation, or any combination thereof. The formation of STI can also include a high-temperature annealing step to densify the provided insulating material to improve electrical isolation. Of course, other STI structures can be adopted.

[0079] Next, as Figure 5 in S3 and Figures 8-10As shown, a gate structure 103 and a dummy structure 104 are fabricated on the semiconductor substrate 100. The gate structure 103 is at least formed on the active region 101, and the dummy structure 104 is at least formed on the isolation structure 102 between adjacent active regions 101, and there is a spacing between the gate structure 103 and the dummy structure 104 in the second direction. The structural features of the gate structure 103 and the dummy structure 104 can be referred to the description in the semiconductor device structure part of this embodiment, which will not be elaborated here.

[0080] As an example, the gate structure 103 and the dummy structure 104 are fabricated simultaneously based on the same process. The dummy structure 104 and the gate structure 103 are fabricated simultaneously based on the same process. The introduction of the dummy structure 104 does not require any change in process conditions and steps, and the process is simple and feasible.

[0081] As an example, the gate structure 103 includes a plurality of gate units 107 corresponding to the active regions 101 one by one. The gate units 107 span across the corresponding active regions 101 in the first direction, and each of the gate units 107 is electrically connected based on the same metal layer 108.

[0082] As an example, the gate structure 103 includes a strip-shaped gate that spans across each of the active regions 101 in the first direction.

[0083] As an example, in the first direction, there is a spacing between adjacent gate units 107, and the projection in the first direction of the dummy structure 104 between the gate units 107 corresponding to two adjacent active regions 101 and the active regions 101 overlaps.

[0084] In one example, a method for forming the gate structure 103 and the dummy structure 104 is provided. The gate structure 103 and the dummy structure 104 can be formed simultaneously without adding extra process steps. A mask material layer can be first formed on the semiconductor substrate 100, and then patterned to obtain graphic windows corresponding to the gate structure and the dummy structure, and then gate materials are formed in the windows to obtain the gate structure and the dummy structure. For example, the gate material layer formed in the windows can include a gate dielectric and a gate conductor layer formed on the gate dielectric.

[0085] In one example, the gate dielectric can be made of silicon oxide, silicon nitride, silicon oxynitride, and / or a high-k dielectric film (such as a hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide film and / or a combination thereof). The gate dielectric can be set by any suitable method, such as CVD, PVD, PECVD, LPCVD, RTCVD, sputtering, MOCVD, ALD, thermal oxidation or nitridation, or a combination thereof. In another example, the gate conductor can be made of a metal or a metal alloy, such as tungsten, cobalt, nickel, copper, or aluminum and / or a combination thereof. In some embodiments, the gate conductor can also include a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), etc. The gate conductor can be formed by any suitable deposition method, such as sputtering, thermal evaporation, electron beam evaporation, ALD, PVD, and / or a combination thereof. In other examples, the gate conductor can also include a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, and any other suitable material, and / or a combination thereof. In some embodiments, the polycrystalline material can be combined with any suitable type of dopant (such as boron, phosphorus, or arsenic, etc.). In some embodiments, the gate conductor can also be an amorphous semiconductor having the above materials.

[0086] As an example, after forming the gate structure 103 and the dummy structure 104, the method further includes the step of ion implanting the active region 101 to form a source doping region 105 and a drain doping region 106 on both sides of the gate structure 103 to respectively prepare the source and drain of the device.

[0087] As an example, after forming the source doping region 105 and the drain doping region 106, the method further includes the step of ion doping the active region 101 on both sides of the gate structure 103 to form an LDD doping region (not shown in the figure).

[0088] Wherein, for the structural features and descriptions of the source doping region 105, the drain doping region 106, and the LDD doping region formed based on the above two examples, reference can be made to the description of this embodiment in the semiconductor device structure, which will not be elaborated herein.

[0089] Among them, in one example, the source / drain is combined with a high-concentration dopant. For example, for an n-type MOSFET, the dopant for the source / drain may include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. For a p-type MOSFET, the dopant for the source / drain 460-1 may include any suitable p-type dopant, such as boron. Dopant incorporation can be achieved by ion implantation followed by dopant activation annealing. The source / drain can be made of the same material as the semiconductor substrate, for example, silicon. In some embodiments, the source / drain can be made of a material different from the semiconductor substrate 100 to achieve high performance. For example, on a silicon substrate, the source / drain for a p-type MOSFET may include SiGe, and the source / drain 460-2 for an n-type MOSFET may be combined with carbon. Forming the source / drain with different materials may include back-etching the substrate material in the source / drain region and using techniques such as epitaxy to set a new source / drain material. Doping of the source / drain can also be achieved by in-situ doping during epitaxy.

[0090] In addition, optional source / drain extensions (LDD doped regions) and / or halo regions (not shown in the figure) can be prepared along each side of the gate structure. The source / drain extensions and / or halo regions are located inside the active device region below the gate stack layer and can be implemented for improved short-channel control of peripheral devices with a channel length less than about 0.5 μm. The formation of the source / drain extensions and / or halo regions can be similar to the formation of the source / drain, but different implantation conditions (such as dose, angle, energy, species, etc.) can be used to obtain an optimized doping profile, depth, or concentration.

[0091] As an example, the virtual structure 104 is correspondingly located between the source doping regions 105 adjacent to the active region 101 or between the drain doping regions 106. In addition, according to the description in the above semiconductor device structure, the virtual structure 104 can also be simultaneously disposed between the adjacent source doping regions 105 and the drain doping regions 106, that is, the projection of the virtual structure 104 on the isolation structure 102 is located between the source doping regions 105 and / or the projection of the virtual structure 104 on the isolation structure 102 is located between the drain doping regions 106. In a further example, in the first direction, the virtual structure 104 further extends to form an overlapping region above the source doping regions 105 or the drain doping regions 106 of two adjacent active regions 101. Among them, along the first direction, the size d of the overlapping region is between 1 / 5 and 1 / 3 of the size of the corresponding source doping region or drain doping region.

[0092] In summary, for the semiconductor device structure and its manufacturing method of the present invention, a virtual structure is fabricated on the isolation structure between adjacent active regions. The projection of the virtual structure on the isolation structure is located between the source doping regions or between the drain doping regions, and can further extend above the adjacent source doping region or drain doping region to form an overlapping region, which can block part of the ion implantation, effectively improve the breakdown voltage of the bit line memory, reduce the breakdown risk. The virtual structure and the gate structure can be fabricated simultaneously without changing any process conditions and steps, and the process is simple and feasible. The virtual structure of the present invention can not increase the device area additionally. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device structure, characterized in that, The semiconductor device structure includes: a semiconductor substrate; a plurality of active regions and isolation structures located within the semiconductor substrate, the active regions and the isolation structures being alternately arranged at intervals in a first direction, an isolation structure being formed between two adjacent active regions in the first direction, the active regions extending in a second direction, the first direction being perpendicular to the second direction; a gate structure located at least on the active regions; and a dummy structure located at least on the isolation structures, and there being a spacing between the gate structure and the dummy structure in the second direction; source doping regions and drain doping regions are further formed on both sides of the gate structure in the active regions, the dummy structure being located between the source doping regions and / or the dummy structure being located between the drain doping regions; the source doping regions and the drain doping regions serve as the source and drain of the device and are arranged in the second direction.

2. The semiconductor device structure according to claim 1, characterized in that, The gate structure and the dummy structure are made of the same material and have the same height.

3. The semiconductor device structure according to claim 1, wherein The gate structure includes a plurality of gate units corresponding one-to-one to the active regions, each gate unit spanning the corresponding active region in the first direction, and each of the gate units being electrically connected based on the same metal layer.

4. The semiconductor device structure according to claim 3, wherein, There is a spacing between adjacent gate units, and the projections of the dummy structures corresponding to the two gate units corresponding to two adjacent active regions in the first direction overlap with the active regions.

5. The semiconductor device structure according to claim 1, wherein The gate structure includes a strip-shaped gate that spans across each of the active regions in the first direction.

6. The semiconductor device structure according to claim 1, characterized in that, Lightly doped drain regions are further formed on both sides of the gate structure in the active regions.

7. The semiconductor device structure according to claim 1, wherein, The semiconductor device structure is a bit line driver.

8. The semiconductor device structure according to any one of claims 1-7, characterized in that, In the first direction, the dummy structure extends above the source doping region to form an overlapping region, or the dummy structure extends above the drain doping region to form the overlapping region, and the width d of the overlapping region in the first direction is 0.05 - 0.2 μm.

9. The semiconductor device structure according to claim 8, wherein In the first direction, the size of the overlapping region is between 1 / 5 - 1 / 3 of the size of the corresponding source doping region or drain doping region.

10. A method for preparing a semiconductor device structure, characterized in that, The manufacturing method includes the following steps: providing a semiconductor substrate; forming a plurality of active regions and isolation structures in the semiconductor substrate, the active regions and the isolation structures being alternately arranged at intervals in a first direction, an isolation structure being formed between two adjacent active regions in the first direction, the active regions extending in a second direction, the first direction being perpendicular to the second direction; fabricating a gate structure and a dummy structure on the semiconductor substrate, wherein the gate structure is formed at least on the active regions, the dummy structure is formed at least on the isolation structures, and there is a spacing between the gate structure and the dummy structure in the second direction; Ion implantation is performed on the active region to form a source doping region and a drain doping region on both sides of the gate structure, and the dummy structure is located between the source doping regions and / or the dummy structure is located between the drain doping regions; the source doping region and the drain doping region serve as the source and drain of the device and are arranged along the second direction.

11. The manufacturing method of the semiconductor device structure according to claim 10, characterized in that, The gate structure and the dummy structure are prepared simultaneously based on the same process.

12. The method for preparing a semiconductor device structure according to claim 10, wherein, The gate structure includes a plurality of gate units corresponding to the active regions one by one. Each gate unit spans across the corresponding active region in the first direction, and the gate units are electrically connected based on the same metal layer; alternatively, the gate structure includes a strip-shaped gate that spans across each active region in the first direction.

13. The method for manufacturing a semiconductor device structure according to claim 12, wherein, There is a spacing between adjacent gate units, and the projection of the dummy structure between the gate units corresponding to adjacent active regions and the active regions in the first direction has an overlap.

14. The method for preparing a semiconductor device structure according to claim 10, wherein After forming the source doping region and the drain doping region, the following step is further included: ion doping is performed on the active regions on both sides of the gate structure to form a lightly doped drain region.

15. The method for manufacturing a semiconductor device structure according to claim 10, wherein In the first direction, the dummy structure extends above the source doping region to form an overlapping region, or the dummy structure extends above the drain doping region to form the overlapping region. The width d of the overlapping region in the first direction is 0.05 - 0.2 μm.

16. The method for preparing the semiconductor device structure according to claim 15, characterized in that, Along the first direction, the size of the overlapping region is between 1 / 5 and 1 / 3 of the size of the corresponding source doping region or drain doping region.

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