Semiconductor structure and preparation method thereof, three-dimensional memory and storage system

Abstract

The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its preparation method, a three-dimensional memory, and a storage system. It can reduce the problems of device structure performance deterioration and even failure caused by poor filling of subsequent filling materials. A semiconductor structure comprises: a stacked structure and an insulating portion, the stacked structure comprising a plurality of insulating layers and a plurality of gate conductive layers alternately stacked along a first direction; the stacked structure has a first core region and a step region; in the step region, the stacked structure is divided into a wall and a step structure arranged in sequence along a third direction, a groove penetrating the wall along the third direction is provided on the upper surface of the wall, the step structure comprises a first step cluster and a second step cluster arranged along a second direction, the second step cluster is farther away from the first core region than the first step cluster, the first step cluster and the second step cluster are both in contact with the sidewall of the wall, and the second step cluster is located below the groove, and the insulating portion is embedded in the groove.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a three-dimensional memory, and a storage system. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, manufacturing technologies such as planar processes become challenging and costly. This causes the storage density of planar memories such as 2D NAND flash memory to approach the upper limit, posing severe challenges to the semiconductor memory industry.

[0003] Three-dimensional memory devices (such as 3D NAND flash memory) overcome these limitations. Specifically, by stacking memory cells three-dimensionally to form a multi-layer structure, they increase storage density and achieve storage capacity several times higher than comparable planar memory devices. However, as the number of layers in a three-dimensional memory device increases, poor filling can occur during the subsequent oxide filling process. Furthermore, the oxide filling material and the steps are made of different materials. Under the same thermal treatment, the difference in expansion coefficients can easily generate significant stress, which can lead to device performance degradation or even failure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a three-dimensional memory, and a storage system, which can reduce problems such as device structure performance deterioration and even failure caused by subsequent poor filling of filling materials.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor structure is provided, comprising: a stacked structure and an insulating portion, wherein the stacked structure comprises a plurality of insulating layers and a plurality of gate conductive layers alternately stacked along a first direction; the stacked structure has a first core region and a step region arranged in sequence along a second direction; in the step region, the stacked structure is divided into walls and step structures arranged in sequence along a third direction, a groove is provided on the upper surface of the wall, and passes through at least two adjacent walls along the third direction; the step structure comprises a first step cluster and a second step cluster arranged along the second direction, the second step cluster is farther away from the first core region than the first step cluster, the first step cluster and the second step cluster are both in contact with the sidewalls of the wall, and the second step cluster is located below the groove; the insulating portion is embedded in the groove and in contact with the sidewalls of the groove; wherein the first step cluster and the second step cluster respectively comprise a plurality of step groups, each step group comprises a plurality of gate conductive patterns arranged in a staircase manner, and each gate conductive pattern is located in one of the plurality of gate conductive layers; the first direction, the second direction and the third direction are perpendicular to each other.

[0007] In some embodiments, among the multiple step groups included in the first step cluster, the step group closest to the groove is the first step group, and at least part of the gate conductive pattern in the first step group is higher than the bottom of the groove.

[0008] In some embodiments, the uppermost gate conductive pattern in the first step group is located in the uppermost gate conductive layer among the plurality of gate conductive layers.

[0009] In some embodiments, the inclination directions of step groups adjacent to the first step group in the first step group and the second step cluster are opposite.

[0010] In some embodiments, among the multiple step groups included in the first step cluster, the step group farthest from the groove is the second step group, and at least part of the gate conductive pattern included in the second step group is higher than the topmost gate conductive pattern included in the step group adjacent to the second step group in the first step cluster.

[0011] In some embodiments, in the second step group, each gate conductive pattern in at least a portion of the gate conductive patterns is located in the same gate conductive layer as at least one gate conductive pattern in the first step group, and the first step group is the step group closest to the groove among the multiple step groups included in the first step cluster.

[0012] In some embodiments, the semiconductor structure further includes a plurality of first gate lines located in the first core region; the step region includes a first sub-region and a second sub-region arranged in sequence along the second direction, the first sub-region is located on the side of the groove close to the first core region, and the groove is located in the second sub-region; the wall includes a plurality of conductive lines; the first step cluster is located in the first sub-region, and a gate conductive pattern contained in the first step cluster is in contact with a first conductive line, and the first conductive line is in contact with a first gate line, the second step cluster is located in the second sub-region, and a gate conductive pattern contained in the second step cluster is in contact with a second conductive line, and the second conductive line is in contact with a first gate line; wherein, the first conductive line is the portion of a conductive line contained in the wall located in the first sub-region, and the second conductive line is the portion of a conductive line contained in the wall located in the first sub-region and the second sub-region.

[0013] In some embodiments, the semiconductor structure also includes: a plurality of first contacts electrically connected to the first step cluster; two gate conductive patterns located in the same gate conductive layer and belonging to different step groups, one of the gate conductive patterns is in contact with at least one of the plurality of first contacts, and the other gate conductive pattern is not in contact with any of the plurality of first contacts.

[0014] In some embodiments, among the multiple step groups included in the first step cluster, a step group at the lowest position is the third step group; among the multiple step groups included in the second step cluster, a step group at the highest position is the fourth step group; the lowest gate conductive pattern in the third step group and the highest gate conductive pattern in the fourth step group are respectively located in two adjacent gate conductive layers among the multiple gate conductive layers.

[0015] In some embodiments, among the multiple step groups included in the same step cluster, the inclination directions of two adjacent step groups are opposite.

[0016] In some embodiments, the stacked structure further comprises: a second core region, located on a side of the step region away from the first core region; and a third step cluster, located on a side of the groove away from the first step cluster, and contacting the sidewall of the wall. The third step cluster comprises a plurality of step groups, each step group comprising a plurality of gate conductive patterns arranged in a staircase pattern, each gate conductive pattern being located in one of the plurality of gate conductive layers.

[0017] In some embodiments, the semiconductor structure further includes a plurality of second gate lines located in the second core region; the step region further includes a third sub-region, the third sub-region being located on the side of the groove away from the first core region; the third step cluster is located in the third sub-region, and a gate conductive pattern contained in the third step cluster is in contact with a third conductive line, the third conductive line is in contact with a second gate line, a gate conductive pattern contained in the second step cluster is in contact with a fourth conductive line, and the fourth conductive line is in contact with a second gate line; wherein, the third conductive line is a portion of a conductive line contained in the wall located in the third sub-region, and the fourth conductive line is a portion of a conductive line contained in the wall located in the second sub-region and the third sub-region.

[0018] In some embodiments, each gate conductive pattern in the plurality of gate conductive patterns in the first step cluster and at least one corresponding gate conductive pattern in the third step cluster are included in the same gate conductive layer.

[0019] On the other hand, a three-dimensional memory is provided, comprising: the semiconductor structure as described above.

[0020] On the other hand, a storage system is provided, comprising a controller and the three-dimensional memory as described above, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0021] In another aspect, a method for preparing a semiconductor structure is provided, comprising:

[0022] An initial stacked structure is formed, where the initial stacked structure includes a plurality of insulating layers and a plurality of sacrificial layers alternately stacked along a first direction.

[0023] The initial stacked structure is divided into a first core region and a step region sequentially arranged along the second direction.

[0024] An initial wall and an initial step structure are formed on the initial stacked structure and located in the step area, arranged in sequence along a third direction. A groove is provided on the upper surface of the initial wall, extending through at least two adjacent initial walls along the third direction. The initial step structure includes a first initial step cluster and a second initial step cluster arranged along a second direction. The first initial step cluster and the second initial step cluster are both in contact with the sidewalls of the initial wall, and the second initial step cluster is located below the groove. The first direction, the second direction, and the third direction are perpendicular to each other. The first initial step cluster and the second initial step cluster each include multiple initial step groups, each initial step group includes multiple sacrificial patterns arranged in a staircase manner, and each sacrificial pattern is located in one of the multiple sacrificial layers.

[0025] The groove is filled with insulating material to form an insulating portion, and the insulating portion is embedded in the groove and in contact with a side wall of the groove.

[0026] The sacrificial layer in the initial stacked structure is replaced with a gate conductive layer to obtain a stacked structure including a plurality of insulating layers and a plurality of gate conductive layers.

[0027] In some embodiments, the initial wall and the initial step structure arranged in sequence along a third direction are formed on the initial stacking structure and located in the step area, including: dividing the portion of the initial stacking structure located in the step area into a wall area and a step partition along the third direction; protecting the portion of the initial stacking structure located in the wall area, and etching the portion of the initial stacking structure located in the step partition to obtain the initial wall located in the wall area and the initial step structure located in the step partition; etching the initial wall to form the groove on the upper surface of the initial wall.

[0028] In some embodiments, the step partitions include a plurality of third sub-regions and a plurality of fourth sub-regions sequentially distributed along the second direction, each third sub-region including: a first protection zone and a first etching zone located on a side of the first protection zone away from the first core zone, and each fourth sub-region including: a second protection zone and a second etching zone located on a side of the second protection zone close to the first core zone; etching the portion of the initial stacked structure located in the step partitions includes: protecting the portion of the initial stacked structure located in the first and second protection zones, and trimming and etching the portion of the initial stacked structure located in the first and second etching zones to obtain a preliminary step structure, the preliminary step structure including a first preliminary step cluster and a second preliminary step cluster sequentially arranged along the second direction, the first preliminary step cluster and the second preliminary step cluster each including a plurality of preliminary step groups, the plurality of preliminary step groups being located at the same level; and for the plurality of preliminary step groups, the inclination directions of two adjacent preliminary step groups along the second direction are opposite; at least all the preliminary step groups included in the second preliminary step cluster are pre-etched so that all the preliminary step groups included in the second preliminary step cluster descend to the same level, thereby obtaining the first preliminary step cluster and the second preliminary step cluster.

[0029] In some embodiments, etching the initial wall and performing a preset etching on all original step groups included in the second initial step cluster are performed simultaneously.

[0030] In some embodiments, further comprising:

[0031] Before etching all the initial step groups included in the second preliminary step cluster, the first preliminary step cluster and the second preliminary step cluster are subjected to multiple preset etchings, so that the multiple preliminary step groups included in the first preliminary step cluster are located at different levels and the multiple preliminary step groups included in the second preliminary step cluster are located at different levels.

[0032] In some embodiments, performing a predetermined number of etchings on the first preliminary step cluster and the second preliminary step cluster includes:

[0033] Multiple sets of mask plates are used to perform multiple preset etchings on the first preliminary step cluster and the second preliminary step cluster. In any two preset etchings, for the first preliminary step cluster and / or the second preliminary step cluster, the edges of the openings of the mask plate used for one etching do not overlap with the edges of the openings of the mask plate used for the other etching in the second direction.

[0034] Embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, a three-dimensional memory, and a storage system. By providing a groove on the upper surface of a wall, since the groove penetrates the wall along a third direction, the filling depth of the oxide filling material on the second step cluster is reduced, and the filling depth-to-width ratio of the oxide filling material on the second step cluster can be reduced, thereby reducing the risk of poor filling. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0036] Figure 1A is a schematic diagram of a three-dimensional structure of a semiconductor structure according to some embodiments;

[0037] Figure 1B for Figure 1A A cross-sectional view of a memory cell string in the semiconductor structure shown along section line AA;

[0038] Figure 1C A three-dimensional structural diagram of the wall and step structure in an array device provided for related technology;

[0039] Figure 1D A three-dimensional structural diagram of the wall and step structure in another array device provided for related technology;

[0040] Figure 1E A structural diagram showing contact points and gate conductive patterns according to some embodiments;

[0041] Figure 2A is a three-dimensional structural diagram of a wall and step structure in a semiconductor structure according to some embodiments;

[0042] Figure 2B for Figure 2A Enlarged view of the middle Q region;

[0043] Figure 2C A structural diagram of a semiconductor structure in which a step region is divided into a first sub-region, a second sub-region, and a third sub-region according to some embodiments;

[0044] Figure 2D is a top view of a gate conductive pattern in a step group G2 and a step group G8 connected to a first gate line according to some embodiments;

[0045] Figure 2E is a structural diagram of an insulating portion embedded in a groove according to some embodiments;

[0046] Figure 2F A structural diagram showing a semiconductor structure in which a first step group and a fifth step group divide a groove structure into three groove structures according to some embodiments;

[0047] Figure 2G is a top view of a gate conductive pattern in a step group G17 and a step group G8 connected to a second gate line according to some embodiments;

[0048] Figure 3A is a structural block diagram of a storage system according to some embodiments;

[0049] Figure 3B is a structural block diagram of a storage system according to some other embodiments;

[0050] Figure 4A is a perspective view of forming an initial stacked structure according to some embodiments;

[0051] Figure 4B A diagram showing a structure for forming partition steps according to some embodiments;

[0052] Figure 4C A structural diagram of forming an initial wall and an initial step structure according to some embodiments;

[0053] Figure 4D A structural diagram of dividing a step area into a wall area and a step area according to some embodiments;

[0054] Figure 4E is a structural diagram of dividing a step zone into a fourth sub-zone and a fifth sub-zone according to some embodiments;

[0055] Figure 4F A structural diagram of forming a preliminary step structure according to some embodiments;

[0056] Figure 4G is a top view of a mask pattern for forming a preliminary step structure according to some embodiments;

[0057] Figure 4H is a flow chart of forming a preliminary step structure according to some embodiments;

[0058] Figure 4I A structural diagram showing a first preliminary step cluster including multiple preliminary step groups located at different levels and a second preliminary step cluster including multiple preliminary step groups located at different levels according to some embodiments;

[0059] Figure 4Jis a flow chart of performing a first preset etching on a first preliminary step cluster and a second preliminary step cluster according to some embodiments;

[0060] Figure 4K is a flow chart of performing a second preset etching on a first preliminary step cluster and a second preliminary step cluster according to some embodiments;

[0061] Figure 4L is a flow chart of performing a third preset etching on a first preliminary step cluster and a second preliminary step cluster according to some embodiments;

[0062] Figure 4M 4 is a flow chart of performing a fourth predetermined etching on the first preliminary step cluster and the second preliminary step cluster according to some embodiments. DETAILED DESCRIPTION

[0063] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0064] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0065] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0066] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0067] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0068] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0069] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0070] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0071] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0072] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0073] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0074] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0075] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0076] The term "three-dimensional memory" refers to a semiconductor device formed by arraying strings of memory cell transistors on a major surface of a substrate (referred to herein as "memory cell strings," such as NAND memory cell strings) and extending perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the major surface (i.e., lateral surface) of the substrate.

[0077] Some embodiments of the present disclosure provide a three-dimensional memory device, comprising a semiconductor structure and peripheral devices. The semiconductor structure may also be referred to as an array device.

[0078] The peripheral devices are configured to control and sense the array devices. The peripheral devices may be any suitable digital, analog, and / or mixed signal control and sensing for facilitating the operation of the array devices, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors).

[0079] The peripheral devices may include transistors formed on a substrate, wherein all or a portion of the transistors are formed in the substrate (e.g., below the top surface of the substrate) and / or directly on the substrate. The substrate may be made of a semiconductor material, such as, but not limited to, silicon, germanium, silicon-on-insulator (SOI), etc.

[0080] In some embodiments, the array device can be set above the peripheral device, or the peripheral device can be set above the array device, so that the array device and the peripheral device can be manufactured at the same time, avoiding mutual influence between the peripheral device and the array device during manufacturing, which is not conducive to the temperature selection problem of the subsequent layers during the manufacturing process.

[0081] In some embodiments, the three-dimensional memory device may further include an array interconnect layer, which may be disposed between the array device and the peripheral device, or on a side of the array device away from the peripheral device, or on a side of the peripheral device away from the array device. The array interconnect layer electrically connects the peripheral device and the array device, thereby transmitting electrical signals between different regions of the array device, or between the peripheral device and the array device.

[0082] In some embodiments, the array interconnect includes multiple interconnect layers and contact layers. In some embodiments, the interconnect layers include multiple metal layers. The metal layers can be made of tungsten, copper, aluminum, or other suitable materials. In some embodiments, the contact layers can be made of tungsten, copper, aluminum, or other suitable materials.

[0083] Some embodiments of the present disclosure provide a semiconductor structure 100, such as Figure 1A to Figure 1E As shown, it includes: a substrate 104, a stacked structure 101 provided on the substrate 104, and the stacked structure 101 may include a plurality of insulating layers alternately stacked along a first direction Z (such as Figure 1E 101a) and multiple gate conductive layers 101b. In some embodiments, the substrate 104 can be made of a semiconductor material, including but not limited to silicon, germanium, silicon-on-insulator (SOI), etc. In some embodiments, the gate conductive layer 101b is made of a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, doped silicon, and / or silicide. The insulating layer 101a is made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination of the above materials.

[0084] In some embodiments, as Figure 1A and Figure 1BAs shown, the array device 100 also includes a plurality of memory cell strings 103, which extend along a first direction Z and penetrate the stacked structure 101. A memory cell string 103 includes a channel structure 102, and the channel structure 102 includes a semiconductor channel layer and a dielectric layer. The dielectric layer includes a tunnel layer, a memory cell layer, and a barrier layer. Electrons or holes in the semiconductor channel layer can tunnel into the memory cell layer through the tunnel layer. The memory cell layer is used to store charge. The storage or removal of charge in the memory cell layer determines the switching state of the semiconductor channel layer. In some embodiments, the material of the semiconductor channel layer includes amorphous silicon, polycrystalline silicon, or single crystal silicon. The tunnel layer is made of silicon oxide, silicon nitride, or a combination thereof. The material of the barrier layer includes silicon oxide, silicon nitride, a high dielectric constant insulating material, or a combination thereof. The material of the memory cell layer includes silicon nitride, silicon oxynitride, silicon, or a combination of the above materials.

[0085] In some embodiments, as Figure 1A and Figure 1B The gate conductive layer 101b in the stacked structure 101 is used as a selection gate or word line for the plurality of memory cell strings 103. For example, along the first direction Z, the bottommost gate conductive layer 101b in the multilayer gate conductive layer 101b is configured as a source select gate SGS, the topmost gate conductive layer 101b in the multilayer gate conductive layer 101b is configured as a drain select gate SGD (also referred to as a top select gate), and the middle gate conductive layer 101b in the multilayer gate conductive layer 101b is configured as a plurality of word lines WL (see FIG. 1 ). Figure 1B Herein, the select gate and word line are collectively referred to as gate line WL_0. In some embodiments, the select gate and word line WL are made of a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, doped silicon, and / or silicide.

[0086] like Figure 1B As shown, one memory cell string 103 is equivalent to the storage capacity of multiple planar memory cells. Therefore, a three-dimensional memory can provide a larger storage capacity.

[0087] In order to transmit the selection terminal signal or the word line signal to each gate line, in some embodiments, as Figure 1A 、 Figure 1C 、 Figure 1D and Figure 2A As shown, the stacked structure 101 includes a first core region A1 and a step region B sequentially arranged along the second direction X. A plurality of memory cell strings 103 are arranged in the first core region A1. Figure 2C As shown, the plurality of gate lines WL_0 include a plurality of first gate lines WL_01 located in the first core area A1. Figure 1C 、 Figure 1D and Figure 2AAs shown, in the step area B, the laminated structure 101 is divided into walls 11 and step structures 21 arranged in sequence along the third direction Y. The first direction Z, the second direction X and the third direction Y are perpendicular to each other. Figure 1A As shown, the semiconductor structure 100 further includes a plurality of contacts K (the plurality of contacts K may include, for example, a drain select gate contact SGD CNT, a source select gate contact SGS CNT, a source contact SL CNT, and a word line contact WL CNT). Figure 2A As shown, the step structure 21 includes a first step cluster 211 and a second step cluster 212 arranged along the second direction X. The second step cluster 212 is farther away from the first core area A1 than the first step cluster 211. The first step cluster 211 and the second step cluster 212 are both in contact with the side wall of the wall 11. The first step cluster 211 and the second step cluster 212 each include a plurality of step groups G. For example, the plurality of step groups G included in the first step cluster 211 are sequentially G1 to G7 along the second direction X, and the plurality of step groups G included in the second step cluster 212 are sequentially G8 to G11 along the second direction X. Combined Figure 2A and Figure 2C Each step group G includes a plurality of gate conductive patterns GM arranged in a stairway, and each gate conductive pattern GM is located in one gate conductive layer 101b among the plurality of gate conductive layers 101b.

[0088] In some embodiments, the semiconductor structure 100 further includes a source terminal SL located below the source select gate SGS. In some examples, multiple memory cell strings 103 share the source terminal SL.

[0089] In some embodiments, the semiconductor structure 100 further includes a bit line BL, and the bit line BL is electrically connected to the memory cell string 103 through a bit line contact BL CNT.

[0090] It should be noted that the plurality of memory cell strings 103 form a memory cell array in the XY plane. The second direction X and the third direction Y are, for example, two orthogonal directions in the memory cell array: the second direction X is, for example, the extension direction of the word lines WL, and the third direction Y is, for example, the extension direction of the bit lines BL. The first direction Z is perpendicular to the XY plane.

[0091] In order to realize the block storage of storage area, such as Figure 1C 、 Figure 1D and Figure 2A As shown, the semiconductor structure 100 further includes isolation trenches St for dividing the stacked structure 101 into a plurality of memory blocks R. The plurality of memory blocks R are arranged in a third direction Y, with adjacent memory blocks R separated by the isolation trenches st. In some examples, the isolation trenches St penetrate the stacked structure 101 along the first direction Z and extend at least along the second direction X.

[0092] Here, taking two adjacent memory blocks R forming a memory block group as an example, the two memory blocks R in a memory block group can share a separate partitioned step structure (separated by an isolation trench St), and the two memory blocks R are mirror-symmetrical. Each partitioned step structure can include M steps, each step includes multiple sub-partitions in the third direction, the height difference between adjacent steps is the height of N steps, and the height difference between adjacent sub-partitions is the height of 1 step, where M is a natural number greater than or equal to 1, thereby forming a two-dimensional composite three-dimensional step structure.

[0093] Among them, a step S can be composed of a composite layer, including an insulating layer and a gate conductive layer. In this case, the height of a step S is the height of a composite layer. At this time, the height of a step can be the height of the steps of the number of partitions, that is, the height difference between adjacent steps is the height of the steps of the number of partitions, that is, N is equal to the number of partitions.

[0094] For example, when each step includes 2 sub-partitions, the height of one step is the height of 2 steps; when each step includes 3 sub-partitions, the height of one step is the height of 3 steps; and so on. When each step includes N sub-partitions, the height of one step is the height of N steps.

[0095] like Figure 2B The structure in which each step includes two sub-partitions in the third direction Y is shown, and each sub-partition step structure can form two steps S in the third direction Y. Figure 2A As shown, each partitioned step structure may include two mirror-symmetrical step structures 21 , the two step structures 21 are separated by an isolation trench St, and each step structure 21 contacts a side wall of a wall 11 .

[0096] Here, taking each step group G of each step structure 21 including 30 steps S as an example, the levels of the steps S close to the wall 11 can be the 1st, 3rd, 5th, 7th, 9th, 11th, ..., 29th level from bottom to top, and the levels of the step structure 21 away from the wall 11 can be the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, 16th, ..., 30th level from bottom to top. Figure 2A and Figure 2C As shown, the gate conductive pattern GM of each step S is located in the same layer as a gate line (such as the first gate line WL_01 ).

[0097] In order to clearly illustrate the steps S, the following explanation is made: each step S extends laterally (for example, along the Y-axis direction) farther than any steps S located at a higher level. In other words, each step S protrudes laterally than any steps S located at a higher level, so that the shape of the horizontal cross-section of the step group (for example, the cross-section in the XY plane) changes in the step group according to the vertical distance from the top surface of the substrate or source layer (that is, the side located at a higher level of the two side surfaces opposite to each other along the Z-axis direction).

[0098] The above describes the basic structure of the three-dimensional memory. As the storage capacity of the three-dimensional memory becomes higher and higher, the number of layers of the stacked structure 101 becomes higher and higher. For example, the number of layers of the stacked structure 101 can reach 96 layers or even 144 layers. However, as the number of layers of the stacked structure 101 becomes higher and higher, Figure 1C and Figure 1D As shown, when the oxide filling material is subsequently filled, the filling depth of the oxide filling material on the step structure 21 becomes larger and larger. According to the material properties of the oxide filling material, the aspect ratio of the oxide filling material during filling (the ratio of the filling depth to the width, the width refers to the size of the structure to be filled along the third direction Y, which may refer to the size of the partitioned step structure along the third direction Y, that is, the size between the two walls 11) is limited to a certain extent. This causes poor filling when the aspect ratio exceeds the limit. For example, some oxide filling materials may be sealed prematurely when filled deeper. This will cause filling voids, and the stress is more concentrated at the sealing location. Cracks will appear when encountering external force or during subsequent annealing, leading to problems such as deterioration of device structural performance or even failure.

[0099] Based on this, in some embodiments, such as Figure 2A and Figure 2C As shown, a groove 111 is provided on the upper surface of the wall 11 and passes through at least two adjacent walls along the third direction Y, and the second step cluster 212 is located below the groove 111 .

[0100] The upper surface of the wall 11 is the surface for the contact to pass through, that is, the direction of the step S in the step structure 12 is upward, and conversely, the direction away from the step S is downward. The second step cluster 212 is located below the groove 111, which means that the gate conductive pattern GM of the top layer of the second step cluster 212 is flush with the bottom of the groove 111, or the gate conductive pattern GM of the top layer of the second step cluster 212 is lower than the bottom of the groove 111.

[0101] In these embodiments, the groove 111 is provided on the upper surface of the wall 11. Since the groove 111 penetrates the wall 11 along the third direction, Figure 1C and Figure 1DIn comparison, this is equivalent to reducing the filling depth of the oxide filling material on the second step cluster 212 , which can reduce the filling aspect ratio of the oxide filling material on the second step cluster 212 , thereby reducing the risk of poor filling.

[0102] In some embodiments, combined Figure 2A 、 Figure 2C and Figure 2D Step region B includes a first sub-region B1 and a second sub-region B2 arranged sequentially along the second direction. First sub-region B1 is located on the side of groove 111 close to first core region A1, while groove 111 is located in second sub-region B2. Wall 11 includes multiple conductive lines. A first step cluster 211 is located in first sub-region B1. A gate conductive pattern GM included in first step cluster 211 contacts a first conductive line DL1, which in turn contacts a first gate line WL_01. A second step cluster 212 is located in second sub-region B2. A gate conductive pattern GM included in second step cluster 212 contacts a second conductive line DL2, which in turn contacts a first gate line WL_01. The first conductive line WL_01 is the portion of a conductive line included in wall 11 located in first sub-region B1, and the second conductive line DL2 is the portion of a conductive line included in wall 11 located in first sub-region B1 and second sub-region B2.

[0103] That is, in these embodiments, for the first step cluster 211, a gate conductive pattern GM contained therein can be electrically connected to a first gate line WL_01 of the first core area A1 through a first conductive line DL1. That is, the gate conductive pattern GM, the first conductive line DL1, and the first gate line WL_01 connected to the gate conductive pattern GM contained in the first step cluster 211 belong to the same gate conductive layer 101b. For the second step cluster 212, a gate conductive pattern GM contained therein can be electrically connected to a first gate line WL_01 of the first core area A1 through a second conductive line 204. That is, the gate conductive pattern GM, the second conductive line 204, and the first gate line WL_01 connected to the gate conductive pattern GM contained in the second step cluster 212 belong to the same gate conductive layer 101b. By connecting contacts on the gate conductive patterns GM contained in each of the first step cluster 21 and the second step cluster 22, signals can be transmitted to the first gate lines WL_01 connected to each of them.

[0104] For example, the gate conductive pattern GM included in the first step cluster 211 belongs to the step group G2, and the gate conductive pattern GM included in the second step cluster 212 belongs to the step group G8. The gate conductive pattern GM included in the step group G2 is electrically connected to a first gate line WL_01 in the first core region through a first conductive line DL1. Figure 2DAs shown, the gate conductive pattern GM included in the step group G2 is electrically connected to a first gate line WL_01 of the first core area A1 through a second conductive line DL2. Figure 2D shown.

[0105] It should be noted that the above shows a situation where the gate conductive patterns GM included in the step group G2 and the step group G8 are located in different gate conductive layers. Those skilled in the art can understand that when the gate conductive patterns GM included in the step group G2 and the step group G8 are located in the same gate conductive layer, the gate conductive pattern GM included in the step group G2 is electrically connected to a first gate line WL_01 of the first core area A1 through the first conductive line DL1, the second conductive line DL2 includes the first conductive line DL1, and the gate conductive patterns GM included in the step group G2 and the step group G8 are both connected to the same first gate line WL_01.

[0106] In some embodiments, the contact K is made of a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, and / or silicide.

[0107] In some embodiments, combined Figure 2C and Figure 2E As shown, the semiconductor structure further includes an insulating portion 112 , which is embedded in the groove 111 and contacts the sidewall of the groove 111 .

[0108] In these embodiments, the material of the insulating portion 112 may be an oxide material, that is, Figure 2E FIG. 1 shows a structure after the groove 111 is filled with oxide.

[0109] Of course, in other embodiments, the insulating portion 112 can also be arranged above the first step cluster 211 and the second step cluster 212, that is, the area where the step group included in the first step cluster 211 and the second step cluster 212 is located is filled. The final product can be a structure in which the first step cluster 211, the second step cluster 212 and the groove 111 are all filled with oxide material, and the contact K passes through the oxide material and is electrically connected to the first step cluster 211 and the second step cluster 212.

[0110] In some embodiments, as Figure 2A As shown, among the multiple step groups G included in the first step cluster 211, the step group closest to the groove 111 is the first step group. Figure 2A In G7 , at least a portion of the gate conductive pattern GM in the first step group is higher than the bottom 111 a of the groove 111 .

[0111] At least part of the gate conductive pattern GM in the first step group is higher than the bottom 111a of the groove 111 means that part of the gate conductive pattern GM in the first step group is higher than the bottom 111a of the groove 111, or all of the gate conductive patterns GM in the first step group are higher than the bottom 111a of the groove 111. Here, when part of the gate conductive pattern GM in the first step group is higher than the bottom 111a of the groove 111, the lowermost gate conductive pattern GM in the first step group is flush with the bottom 111a of the groove 111, or at least the lowermost gate conductive pattern GM in the first step group is lower than the bottom 111a of the groove 111. When all of the gate conductive patterns GM in the first step group are higher than the bottom 111a of the groove 111, the lowermost gate conductive pattern GM in the first step group is higher than the bottom 111a of the groove 111.

[0112] In these embodiments, by making at least part of the gate conductive pattern GM in the first step group higher than the bottom 111a of the groove 111, the first step group can also separate the remaining step groups in the first step cluster 211 from the second step cluster 212. Figure 2F As shown, the first step group separates the remaining step groups in the first step cluster 211 and the second step cluster 212 into two groove structures W2, as shown in FIG. Figure 1D As shown, compared with a large groove structure W1 formed by the first step cluster 211 and the second step cluster 212, when the oxide filling material is filled on the first step cluster 211 and the second step cluster 212, the oxide filling material is filled in the two groove structures W2 respectively, so that the stress generated by the oxide filling material can be decomposed from one groove structure W1 to the two groove structures W2, thereby reducing the defects caused by stress and expansion.

[0113] In addition, compared with the first step cluster 211 and the second step cluster 212 forming a large groove structure W1 , the first step group can also play a supporting role.

[0114] In some embodiments, the gate conductive pattern GM of the uppermost layer DL in the first step group is located in the uppermost gate conductive layer 101 b among the plurality of gate conductive layers 101 b .

[0115] In these embodiments, the uppermost gate conductive pattern GM in the first step group may be flush with the upper surface of the wall 11 , that is, the first step group is at a higher horizontal position and may play a supporting role similar to that of the wall 11 .

[0116] In some embodiments, among the multiple step groups included in the first step cluster 211, the step group farthest from the groove 111 is the second step group. Figure 2AIn G1 , at least part of the gate conductive patterns GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to the second step group in the first step cluster 211 .

[0117] At least part of the gate conductive patterns GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to the second step group in the first step cluster 211. This means that in the first step cluster 211, part of the gate conductive patterns GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to it, or all of the gate conductive patterns GM in the second step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent to it. Here, when part of the gate conductive patterns GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to it, the lowermost gate conductive pattern GM in the second step group is flush with the uppermost gate conductive pattern GM included in the step group adjacent to it, or at least the lowermost gate conductive pattern GM in the second step group is lower than the uppermost gate conductive pattern GM included in the step group adjacent to it. When all of the gate conductive patterns GM in the second step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent to it, the lowermost gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to it.

[0118] In these embodiments, by making at least part of the gate conductive pattern GM in the second step group higher than the uppermost gate conductive pattern GM included in the step group adjacent to the second step group in the first step cluster 211, the second step group can be placed at a higher level, so that when the first step group is at a higher level, as shown in FIG. Figure 2F As shown, the multiple step groups in the first step cluster 211 have a trend of first decreasing and then increasing along the second direction X. Compared with the trend of the multiple step groups in the first step cluster 211 gradually increasing or decreasing along the second direction X, the stress can be decomposed into multiple step groups, thereby avoiding poor filling caused by stress concentration.

[0119] In some embodiments, as Figure 2A As shown, the second step group (such as Figure 2A In G7), at least part of each gate conductive pattern GM in the gate conductive pattern GM is connected to the first step group (such as Figure 2A At least one gate conductive pattern GM in G1) is located in the same gate conductive layer 101b.

[0120] In the second step group, each gate conductive pattern GM of at least some of the gate conductive patterns GM and at least one gate conductive pattern GM in the first step group are located in the same gate conductive layer 101b, which means that in the second step group, each gate conductive pattern GM of some of the gate conductive patterns GM and one of the gate conductive patterns GM in the first step group are located in the same gate conductive layer 101b, or, in the second step group, each gate conductive pattern GM of all the gate conductive patterns GM and one of the gate conductive patterns GM in the first step group are located in the same gate conductive layer 101b.

[0121] like Figure 2A , each of the gate conductive patterns GM in the second step group and one of the gate conductive patterns GM in the first step group are located in the same gate conductive layer 101b. Those skilled in the art will appreciate that this only illustrates the case where the number of gate conductive patterns GM in the first and second step groups is the same, and the uppermost gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM in the first step group (e.g., the uppermost gate conductive pattern GM in the second step group is flush with the uppermost gate conductive pattern GM in the first step group, or the height of the uppermost gate conductive pattern GM in the second step group is higher than the height of the uppermost gate conductive pattern GM in the first step group). In some embodiments, the number of gate conductive patterns GM in the first step group and the number of gate conductive patterns GM in the second step group may also be different. In this case, the uppermost gate conductive pattern GM in the second step group is higher than the uppermost gate conductive pattern GM in the first step group, or the uppermost gate conductive pattern GM in the first step group is higher than the uppermost gate conductive pattern GM in the second step group. This is not specifically limited herein.

[0122] In some embodiments, the plurality of contacts K may include a plurality of first contacts coupled to the first step cluster 211. Of the two gate conductive patterns GM located in the same gate conductive layer 101b and belonging to different step groups, one gate conductive pattern GM contacts at least one of the plurality of first contacts, and the other gate conductive pattern GM contacts none of the plurality of first contacts.

[0123] like Figure 2A As shown, taking two gate conductive patterns GM located in the same gate conductive layer 101b and belonging to different step groups, which belong to the first step group and the second step group respectively, as an example, all the gate conductive patterns GM in the second step group and at least one gate conductive pattern GM in the first step group are located in the same gate conductive layer 101b, and all of the multiple contacts can be in contact with the second step group. In this case, the first step group serves as a virtual step group and plays a supporting role. Alternatively, some of the multiple contacts are in contact with the first step group, and the rest are in contact with the second step group. In this case, while the second step group plays a supporting role, some steps in the second step group also play an electrical connection role.

[0124] In other embodiments, two gate conductive patterns GM located in the same gate conductive layer 101b and belonging to different step groups are in contact with different first contacts, respectively. That is, the first step group plays a supporting role, and all steps in the first step group play an electrical connection role.

[0125] In some embodiments, among the multiple step groups included in the first step cluster 211, the step group at the lowest position is the third step group. Figure 2A In G4, among the step groups included in the second step cluster 212, the step group at the highest position is the fourth step group, such as Figure 2A In G8 , the lowermost gate conductive pattern GM in the third step group and the uppermost gate conductive pattern GM in the fourth step group are located in two adjacent gate conductive layers 101 b among the plurality of gate conductive layers 101 b .

[0126] In these embodiments, by locating the lowest gate conductive pattern in the third step group and the highest gate conductive pattern in the fourth step group in two adjacent gate conductive layers 101b among the multiple gate conductive layers 101b, the step structure 21 can be effectively and fully utilized to achieve signal transmission for all gate lines.

[0127] In some embodiments, among the multiple step groups included in the same step cluster, the inclination directions of two adjacent step groups are opposite.

[0128] like Figure 2A As shown, in the first step cluster 211, the first step group (G1) arranged sequentially along the second direction X is inclined in the negative direction of the second direction X, the second step group (G2) arranged sequentially along the second direction X is inclined in the positive direction of the second direction X, and the third step group (G3) arranged sequentially along the second direction X is inclined in the negative direction of the second direction X. In the second step cluster 212, the first step group (G8) arranged sequentially along the second direction X is inclined in the negative direction of the second direction X, the second step group (G9) arranged sequentially along the second direction X is inclined in the positive direction of the second direction X, and the third step group (G10) arranged sequentially along the second direction X is inclined in the negative direction of the second direction X.

[0129] In these embodiments, compared to the case where the inclination directions of two adjacent step groups are the same, when the inclination directions of two adjacent step groups are opposite, on the one hand, during the manufacturing process, the two adjacent step groups can be obtained by trimming and etching through the same mask pattern, which can reduce the amount of mask plates used and the number of trimming and etching times. On the other hand, under this structure, the step groups in the final step structure 21 can be staggered with each other, making the step groups more dispersed, and the step structure 21 can be broken down into small pieces, decomposing the stress onto the step groups, thereby avoiding stress concentration and further improving the structural stability of the entire semiconductor structure.

[0130] In some embodiments, the inclination directions of the step groups adjacent to the first step group in the first step group and the second step cluster 212 are opposite.

[0131] The step group adjacent to the first step group in the second step cluster 212 refers to the first step group sequentially arranged along the second direction X in the second step cluster 212 , ie, G8 .

[0132] In these embodiments, by making the inclination directions of the step groups adjacent to the first step group in the first step group and the second step cluster 212 opposite, the same technical effect as the opposite inclination directions of the two adjacent step groups in the same cluster is achieved, which will not be repeated here.

[0133] In some embodiments, as Figure 2A As shown, the stacked structure 101 further includes: a second core area A2, which is located on the side of the step area B away from the first core area A1. The step structure 21 further includes: a third step cluster 213, which is located on the side of the groove 11 away from the first step cluster 211, and the third step cluster 213 is in contact with the side wall of the wall 1. The third step cluster 213 includes multiple step groups, such as Figure 2A As shown, G12 to G18 are sequentially arranged along the second direction. Each step group includes a plurality of gate conductive patterns GM arranged in a stairway, and each gate conductive pattern GM is located in one gate conductive layer 101b among the plurality of gate conductive layers 101b.

[0134] In these embodiments, the first step cluster 211 and the third step cluster 213 are respectively disposed on opposite sides of the groove 111 along the second direction X. Figure 2C and Figure 2G As shown, the plurality of gate lines may further include a plurality of second gate lines WL_02 located in the second core area A2, the step area B may further include a third sub-area B3, the third sub-area B3 is located on the side of the groove 111 close to the second core area A2, and the third step cluster 213 is located in the third sub-area B3. Figure 2GAs shown, a gate conductive pattern GM included in the third step cluster 213 can contact a third conductive line DL3, which in turn contacts a second gate line WL_02. A gate conductive pattern GM included in the second step cluster 212 contacts a fourth conductive line DL4, which in turn contacts a second gate line WL_02. The third conductive line DL3 is the portion of a conductive line included in the wall 11 located in the third sub-area B3, and the fourth conductive line DL4 is the portion of a conductive line included in the wall 11 located in the second sub-area B2 and the third sub-area B3.

[0135] In these embodiments, similarly to the above-mentioned first step cluster 211 in which a gate conductive pattern GM is electrically connected to a first gate line WL_01 through a first conductive line DL1, and the second step cluster 212 in which a gate conductive pattern GM is electrically connected to a first gate line WL_01 through a second conductive line DL2, a gate conductive pattern GM is electrically connected to a second gate line WL_02 through a third conductive line DL3, and a gate conductive pattern GM is electrically connected to a second gate line WL_02 through a fourth conductive line DL4, thereby enabling signal transmission to multiple second gate lines WL_02, thereby enabling bilateral driving.

[0136] like Figure 2F As shown, taking the gate conductive pattern GM included in the third step cluster 213 belonging to the step group G17 and the gate conductive pattern GM included in the second step cluster 212 belonging to the step group G8 as an example, the gate conductive pattern GM included in the step group G17 is electrically connected to a second gate line WL_02 of the second core area A2 through a third conductive line DL3, and the gate conductive pattern GM included in the step group G8 is electrically connected to a second gate line WL_02 of the second core area A2 through a fourth conductive line DL4.

[0137] Among them, the gate conductive pattern GM, the third conductive line DL3 and the second gate line WL_02 connected to the gate conductive pattern GM included in the third step cluster 213 belong to the same gate conductive layer, and the gate conductive pattern GM, the fourth conductive line DL4 and the second gate line WL_02 connected to the gate conductive pattern GM included in the second step cluster 212 belong to the same gate conductive layer.

[0138] That is, in these embodiments, it can be applied to bilateral driving. On the other hand, in this structure, by utilizing the characteristics of the arrangement of the step structure 21, a groove 111 is provided in the middle of the wall 11 corresponding to the step structure 21. On the one hand, it will not affect the bilateral driving. That is, a first step cluster 211 located on the side of the groove 111 close to the first core area A1 is used to transmit a signal to the first gate line WL_01 located in the upper layer of the first core area A1, a third step cluster 213 located on the groove 111 close to the second core area A2 is used to transmit a signal to the second gate line WL_02 located in the upper layer of the second core area A2, and a second step cluster 212 located below the groove 111 is used to transmit signals to both the first gate line WL_01 and the second gate line WL_02 in the lower layer of the first core area A1 and the second core area A2. On the other hand, it can also play a role in decomposing the stress of the insulating material, thereby reducing problems such as poor filling.

[0139] In some embodiments, as Figure 2A As shown, among the multiple step groups included in the third step cluster 213 , the fifth step group, namely G12 , is closest to the groove 111 . At least part of the gate conductive pattern in the fifth step group is higher than the bottom 111 a of the groove 111 .

[0140] At least part of the gate conductive pattern GM in the fifth step group is higher than the bottom 111a of the groove 11, which means that part of the gate conductive pattern GM in the fifth step group is higher than the bottom 111a of the groove 111, or all of the gate conductive patterns GM in the fifth step group are higher than the bottom 111a of the groove 111. Here, when part of the gate conductive pattern GM in the fifth step group is higher than the bottom 111a of the groove 111, the lowermost gate conductive pattern GM in the fifth step group is flush with the bottom 111a of the groove 111, or at least the lowermost gate conductive pattern GM in the fifth step group is lower than the bottom 111a of the groove 111. When all of the gate conductive patterns GM in the fifth step group are higher than the bottom 111a of the groove 111, the lowermost gate conductive pattern GM in the fifth step group is higher than the bottom 111a of the groove 111.

[0141] In these embodiments, by making at least part of the gate conductive pattern GM in the fifth step group higher than the bottom 111a of the groove 111, the fifth step group can separate the remaining step groups in the third step cluster 213 from the second step cluster 212. Figure 2F As shown, the fifth step group separates the remaining step groups in the third step cluster 213 and the second step cluster 212 into two groove structures W2, as shown in FIG. Figure 1CAs shown, compared with a large groove structure W1 formed by the first step cluster 211 and the third step cluster 213, when the oxide filling material is filled on the first step cluster 211 and the third step cluster 213, the oxide filling material is filled in the two groove structures W2 respectively, so that the stress generated by the oxide filling material can be decomposed from one groove structure W1 to the two groove structures W2, thereby reducing the defects caused by stress and expansion.

[0142] At the same time, Figure 3A and Figure 3B As shown, the first step cluster 211, the second step cluster 212 and the third step cluster 213 form a large groove structure W1. In the case that at least part of the gate conductive pattern GM in the first step group and at least part of the gate conductive pattern GM in the fifth step group are higher than the bottom of the groove 111, the first step group and the fifth step group can separate the large groove structure W1 into three groove structures W2. In this way, when the oxide filling material is filled on the first step cluster 211, the second step cluster 212 and the third step cluster 213, the oxide filling material is filled in the three groove structures W2 respectively, so that the stress generated by the insulating material can be decomposed from one groove structure W1 to the three groove structures W2, thereby reducing the defects caused by stress and expansion.

[0143] In some embodiments, the uppermost gate conductive pattern GM in the fifth step group is located in the uppermost gate conductive layer 101 b among the plurality of gate conductive layers 101 b .

[0144] In these embodiments, the uppermost gate conductive pattern GM in the fifth step group may be flush with the upper surface of the wall 11 , that is, the fifth step group is at a higher horizontal position and may play a supporting role similar to that of the wall 11 .

[0145] In some embodiments, among the multiple step groups included in the third step cluster 213, the step group farthest from the groove 111 is the sixth step group, and at least part of the gate conductive pattern GM in the sixth step group is higher than the topmost gate conductive pattern GM contained in the step group adjacent to the sixth step group in the third step cluster 213.

[0146] At least part of the gate conductive patterns GM in the sixth step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to the sixth step group in the third step cluster 213. This means that, in the third step cluster 213, part of the gate conductive patterns GM in the sixth step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to it, or all of the gate conductive patterns GM in the sixth step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent to it. Here, when part of the gate conductive patterns GM in the sixth step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to it, the lowermost gate conductive pattern GM in the sixth step group is flush with the uppermost gate conductive pattern GM included in the step group adjacent to it, or at least the lowermost gate conductive pattern GM in the sixth step group is lower than the uppermost gate conductive pattern GM included in the step group adjacent to it. When all of the gate conductive patterns GM in the sixth step group are higher than the uppermost gate conductive pattern GM included in the step group adjacent to it, the lowermost gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM included in the step group adjacent to it.

[0147] In these embodiments, by making at least part of the gate conductive pattern GM in the sixth step group higher than the uppermost gate conductive pattern GM included in the step group adjacent to the sixth step group in the third step cluster 213, the sixth step group can be placed at a higher level, so that when the fifth step group is placed at a higher level, as shown in FIG. Figure 2F As shown, the multiple step groups in the third step cluster 213 have a trend of first decreasing and then increasing along the second direction X. Compared with the trend of the multiple step groups in the third step cluster 213 gradually increasing or decreasing along the second direction X, the stress generated by the filled oxide material can be decomposed into each step group, thereby avoiding poor filling caused by stress concentration.

[0148] In some embodiments, in the sixth step group, each gate conductive pattern GM in at least a portion of the gate conductive patterns GM and at least one gate conductive pattern GM in the fifth step group are located in the same gate conductive layer 101 b .

[0149] In the sixth step group, each gate conductive pattern GM of at least some of the gate conductive patterns GM and at least one gate conductive pattern GM in the fifth step group are located in the same gate conductive layer 101b, which means that in the sixth step group, each gate conductive pattern GM of some of the gate conductive patterns GM and one of the gate conductive patterns GM in the fifth step group are located in the same gate conductive layer 101b, or, in the sixth step group, each gate conductive pattern GM of all the gate conductive patterns GM and one of the gate conductive patterns GM in the fifth step group are located in the same gate conductive layer 101b.

[0150] like Figure 2A, each of the gate conductive patterns GM in the sixth step group and one of the gate conductive patterns GM in the fifth step group are located in the same gate conductive layer 101 b. Those skilled in the art will appreciate that this only illustrates the case where the fifth and sixth step groups have the same number of gate conductive patterns GM, and the uppermost gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM in the fifth step group (e.g., the uppermost gate conductive pattern GM in the sixth step group is flush with the uppermost gate conductive pattern GM in the fifth step group, or the height of the uppermost gate conductive pattern GM in the sixth step group is higher than the height of the uppermost gate conductive pattern GM in the fifth step group). In some embodiments, the number of gate conductive patterns GM in the fifth step group may be different from the number of gate conductive patterns GM in the second step group. In this case, the uppermost gate conductive pattern GM in the sixth step group is higher than the uppermost gate conductive pattern GM in the first step group, or the uppermost gate conductive pattern GM in the fifth step group is higher than the uppermost gate conductive pattern GM in the sixth step group. This is not specifically limited herein.

[0151] In some embodiments, the plurality of contacts further include a plurality of second contacts coupled to the third step cluster 213. Of two gate conductive patterns located in the same gate conductive layer 101 b and belonging to different step groups, one gate conductive pattern GM contacts at least one of the plurality of second contacts, while the other gate conductive pattern GM does not contact any of the plurality of second contacts.

[0152] like Figure 2A As shown, taking two gate conductive patterns GM located in the same gate conductive layer 101b and belonging to different step groups, which belong to the fifth step group and the sixth step group respectively, as an example, all the gate conductive patterns GM in the sixth step group and at least one gate conductive pattern GM in the fifth step group are located in the same gate conductive layer 101b, and all of the multiple contacts can be in contact with the sixth step group. In this case, the fifth step group serves as a virtual step group and plays a supporting role. Alternatively, some of the multiple contacts are in contact with the fifth step group, and the rest are in contact with the sixth step group. In this case, while the sixth step group plays a supporting role, some steps in the sixth step group also play an electrical connection role.

[0153] In other embodiments, two gate conductive patterns GM located in the same gate conductive layer 101b and belonging to different step groups are in contact with different second contacts, respectively. That is, the fifth step group plays a supporting role, and all steps in the fifth step group play an electrical connection role.

[0154] In some embodiments, as Figure 2AAs shown, each gate conductive pattern GM in the plurality of gate conductive patterns GM in the first step cluster 211 and at least one corresponding gate conductive pattern GM in the third step cluster 213 are included in the same gate conductive layer 101 b .

[0155] That is, each gate conductive pattern in the first step cluster 211 can find a gate conductive pattern of corresponding height in the third step cluster 213. This enables electrical extraction of the first gate line WL_01 and the second gate line WL_02 at the same level in the first core area A1 and the second core area A2.

[0156] In some embodiments, in the third step cluster 213 , the inclination directions of two adjacent step groups are opposite.

[0157] like Figure 2A As shown, in the third step cluster 213, the first step group (G12) arranged in sequence along the second direction X is inclined in the positive direction of the second direction X, the second step group (G13) arranged in sequence along the second direction X is inclined in the negative direction of the second direction X, and the third step group (G14) arranged in sequence along the second direction X is inclined in the positive direction of the second direction X.

[0158] In these embodiments, compared with the case where the inclination directions of two adjacent step groups are the same, when the inclination directions of two adjacent step groups are opposite, on the one hand, during the manufacturing process, the two adjacent step groups can be obtained by trimming and etching through the same mask pattern, which can reduce the amount of mask pattern used and the number of trimming and etching times. On the other hand, under this structure, the step groups in the final step structure 21 can be staggered with each other, making the step group distribution more dispersed, and the step structure 21 can be broken down into small pieces, decomposing the stress onto the step groups, thereby avoiding stress concentration and further improving the structural stability of the entire semiconductor structure.

[0159] In some embodiments, the fifth step group and the step groups adjacent to the fifth step group in the second step cluster 212 have opposite inclination directions.

[0160] The step group adjacent to the fifth step group in the second step cluster 212 is the last step group in the second step cluster 212 sequentially arranged along the second direction X, ie, G11.

[0161] In these embodiments, by making the inclination directions of the fifth step group and the step groups adjacent to the fifth step group in the second step cluster 212 opposite, the same technical effect as the opposite inclination directions of the two adjacent step groups in the same cluster is achieved, which will not be repeated here.

[0162] The first step cluster 211 and the third step cluster 213 may be symmetrical or asymmetrical in the second direction X, which is not specifically limited here. In the embodiment of the present disclosure, only the case where the first step cluster 211 and the third step cluster 213 are asymmetrical in the second direction X is shown.

[0163] Some embodiments of the present disclosure also provide a storage system. Figure 3A is a block diagram of a storage system according to some embodiments. Figure 3B FIG is a block diagram of a storage system according to some other embodiments. Figure 3A and Figure 3B The storage system 1 includes a three-dimensional memory 10 and a controller 20. The three-dimensional memory 10 can be any of the three-dimensional memory provided in the above embodiments. The controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0164] The storage system 1 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC) package). That is, the storage system 1 can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0165] In some embodiments, see Figure 3A The storage system 1 includes a controller 20 and a three-dimensional memory 10. The storage system 1 can be integrated into a memory card.

[0166] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0167] In other embodiments, see Figure 3BThe storage system 1 includes a controller 20 and a plurality of three-dimensional memories 10. The storage system 1 is integrated into a solid state drive (SSD).

[0168] In the storage system 1, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0169] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0170] In some embodiments, the controller 20 can be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 can also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 can also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 20 can also be configured to process error correction codes for data read from or written to the three-dimensional memory 10.

[0171] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10. For example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0172] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0173] Some embodiments of the present disclosure also provide a method for fabricating a semiconductor structure. This method can be used to fabricate the semiconductor structure provided in any of the above embodiments. Based on the above, the semiconductor structure fabricated using this method can include a first core region, a step region, and a second core region disposed sequentially. The description of the first core region, the step region, and the second core region of the semiconductor structure can be found in the description of the semiconductor structure above and will not be repeated here.

[0174] The method for preparing the semiconductor structure comprises:

[0175] S1) Figure 4A As shown, an initial stacked structure 101_1 is formed, and the initial stacked structure 101_1 includes a plurality of insulating layers and a plurality of sacrificial layers alternately stacked along a first direction.

[0176] For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition and other methods can be used to alternately deposit insulating layers and sacrificial layers on the substrate. One insulating layer and one sacrificial layer constitute one level. The initial stacked structure 101_1 can be 8 levels, 16 levels, 32 levels, 64 levels, 96 levels, 128 levels, 136 levels, 144 levels or even 300 levels.

[0177] The insulating layer may be made of silicon oxide, and the sacrificial layer may be made of silicon nitride.

[0178] With the exception of the sacrificial layer, which differs from the gate conductive layer described above in material, the remaining structures in the initial stacked structure 101_1 share the same characteristics, including position, material, and function, as their corresponding structures in the stacked structure. Therefore, unless otherwise specified, the remaining structures in the initial stacked structure 101_1 can be referred to above for the corresponding structures in the stacked structure 101 and will not be further described below. Specifically, unless otherwise specified, the structures in the initial stacked structure with the word "initial" in their names can be referred to above for the corresponding structures in the stacked structure.

[0179] Since the semiconductor structure to be formed has the first core region A1 , the step region B, and the second core region A2 , the initial stacked structure 101_1 also has the first core region A1 , the step region B, and the second core region A2 .

[0180] S2) Figure 4B As shown, the initial stacked structure 101_1 is divided into a first core area A1 and a step area B arranged along the second direction.

[0181] Specifically, a partitioning step 201 can be formed on the initial stacked structure 101_1. The partitioning step 201 can divide the initial stacked structure 101_1 into a first core area A1, a second core area A2, and a step area B. This description uses double-sided driving as an example. The partitioning step 201 can serve as a connection step for the top select gate of the memory cell string 102.

[0182] Partitioning steps 201 are formed on the initial stacked structure 101_1, specifically comprising: trimming and etching the top several composite layers of the initial stacked structure 101_1 along the second direction X to form two mutually symmetrical partitioning steps 201a and 201b. The initial stacked structure 101_1 is divided into a first core area A1, a step area B, and a second core area A2 arranged in sequence by the two partitioning steps 201a and 201b.

[0183] The number of levels corresponding to the trimming etching may be 2 to 3 layers, and the formed step region B is located between the first core region A1 and the second core region A2.

[0184] S3) Figure 4C As shown, an initial wall 11_1 and an initial step structure 21_1 are formed on the initial stacked structure 101_1 and located in step region B, arranged sequentially along a third direction Y. A groove 111 is provided on the upper surface of the initial wall 11_1, extending through at least two adjacent initial walls 11_1 along the third direction Y. The initial step structure 21_1 includes a first initial step cluster 211_1 and a second initial step cluster 212_1 arranged along a second direction X. Both the first and second initial step clusters 211_1, 212_1 contact the sidewalls of the wall 1, with the second initial step cluster 212 located below the groove 111. The first, second, and third directions Z, Y are perpendicular to each other. The first and second initial step clusters 211_1, 212_1 each include multiple initial step groups, each of which includes multiple sacrificial patterns arranged in a staircase pattern. Each sacrificial pattern is located in one of the multiple sacrificial layers.

[0185] like Figure 4C As shown, the first initial step cluster 211_1 may include 7 step groups, such as G1' to G7', and the second initial step cluster 212_1 may include 4 step groups, such as G8' to G11'.

[0186] Here, taking a storage block R as an example, the first step cluster 211 and the second step cluster 212 may belong to a step structure 21 included in the partitioned step structure. A step partition Bi is formed between two walls 1. The partitioned step structure may include M steps, each step including multiple sub-partitions in the third direction. The height difference between adjacent steps is the height of N steps, and the height difference between adjacent sub-partitions is the height of 1 step, where M is a natural number greater than or equal to 1, thereby forming a two-dimensional composite three-dimensional step structure.

[0187] On the initial stacked structure 101_1 and in the step area B, an initial wall 11_1 and an initial step structure 21_1 are sequentially arranged along the third direction Y, as shown in FIG. Figure 4D to Figure 4G Shown, including:

[0188] S31, such as Figure 4D As shown, the portion of the initial stacked structure 101_1 located in the step area B is divided into a wall area Bj and a step partition Bi along the third direction Y, wherein, as shown in FIG. Figure 4D As shown, the area shown by the dotted box is the step partition Bi, and the area between the two step partitions Bi is Bj.

[0189] S32 , protecting the portion of the initial stacked structure 101_1 located in the wall area Bj, and etching the portion of the initial stacked structure 101_1 located in the step partition Bi, to obtain the initial wall 11_1 located in the wall area Bj and the initial step structure 21_1 located in the step partition Bi.

[0190] In some embodiments, Figure 4E As shown, the step partition Bi may include a plurality of fourth sub-areas B4 and a plurality of fifth sub-areas B5 distributed in sequence along the second direction, each fourth sub-area B4 includes: a first protection area B4i1 and a first etching area B4i2 located on the side of the first protection area B4i1 away from the first core area A1, and each fifth sub-area B5 includes: a second protection area B5i1 and a second etching area B5i2 located on the side of the second protection area B5i1 close to the first core area A1.

[0191] Etching the portion of the initial stacked structure 101_1 located in the step partition Bi includes:

[0192] like Figure 4E and Figure 4FAs shown, the portions of the initial stacked structure 101_1 located in the first protection zone B4i1 and the second protection zone B5i1 are protected, while the portions of the initial stacked structure 101_1 located in the first etching zone B4i2 and the second etching zone B5i2 are trimmed and etched, resulting in a preliminary step structure 21_2. The preliminary step structure 21_2 includes a first preliminary step cluster 211_2 and a second preliminary step cluster 212_2 sequentially arranged along the second direction. The first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 each include multiple preliminary step groups, and the multiple preliminary step groups are located at the same level. Furthermore, for the multiple preliminary step groups, adjacent ones have opposite inclinations along the second direction.

[0193] It should be noted that, in this document, A and B being located at the same level may mean that, with a point in the semiconductor structure (e.g., the center of the semiconductor structure) as the origin and the direction from the substrate to the semiconductor structure or the source layer to the semiconductor structure as the positive Z-axis direction, the coordinates of the center of A and the center of B along the Z-axis direction are equal relative to the origin. Similarly, A being located at a higher level than B may mean that, with a point in the semiconductor structure (e.g., the center of the semiconductor structure) as the origin and the direction from the substrate to the semiconductor structure or the source layer to the semiconductor structure as the positive Z-axis direction, the coordinate of the center of A along the Z-axis direction is greater than the coordinate of the center of B along the Z-axis direction relative to the origin. A being located at a lower level than B may mean that, with a point in the semiconductor structure (e.g., the center of the semiconductor structure) as the origin and the direction from the substrate to the semiconductor structure or the source layer to the semiconductor structure as the positive Z-axis direction, the coordinate of the center of A along the Z-axis direction is less than the coordinate of the center of B along the Z-axis direction relative to the origin.

[0194] For multiple preliminary step groups, along the second direction, the inclination directions of two adjacent preliminary step groups are opposite, which means that among any two adjacent preliminary step groups, if the first step group (such as G1") arranged in sequence along the second direction is inclined in the negative direction of the second direction X, then the second step group (such as G2") arranged in sequence along the second direction is inclined in the positive direction of the second direction X; if the first step group (such as G2") arranged in sequence along the second direction is inclined in the positive direction of the second direction X, then the second step group (such as G3") arranged in sequence along the second direction is inclined in the negative direction of the second direction X.

[0195] In these embodiments, since the plurality of preliminary step groups are at the same level and the inclination directions of two adjacent preliminary step groups are opposite along the second direction, the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 meet the mirror symmetric distribution condition, that is, Figure 4F As shown, the multiple preliminary step groups have the same number of levels, and the multiple preliminary step groups are mirror-symmetrical.

[0196] Of course, if Figure 4F As shown, the preliminary step structure 21_2 may further include a third preliminary step cluster 213_2. In this case, the plurality of preliminary step groups may be respectively denoted as G1" to G18", and are mirror-symmetrical with each other.

[0197] In some embodiments, a mask pattern can be used to protect the portions of the initial stacked structure 101_1 located in the first protection zone B4i1 and the second protection zone B5i1, and under the protection of the mask pattern and multiple trimming, the portions of the initial stacked structure located in the first etching zone B4i2 and the second etching zone B5i2 can be etched.

[0198] Specifically, for example, using three mask patterns to protect the portion of the initial stacked structure 101_1 located in the first protection zone B4i1 and the second protection zone B5i1, and trimming and etching the portion of the initial stacked structure 101_1 located in the first etching zone B4i2 and the second etching zone B5i2, as shown in FIG. Figure 4G As shown, the first mask pattern M1 among the three mask patterns can be used to trim and etch the portion of the initial stacked structure 101_1 located in the first etching area B4i2 and the second etching area B5i2, trimming 4 times and etching 5 times to obtain a step structure with 5 steps. Then, the second mask pattern M2 can be used to trim and etch the portion of the initial stacked structure 101_1 located in the first etching area B4i2 and the second etching area B5i2, similarly trimming 4 times and etching 5 times to obtain 5 steps. Finally, the third mask pattern M3 can be used to trim and etch the portion of the initial stacked structure 101_1 located in the first etching area B4i2 and the second etching area B5i2, similarly trimming 4 times and etching 5 times to obtain 5 steps. In this way, each first etching area B4i2 and second etching area B5i2 obtains 15 steps.

[0199] The steps here have the same meaning as the steps above and will not be described again here.

[0200] In order to realize a structure in which each step includes multiple steps S along the third direction, in some embodiments, the step partition Bi can be divided into multiple sub-partitions along the third direction, and etching is performed so that each two adjacent sub-partitions differ by a composite layer (including an insulating layer and a sacrificial layer) to obtain a partitioned step structure having multiple steps along the third direction Y.

[0201] Taking the example of each step comprising two sub-regions in the third direction Y, each sub-region step structure can form two steps S in the third direction Y. In this case, each etching step descends by the height of two composite layers (i.e., comprising two insulating layers and two sacrificial layers). In other words, the height of one step is equal to the height of two composite layers. In this case, taking the example of each first etched area B4i2 and second etched area B5i2 each obtaining 15 steps, a preliminary step group can include 30 levels of steps.

[0202] like Figure 4H As shown, in the above-mentioned trimming and etching process, after each etching is completed, the portion of each step group in the middle covered by the first mask pattern M1, the second mask pattern M2 and the third mask pattern M3 is trimmed on both sides of the second direction X, and the portion of the step groups G1" and G18" on both sides covered by the first mask pattern M1, the second mask pattern M2 and the third mask pattern M3 is trimmed on a single side along the second direction X, thereby finally obtaining a plurality of preliminary step groups that are mirror-symmetrical.

[0203] It should be noted that, in Figure 4G , the situation where the sizes of the first mask pattern M1, the second mask pattern M2, and the third mask pattern M3 along the second direction X change from small to large is shown. Those skilled in the art will understand that the sizes of the first mask pattern M1, the second mask pattern M2, and the third mask pattern M3 along the second direction X can also change from large to small, and the same multiple preliminary step groups can also be obtained.

[0204] S33 , performing a preset etching on at least all preliminary step groups included in the second preliminary step cluster 212_2 , so that all preliminary step groups included in the second preliminary step cluster 212_2 are lowered to the same level, thereby obtaining a first preliminary step cluster 211_1 and a second preliminary step cluster 212_1 .

[0205] For example, all preliminary step groups included in the second preliminary step cluster 212_2 can be made to descend 30 levels. At this time, all preliminary step groups included in the first preliminary step cluster 211_2 are located 30 levels above the initial stacking structure 101_1, and all preliminary step groups included in the second preliminary step cluster 212_2 are located 30 levels below the initial stacking structure 101_1, together forming a 60-level step structure, which can realize signal transmission to 60-level gate lines.

[0206] In some embodiments, the preparation method further includes: before etching all the preliminary step groups included in the second preliminary step cluster 212_2, performing multiple preset etchings on the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2, so that the multiple preliminary step groups included in the first preliminary step cluster 211_2 are located at different levels, and the multiple preliminary step groups included in the second preliminary step cluster 212_2 are located at different levels.

[0207] Different levels have the opposite meanings to the same levels mentioned above. For details, please refer to the above description and will not be repeated here. All levels that do not meet the meaning of the same level belong to different levels. That is, in these embodiments, by making the multiple preliminary step groups included in the first preliminary step cluster 211_2 at different levels and the multiple preliminary step groups included in the second preliminary step cluster 212_2 at different levels, the steps included in each preliminary step group can be used for electrical lead-out of the gate line as much as possible, and the production of one hundred or even several hundred levels of steps can be achieved.

[0208] like Figure 4I As shown, six of the seven preliminary step groups included in the first preliminary step cluster 211_2 are located at different levels, and four preliminary step groups included in the second preliminary step cluster 212_2 are located at different levels.

[0209] Taking the example of each preliminary step group including 30 levels of steps, the first preliminary step cluster 211_2 has 180 levels of steps, and the second preliminary step cluster 212_2 has 120 levels of steps. After all the preliminary step groups contained in the second preliminary step cluster 212_2 are etched so that all the preliminary step groups contained in the second preliminary step cluster 212_2 are lowered by 150 levels, the first initial step cluster 211_2 finally obtained is located 180 levels above the initial stacked structure, and all the preliminary step groups contained in the second preliminary step cluster 212_2 are located 120 levels below the initial stacked structure, together forming a step structure of 300 levels, which can realize signal transmission to the gate lines of 300 levels.

[0210] In some embodiments, the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2 are subjected to a plurality of predetermined etching steps, including:

[0211] Multiple sets of mask plates M are used to perform multiple preset etchings on the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2. In any two preset etchings, for the first preliminary step cluster 211_2 and / or the second preliminary step cluster 212_2, the edges of the openings of the mask plate M used in one etching do not overlap with the edges of the openings of the mask plate M used in the other etching in the second direction.

[0212] Here, taking the example that the number of preliminary step groups included in the first preliminary step cluster 211_2 is 7, which are sequentially labeled as G1", G2", G3", G4", G5", G6", and G7" along the second direction X, the number of preliminary step groups included in the second preliminary step cluster 212_2 is 4, which are sequentially labeled as G8", G9", G10", and G11" along the second direction, and the preliminary step groups included in the first preliminary step cluster 211_2 except G1" and G7" are all lowered to different levels (that is, the 6 preliminary step groups are located at different levels), and the preliminary step groups included in the second preliminary step cluster 212_2 are also lowered to different levels (that is, the 4 preliminary step groups are all located at different levels), multiple preset etchings are performed on the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2, including:

[0213] Four sets of masks M are used to perform four preset etchings on the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2.

[0214] Here, description is given by taking an example where the preliminary step structure 21_2 includes a first preliminary step cluster 211_2 , a second preliminary step cluster 212_2 , and a second preliminary step cluster 213_2 .

[0215] like Figure 4J As shown, in the first preset etching, the opening of the mask plate M used exposes G3"~G4", G8"~G9", G15"~G16", and accordingly, the positions of the edges of the opening of the mask plate M in the second direction are respectively located on the left side of G3", the right side of G4", the left side of G8", the right side of G9", the left side of G15" and the right side of G16".

[0216] like Figure 4K As shown, in the second preset etching, the openings of the mask plate M used expose G2"~G5", G8"~G10", G14"~G17", and the edges of the openings of the mask plate M in the second direction X are respectively located on the left side of G2", the right side of G5", the left side of G8", the right side of G9", the left side of G15" and the right side of G16".

[0217] like Figure 4L As shown, in the third preset etching, the openings of the mask plate M used expose G4"~G6", G9"~G11", G13"~G15", and the edges of the openings of the mask plate in the second direction X are respectively located on the left side of G4", the right side of G5", the left side of G9", the right side of G11", the left side of G13" and the right side of G15".

[0218] like Figure 4MAs shown, in the fourth preset etching, the opening of the mask plate M used exposes G8″ to G11″, and the edges of the opening of the mask plate in the second direction are respectively located on the left side of G8″ and the right side of G11″.

[0219] Thus, it can be seen that, during the predetermined etching process, for the preliminary step groups included in the first preliminary step cluster 211, the edges of the openings of the mask M used in any two predetermined etchings do not overlap in the second direction X. This can, on the one hand, prevent the edges of the openings of the mask M from being easily etched poorly when etching multiple times at the same location as the depth of the preliminary step groups decreases. On the other hand, different preliminary step groups can be made to descend to different depths, thereby achieving electrical extraction of all subsequent gate lines.

[0220] It should be noted that, for the first preliminary step cluster 211_2 and the second preliminary step cluster 212_2, only the situation is shown here that for the first preliminary step cluster 211_2, in any two preset etchings, the edge of the opening of the mask plate M used in one etching and the edge of the opening of the mask plate M used in the other etching do not overlap in the second direction. Those skilled in the art can understand that, for the second preliminary step cluster 212_2, it is also possible to select a different position of the opening of the mask plate M in each preset etching to achieve that in any two preset etchings, the edge of the opening of the mask plate M used in one etching and the edge of the opening of the mask plate M used in the other etching do not overlap in the second direction. This can also avoid the defect of poor etching that is easily caused by the increasing depth of the preliminary step group.

[0221] In these embodiments, by pre-etching G2" to G6" included in the first preliminary step cluster and pre-etching G13" to G17" included in the third preliminary step cluster 213_2 without pre-etching G7" and G12", G7" and G12" can form two support pillars on both sides of the groove 111 to facilitate supporting. At the same time, the two support pillars can also separate the first step cluster 211, the second step cluster 212 and the third step cluster 213 into three groove structures to facilitate stress decomposition when subsequently filling the insulating material.

[0222] Here, in order to conveniently illustrate the comparison between the overlapping and non-overlapping situations of the edges of the openings of the mask plate M during multiple preset etchings, the embodiment of the present disclosure is illustrated by taking the initial step structure including the first initial step cluster 211_1, the second initial step cluster 212_1 and the third initial step cluster 213_1 as an example. Those skilled in the art will understand that if the initial step structure 21_1 only includes the first initial step cluster 211_1 and the second initial step cluster 212_1, during multiple preset etchings, the overlapping situation of the edges of the openings of the above-mentioned mask plate M can also be referred to. Of course, the edges of the openings of the mask plate M used for each etching can also be adjusted according to the actual structure to be produced.

[0223] S34 , etching the initial wall 11_1 to form the groove 111 on the upper surface of the initial wall 11_1 .

[0224] This step may occur after the above-mentioned S33, or may be performed simultaneously with the preset etching of all preliminary step groups included in the second preliminary step cluster 212_2, so as to obtain the following: Figure 4M The structure shown.

[0225] Here, taking the example of the first preset etching in which G3"-G4", G8"-G9", and G15"-G16" are all lowered by 30 levels, the second preset etching in which G2"-G5", G8"-G10", and G14"-G17" are all lowered by 30 levels, the third preset etching in which G4"-G6", G9"-G11", and G13"-G15" are all lowered by 90 levels, and the fourth preset etching in which G8"-G11" are lowered by 150 levels, after S33, when etching the initial wall 11_1, the initial wall 11_1 can be lowered by at least 150 levels. When S33 is performed synchronously with the preset etching of all preliminary step groups included in the second preliminary step cluster 212_2, the initial wall 11_1 and G8"-G11" can be simultaneously lowered by 150 levels. That is, in the fourth preset etching, the initial wall 11_1 is synchronously etched. At this time, the opening of the mask M still exposes the region corresponding to G8″ to G11″ of the initial wall 11_1.

[0226] S4 . Fill the groove 111 with insulating material to form an insulating portion embedded in the groove 111 . The insulating portion is embedded in the groove 111 and contacts the sidewall of the groove 111 .

[0227] The insulating material may be an oxide material. When filling, the step structure may be filled with the insulating material first. At this time, due to the provision of the groove 111, the aspect ratio when filling the step structure 21 is reduced, thereby reducing stress and avoiding poor filling of the insulating portion at the step structure 21.

[0228] S5. Replace the sacrificial layer in the initial stacked structure 101_1 with the gate conductive layer 101 b to obtain a stacked structure 101 including a plurality of insulating layers and a plurality of gate conductive layers 101 b.

[0229] At this point, the wall 11 and the step structure 21 are formed. The wall 11 includes multiple conductive lines. The step structure 21 includes a first step cluster 211, a second step cluster 212, and a third step cluster 213 arranged sequentially along the second direction. The second step cluster 212 is further away from the first core area A1 than the first step cluster 211. The first, second, and third step clusters 211, 212, 213 all contact the sidewalls of the wall 11, and the second step cluster 212 is located below the groove 111. The first and second step clusters 211, 212 each include multiple step groups. Each step group includes multiple gate conductive patterns GM arranged in a staircase. Each gate conductive pattern GM is located in one of the multiple gate conductive layers 101b.

[0230] Replacing the sacrificial layer in the initial stacked structure 101 with the gate conductive layer 101b may include removing the sacrificial layer in the stacked structure 101 and forming the gate conductive layer 101b in the original location of the sacrificial layer. The sacrificial layer may be removed by, for example, a wet etching process; and the sacrificial layer may be made of, for example, silicon nitride or polysilicon.

[0231] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: Layer structure, wherein the stacked structure includes a plurality of insulating layers and a plurality of gate conductive layers alternately stacked along a first direction; The stacked structure comprises a first core region and a step region arranged along a second direction; in the step region, the stacked structure is divided into a wall and a step structure arranged along a third direction; a groove is provided on the upper surface of the wall and passes through at least two adjacent walls along the third direction; the step structure comprises a first step cluster and a second step cluster arranged along the second direction, the second step cluster being farther away from the first core region than the first step cluster, the first step cluster and the second step cluster both being in contact with a side wall of the wall, and the second step cluster being located below the groove; an insulating portion, the insulating portion being embedded in the groove and in contact with a sidewall of the groove; Among them, the first step cluster and the second step cluster respectively include multiple step groups, each step group includes multiple gate conductive patterns arranged in a staircase, and each gate conductive pattern is located in one of the multiple gate conductive layers; the first direction, the second direction and the third direction are perpendicular to each other.

2. The semiconductor structure according to claim 1, wherein: Among the multiple step groups included in the first step cluster, the step group closest to the groove is the first step group, and at least part of the gate conductive pattern in the first step group is higher than the bottom of the groove.

3. The semiconductor structure according to claim 2, wherein: The uppermost gate conductive pattern in the first step group is located in the uppermost gate conductive layer among the plurality of gate conductive layers.

4. The semiconductor structure according to claim 2, wherein: The inclination directions of step groups adjacent to the first step group in the first step group and the second step cluster are opposite.

5. The semiconductor structure according to claim 1, wherein: Among the multiple step groups included in the first step cluster, the step group farthest from the groove is the second step group, and at least part of the gate conductive pattern included in the second step group is higher than the topmost gate conductive pattern included in the step group adjacent to the second step group in the first step cluster.

6. The semiconductor structure according to claim 5, wherein: In the second step group, each gate conductive pattern in at least part of the gate conductive patterns is located in the same gate conductive layer as at least one gate conductive pattern in the first step group, and the first step group is the step group closest to the groove among the multiple step groups included in the first step cluster.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a plurality of first gate lines located in the first core region; The step area includes a first sub-area and a second sub-area sequentially arranged along the second direction, the first sub-area is located on a side of the groove close to the first core area, and the groove is located in the second sub-area; The wall includes a plurality of conductive wires; The first step cluster is located in the first sub-region, and a gate conductive pattern included in the first step cluster is in contact with a first conductive line, and the first conductive line is in contact with a first gate line; the second step cluster is located in the second sub-region, and a gate conductive pattern included in the second step cluster is in contact with a second conductive line, and the second conductive line is in contact with a first gate line; The first conductive line is a portion of a conductive line included in the wall located in the first sub-area, and the second conductive line is a portion of a conductive line included in the wall located in the first sub-area and the second sub-area.

8. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a plurality of contacts electrically connected to the first step cluster; Among the two gate conductive patterns located in the same gate conductive layer and belonging to different step groups, one gate conductive pattern contacts at least one of the plurality of contacts, and the other gate conductive pattern contacts none of the plurality of contacts.

9. The semiconductor structure according to claim 1, wherein: Among the multiple step groups included in the first step cluster, the step group at the lowest position is the third step group; The second step cluster includes a plurality of step groups, and a step group at the highest position is a fourth step group; The lowermost gate conductive pattern in the third step group and the uppermost gate conductive pattern in the fourth step group are respectively located in two adjacent gate conductive layers among the plurality of gate conductive layers.

10. The semiconductor structure according to claim 1, wherein: Among the multiple step groups included in the same step cluster, the inclination directions of two adjacent step groups are opposite.

11. The semiconductor structure according to any one of claims 1 to 10, characterized in that: The stacked structure further includes: a second core region, the second core region being located on a side of the step region away from the first core region; The step structure further includes: a third step cluster, the third step cluster being located on a side of the groove away from the first step cluster, and the third step cluster being in contact with a side wall of the wall; The third step cluster includes a plurality of step groups, each step group includes a plurality of gate conductive patterns arranged in a stairway, and each gate conductive pattern is located in a gate conductive layer among the plurality of gate conductive layers.

12. The semiconductor structure according to claim 11, wherein: The semiconductor structure further includes a plurality of second gate lines located in the second core region; The step region further includes a third sub-region, and the third sub-region is located on a side of the groove away from the first core region; The third step cluster is located in the third sub-region, and a gate conductive pattern included in the third step cluster contacts a third conductive line, the third conductive line contacts a second gate line, and a gate conductive pattern included in the second step cluster contacts a fourth conductive line, the fourth conductive line contacts a second gate line; Among them, the third conductive line is a conductive line contained in the wall and is located in the third sub-area. The fourth conductive line is a conductive line contained in the wall and is located in the second sub-area and the third sub-area. The step area includes a first sub-area and a second sub-area arranged in sequence along the second direction. The first sub-area is located on the side of the groove close to the first core area, and the groove is located in the second sub-area.

13. The semiconductor structure according to claim 11, wherein: Each gate conductive pattern in the plurality of gate conductive patterns in the first step cluster and at least one corresponding gate conductive pattern in the third step cluster are included in the same gate conductive layer.

14. A three-dimensional memory, characterized in that: include: The semiconductor structure according to any one of claims 1 to 13.

15. A storage system, characterized in that: The device comprises a controller and the three-dimensional memory according to claim 14 , wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

16. A method for preparing a semiconductor structure, characterized in that: include: forming an initial stacked structure comprising a plurality of insulating layers and a plurality of sacrificial layers alternately stacked along a first direction; dividing the initial stacked structure into a first core region and a step region arranged along a second direction; Initial walls and an initial step structure are formed on the initial stacked structure and located in the step area, arranged in sequence along a third direction; a groove is formed on the upper surface of the initial wall and penetrates at least two adjacent initial walls along the third direction; the initial step structure includes a first initial step cluster and a second initial step cluster arranged along a second direction, the first initial step cluster and the second initial step cluster both contact the sidewalls of the initial wall, and the second initial step cluster is located below the groove; wherein the first direction, the second direction, and the third direction are perpendicular to each other; the first initial step cluster and the second initial step cluster each include a plurality of initial step groups, each initial step group includes a plurality of sacrificial patterns arranged in a staircase manner, and each sacrificial pattern is located in one of the plurality of sacrificial layers; Filling the groove with an insulating material to form an insulating portion, wherein the insulating portion is embedded in the groove and contacts a sidewall of the groove; The sacrificial layer in the initial stacked structure is replaced with a gate conductive layer to obtain a stacked structure including a plurality of insulating layers and a plurality of gate conductive layers.

17. The method for preparing a semiconductor structure according to claim 16, wherein: The initial wall and the initial step structure arranged in sequence along the third direction are formed on the initial stacked structure and located in the step area, comprising: Dividing the portion of the initial stacked structure located in the step area into a wall area and a step area along a third direction; Protecting the portion of the initial stacked structure located in the wall area, and etching the portion of the initial stacked structure located in the step partition to obtain the initial wall located in the wall area and the initial step structure located in the step partition; The initial wall is etched to form the groove on the upper surface of the initial wall.

18. The method for preparing a semiconductor structure according to claim 17, wherein: The step partition includes a plurality of third sub-regions and a plurality of fourth sub-regions sequentially distributed along the second direction, each third sub-region includes: a first protection zone and a first etching zone located on a side of the first protection zone away from the first core zone, and each fourth sub-region includes: a second protection zone and a second etching zone located on a side of the second protection zone close to the first core zone; The etching of the portion of the initial stacked structure located in the step partition comprises: Protecting portions of the initial stacked structure located in the first protection zone and the second protection zone, and trimming and etching portions of the initial stacked structure located in the first etching zone and the second etching zone to obtain a preliminary step structure, wherein the preliminary step structure includes a first preliminary step cluster and a second preliminary step cluster sequentially arranged along a second direction, wherein the first preliminary step cluster and the second preliminary step cluster each include a plurality of preliminary step groups, and the plurality of preliminary step groups are located at the same level; and for the plurality of preliminary step groups, along the second direction, two adjacent preliminary step groups have opposite inclination directions; At least all initial step groups included in the second preliminary step cluster are subjected to a preset etching process, so that all initial step groups included in the second preliminary step cluster are lowered to the same level, thereby obtaining the first initial step cluster and the second initial step cluster.

19. The method for preparing a semiconductor structure according to claim 18, wherein: The initial wall is etched, and all the original step groups included in the second initial step cluster are etched in a preset manner simultaneously.

20. The method for preparing a semiconductor structure according to claim 18, wherein: Also includes: Before etching all the initial step groups included in the second preliminary step cluster, the first preliminary step cluster and the second preliminary step cluster are subjected to multiple preset etchings, so that the multiple preliminary step groups included in the first preliminary step cluster are located at different levels and the multiple preliminary step groups included in the second preliminary step cluster are located at different levels.

21. The method for preparing a semiconductor structure according to claim 20, wherein: The performing a plurality of preset etchings on the first preliminary step cluster and the second preliminary step cluster includes: Multiple sets of mask plates are used to perform multiple preset etchings on the first preliminary step cluster and the second preliminary step cluster. In any two preset etchings, for the first preliminary step cluster and / or the second preliminary step cluster, the edges of the openings of the mask plate used for one etching do not overlap with the edges of the openings of the mask plate used for the other etching in the second direction.

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