Digital microfluidic chip

Abstract

The present invention provides a digital microfluidic chip, comprising an active matrix thin-film transistor array substrate, a discrete hydrophobic film, an upper cover plate, a hydrophobic film deposited on the bottom of the upper cover plate, and droplets and silicone oil injected between the discrete hydrophobic film and the hydrophobic film. The active matrix thin-film transistor array substrate includes a plurality of high-voltage thin-film transistors, each of which includes a first TFT and a second TFT connected in series, and a source-drain connection electrode connecting the first and second TFTs in series. The digital microfluidic chip of the present invention utilizes high-voltage thin-film transistors that can provide voltages exceeding 200V, thereby improving the versatility of the digital microfluidic chip. The high-voltage thin-film transistors can also be applied with AC signals, thereby increasing the service life of the digital microfluidic chip.

Description

Technical Field

[0001] The present invention relates to the technical field of digital microfluidics, and in particular to a digital microfluidics chip. Background Art

[0002] The digital microfluidics (DMF) chip of electrowetting on dielectric (EWOD) is referred to as EWODDMF chip. The working principle of the EWOD DMF chip is to manipulate droplets by applying appropriate voltage to the electrodes to change the interfacial tension between the droplets and the electrodes (coated with a dielectric layer and a hydrophobic layer).

[0003] The main methods for applying voltage to electrodes include PCB, COMS, and active matrix thin-film transistor (AM-TFT) array substrates. Compared to PCB and COMS technologies, AM-TFT array substrates have fewer electrode connections, higher density and higher resolution arrays, and smaller overall device size. In addition, AM-TFT array substrates have enhanced functionality (sensing the position and size of droplets, heating individual droplets), agility, and programmability. Therefore, integrating AM-TFT array substrates with EWOD DMF chips is a very promising technology and has the greatest commercial value. Although AM-TFT addressing provides excellent functionality and configurability, its operating voltage is often between 0 and 60V, which is very difficult for droplets that require high-voltage drive and is not universal.

[0004] Currently, the main methods for increasing the operating voltage of TFTs include increasing the channel length, increasing the thickness of the dielectric layer, lightly doping the source and drain electrodes, and biasing the drain electrode. However, all four of these methods have drawbacks. For example, increasing the channel length reduces the TFT's electrical mobility, on-current, and current-switching ratio; increasing the thickness of the dielectric layer weakens the gate's control capability and increases TFT manufacturing costs; lightly doping the source and drain electrodes affects the TFT's stability and reliability; and biasing the drain electrode increases the TFT's on-resistance and reduces its on-current. Therefore, developing high-performance, high-voltage AM-TFT arrays and integrating them with EWOD DMF chips is a pressing issue. Summary of the Invention

[0005] The object of the present invention is to provide a digital microfluidic chip with improved versatility and service life.

[0006] The present invention provides a digital microfluidic chip, which includes an active matrix thin film transistor array substrate, a discrete hydrophobic film located on the active matrix thin film transistor array substrate, an upper cover plate, a hydrophobic film deposited on the bottom of the upper cover plate, and droplets and silicone oil injected between the discrete hydrophobic film and the hydrophobic film;

[0007] The active matrix thin film transistor array substrate includes a plurality of high-voltage thin film transistors, each of which controls one droplet, and includes a first TFT and a second TFT connected in series, and a source-drain connection electrode connecting the first TFT and the second TFT in series;

[0008] The first TFT and the second TFT each include a gate, a channel region located above the gate, channel contact electrodes respectively contacting both sides of the channel region, a source electrode connected to the channel contact electrode located on one side of the channel region, and a drain electrode connected to the channel contact electrode located on the other side of the channel region; the drain electrode of the first TFT is connected to the source electrode of the second TFT.

[0009] The end of the source electrode has a protrusion extending toward the center of the corresponding channel region, and the protrusion is the excess area after the source electrode and the channel contact electrode located below the source electrode overlap in space; the end of the drain electrode also has a protrusion extending toward the center of the corresponding channel region, and the protrusion is the excess area after the drain electrode and the channel contact electrode located below the drain electrode overlap in space.

[0010] Further, the length of the first protrusion of the source of the first TFT is equal to the length of the second protrusion of the drain of the second TFT, and the length of the second protrusion of the drain of the first TFT is equal to the length of the first protrusion of the source of the first TFT.

[0011] Furthermore, the plurality of high-voltage thin film transistors further include a source-drain connection electrode electrically connected to the drain of the first TFT and the source of the second TFT.

[0012] Furthermore, the multiple high-voltage thin-film transistors also include a contact hole connected to each channel contact electrode and a third contact hole connecting adjacent channel contact electrodes; the source and drain are both connected to the corresponding channel contact electrodes through the corresponding contact holes, and the source-drain connection electrode is connected to the drain of the first TFT and the source of the second TFT through the third contact hole.

[0013] Furthermore, multiple high-voltage thin-film transistors also include a gate dielectric layer, a first oxide insulating layer and a second oxide insulating layer; the gate dielectric layer covers the gate, and the channel region is located on the gate dielectric layer; the first oxide insulating layer covers the channel contact electrode and the channel region; the second oxide insulating layer covers the source and drain, the source-drain connecting electrode and the first oxide insulating layer.

[0014] Furthermore, the active matrix thin film transistor array substrate also includes a planar layer covering multiple high-voltage thin film transistors, a shielding electrode located on the planar layer and on the gate of the thin film transistor, an insulating layer located on the shielding electrode and the planar layer, and a driving electrode located on the insulating layer and passing through the insulating layer to contact the drain of the thin film transistor.

[0015] Furthermore, the discrete hydrophobic film and the active matrix thin film transistor array substrate are discrete and manufactured separately.

[0016] Furthermore, the discrete hydrophobic film includes a dielectric layer film and a hydrophobic layer film located on the dielectric layer film.

[0017] Furthermore, the dielectric layer film includes an insulating polymer compound or a composite layer of a polymer and an oxide.

[0018] Furthermore, the thickness of the dielectric layer film is 500 nanometers to 20 micrometers.

[0019] The digital microfluidic chip of the present invention uses high-voltage thin-film transistors, which can provide a voltage of more than 200V, which is beneficial to improving the versatility of the digital microfluidic chip; the high-voltage thin-film transistors can achieve a higher on-current and can apply AC signals, thereby increasing the service life of the digital microfluidic chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 Schematic diagram of the structure of a digital microfluidic chip according to an embodiment of the present invention;

[0022] Figure 2 yes Figure 1 Schematic diagram of the structure of the high-voltage thin-film transistor of the digital microfluidic chip shown;

[0023] Figure 3 yes Figure 1 A circuit diagram of a high-voltage thin-film transistor is shown;

[0024] Figure 4 yes Figure 1 Schematic diagram of the structure of the discrete hydrophobic membrane of the digital microfluidic chip shown. DETAILED DESCRIPTION

[0025] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0026] In the description of the present invention, it should be understood that the terms "length," "width," "up," "down," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," "outside," and the like, indicating positions or location relationships, are based on the positions or location relationships shown in the accompanying drawings and are intended only to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present invention. Furthermore, in the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

[0027] The present invention provides a method for manufacturing a digital microfluidic chip, as follows: Figure 1 As shown, the following steps are included:

[0028] S1: Depositing a first metal layer on a glass substrate 10, and patterning the first metal layer to form a first gate 21 and a second gate 22 spaced apart from each other, wherein the first metal layer can be made of a transparent conductive material, such as ITO and FTO; the first metal layer can also be made of a metal material, such as Mo, Cr, Au, Ti, Al, Ag, Cu, etc.;

[0029] S2: forming a gate dielectric layer 20 covering the first metal layer, wherein the material of the gate dielectric layer 20 is SiO2, SiN x , Al2O3, HfO2, ZrO2, etc.;

[0030] S3: forming a first channel region 31 and a second channel region 32 on the gate dielectric layer 20 , respectively, above the first gate 21 and the second gate 22 , wherein the material of the first channel region 31 and the second channel region 32 may be amorphous silicon, polycrystalline silicon or amorphous metal oxide (such as IGZO, ZnO, ITZO);

[0031] S4: depositing a second metal layer, and patterning the second metal layer to form a first channel contact electrode 41 and a second channel contact electrode 42, which are respectively located on both sides of the first channel region 31 and the second channel region 32 and contact the first channel region 30 and the second channel region 32, respectively. The second metal layer can be made of a transparent conductive material, such as ITO and FTO; the second metal layer can also be made of a metal material, such as Mo, Cr, Au, Ti, Al, Ag, Cu, etc.;

[0032] S5: forming a first oxide insulating layer 51 covering the second metal layer, the first channel region 31 and the second channel region 32, and etching the first oxide insulating layer 51 to form a first contact hole 511 connected to the first channel contact electrode 41, a second contact hole 512 connected to the second channel contact electrode 42, and a third contact hole 513 connecting the adjacent first channel contact electrode 41 and the second channel contact electrode 42;

[0033] S6: depositing a third metal layer, and patterning the third metal layer to form a first source 43 and a first drain 44 connected to the first contact hole 511 and located on both sides of the first channel region 31, respectively; a second source 45 and a second drain 46 connected to the second contact hole 512 and located on both sides of the second channel region 32, respectively; and a source-drain connection electrode 47 connected to the third contact hole 513, wherein the source-drain connection electrode 47 connects the first drain 44 and the second source 45; the third metal layer can be made of a transparent conductive material, such as ITO and FTO, or a metal material, such as Mo, Cr, Au, Ti, Al, Ag, Cu, etc.;

[0034] S7: forming a second oxide insulating layer 52 covering the third metal layer and the first oxide insulating layer 51. The materials of the first oxide insulating layer 51 and the second oxide insulating layer 52 are SiO2, SiN x , Al2O3, HfO2, ZrO2;

[0035] S8: forming a planarization layer 60 covering the second oxide insulating layer 52;

[0036] S9: forming a shielding electrode 70 on the planar layer 60 and on the gate 21;

[0037] S10: forming an insulating layer 80 covering the shielding electrode 70 and the planar layer 60 , and opening an opening (not shown) located on the second source electrode 45 in the insulating layer 80 ;

[0038] S11: forming a driving electrode 90 located in the opening and contacting the second source electrode 45;

[0039] S12: forming a discrete hydrophobic film 101 on the driving electrode 90 (specifically, the discrete hydrophobic film 101 is deposited on the surface of the driving electrode 90 by spin coating), thereby forming an AM-TFT array substrate having the discrete hydrophobic film 101 on the surface;

[0040] S13: Depositing a hydrophobic film 104 on the bottom of the upper cover plate 200 and opening a hole (not shown) through the hydrophobic film 104 on the upper cover plate 200;

[0041] S14: The upper cover plate 200 with the hydrophobic film 104 on the bottom and the AM-TFT array substrate with the discrete hydrophobic film 101 on the surface are formed into a box;

[0042] S14: The liquid drop 102 and the silicone oil 103 are injected between the discrete hydrophobic film 101 and the hydrophobic film 104 from the opening of the upper cover plate 200 , and the liquid drop 102 and the silicone oil 103 are located between the driving electrode 90 and the upper cover plate 200 .

[0043] The upper cover plate 200 is made of ITO glass. The liquid drop 102 is surrounded by silicone oil 103. The liquid drop 102 and the silicone oil 103 are incompatible and exist independently.

[0044] The digital microfluidic chip is formed through the above steps.

[0045] The digital microfluidic chip includes an integrated AM-TFT array substrate (active matrix thin film transistor array substrate), a discrete hydrophobic film 101 located on the AM-TFT array substrate, an upper cover plate 200, a hydrophobic film 104 located at the bottom of the upper cover plate 200, and droplets 102 and silicone oil 103 located between the discrete hydrophobic film 101 and the hydrophobic film 104.

[0046] When the upper cover plate 200 and the AM-TFT array substrate are assembled into a box, pillars (not shown) are placed at the four corners to secure them. Silicone (not shown) is then used to seal the upper cover plate 200 and the AM-TFT array substrate. The pillars are square or round in shape and range in height from 50 to 500 microns.

[0047] The digital microfluidic chip of the present invention manufactures a high-performance, ultra-high-throughput, universal sample processing instrument, providing a powerful experimental platform for biomedical research and applications such as genomics, proteomics, and precision medicine.

[0048] The AM-TFT array substrate includes a plurality of high-voltage thin-film transistors arranged in an array, a planar layer 60 covering the plurality of high-voltage thin-film transistors, a shielding electrode 70 located on the planar layer 60 and on the gate electrode 21 of the thin-film transistor, an insulating layer 80 located on the shielding electrode 70 and the planar layer 60, and a driving electrode 90 located on the insulating layer 80 and passing through the insulating layer 80 to contact the second drain electrode 46 of the thin-film transistor.

[0049] The AM-TFT array is used for voltage driving of the digital microfluidic chip, and the discrete hydrophobic film 101 serves as the dielectric layer film and the hydrophobic film of the digital microfluidic chip.

[0050] like Figure 2 As shown, each high-voltage thin film transistor includes a first TFT and a second TFT connected in series, and a source-drain connection electrode 47 electrically connecting the first TFT and the second TFT.

[0051] The first TFT includes a first gate 21, a first channel region 31 located above the first gate 21, a first channel contact electrode 41 contacting both sides of the first channel region 31, a first source 43 connected to the first channel contact electrode 41 located on one side of the first channel region 31, and a first drain 45 connected to the first channel contact electrode 41 located on the other side of the first channel region 31.

[0052] The end of the first source electrode 43 has a first protrusion with a length of L1 extending toward the center of the first channel region 31. The protrusion is the extra area after the first source electrode 43 and the first channel contact electrode 41 located below the first source electrode 43 overlap in space; the end of the first drain electrode 44 also has a protrusion with a length of L2 extending toward the center of the first channel region 31. The protrusion is the second extra area after the first drain electrode 44 and the first channel contact electrode 41 located below the first drain electrode 44 overlap in space.

[0053] The second TFT includes a second gate 22, a second channel region 32 located above the second gate 22, a second channel contact electrode 42 in contact with both sides of the second channel region 32, a second source 45 connected to the second channel contact electrode 42 located on one side of the second channel region 32, and a second drain 46 connected to the second channel contact electrode 42 located on the other side of the second channel region 32.

[0054] The end of the second source electrode 45 has a second protrusion with a length of L2 extending toward the center of the second channel region 32. The protrusion is the extra area after the second source electrode 45 and the second channel contact electrode 42 located below the second source electrode 45 overlap in space. The end of the second drain electrode 46 also has a first protrusion with a length of L1 extending toward the center of the second channel region 32. The protrusion is the extra area after the second drain electrode 46 and the second channel contact electrode 42 located below the second drain electrode 46 overlap in space.

[0055] That is, the high-voltage thin film transistor is formed by epitaxially growing the source and drain to form the first source 43 , the first drain 43 , the second source 44 and the second drain 45 .

[0056] The source-drain connection electrode 47 connects the first drain electrode 44 and the second source electrode 45 .

[0057] The multiple high-voltage thin-film transistors also include a gate dielectric layer 20, a first oxide insulating layer 51, a first contact hole 511 connected to the first channel contact electrode 41, a second contact hole 512 connected to the second channel contact electrode 42, a third contact hole 513 connecting the adjacent first channel contact electrode 41 and the second channel contact electrode 42, and a second oxide insulating layer 52.

[0058] The gate dielectric layer 20 covers the first gate electrode 21 and the second gate electrode 22, and the first channel region 31 and the second channel region 32 are located on the gate dielectric layer 20; the first oxide insulating layer 51 covers the first channel contact electrode 41 and the second channel contact electrode 42, the first channel region 31 and the second channel region 32; the second oxide insulating layer 52 covers the first source electrode 43, the first drain electrode 44, the second source electrode 45, the second drain electrode 46, the source-drain connecting electrode 47 and the first oxide insulating layer 51.

[0059] The planarization layer 60 covers the second oxide insulating layer 52 .

[0060] The first source 43 is connected to the corresponding first channel contact electrode 41 through the corresponding first contact hole 511, and the first drain 44 is connected to the corresponding first channel contact electrode 41 through the corresponding first contact hole 511; the second source 45 is connected to the corresponding second channel contact electrode 42 through the corresponding second contact hole 512, and the second drain 46 is connected to the corresponding second channel contact electrode 42 through the corresponding second contact hole 512; the source-drain connection electrode 47 is connected to the first drain 44 and the second source 45 through the third contact hole 513.

[0061] like Figure 3 As shown, the working principle of the high-voltage thin film transistor is as follows: the first TFT ( Figure 3 TFT1) and the second TFT ( Figure 3 TFT2) is connected in series, Figure 3 This is a circuit diagram of a high-voltage thin-film transistor. The first source 43 of the first TFT is connected to the signal line S, the first drain 44 of the first TFT is connected to the second source 45 of the second TFT, the second drain 46 of the second TFT is connected to one end of the component (i.e., the driving electrode 90), and the other end of the component is grounded.

[0062] Assume that the voltage at the first source 43 of the first TFT is V1, and the voltage at the first drain 44 is V2. Since the first drain 44 of the first TFT is connected to the second source 45 of the second TFT, the voltage at the second source 45 is also V2, and the voltage at the drain 46 of the second TFT is V3. When a high voltage is applied to the signal line, the voltages are sequentially applied to the first TFT, the second TFT, and the electronic components, with the voltage order being V1 > V2 > V3.

[0063] For the first TFT, the voltage V2 of the first drain electrode 44 is greater than 0, so the second protrusion L2 of the first TFT will act on the first channel region 31, reducing the channel electron concentration in this region and increasing the on-resistance, thereby increasing the voltage division of the first TFT.

[0064] For the second TFT, the voltage V2 of the second source 45 is greater than 0, so the second protrusion L2 of the second TFT will act on the second channel region 32, increasing the channel electron concentration in this region and reducing the on-resistance, thereby reducing the voltage division of the second TFT.

[0065] That is to say, the voltage divided by the first TFT will be greater than the voltage divided by the second TFT. The first TFT is the main part of the high-voltage transistor that withstands the high voltage. Conversely, when a negative high voltage is applied to the signal line, the voltage divided by the second TFT will be greater than the voltage divided by the first TFT. The second TFT is the main part of the high-voltage transistor that withstands the high voltage. The principle is the same as the above analysis.

[0066] Since the first TFT and the second TFT are symmetrically arranged, the high-voltage transistor composed of the first TFT and the second TFT can be applied with an AC signal voltage without affecting the performance of the TFT. This is very important for digital microfluidic chips because many biomolecules will adhere to the surface of the digital microfluidic chip when driven by voltage, reducing the life of the device. The AC signal can reduce the adhesion of biomolecules, thereby increasing the life of the device. Figure 4 As shown, the discrete hydrophobic film 101 includes a dielectric layer film 1011 and a hydrophobic layer film 1012 located on the dielectric layer film 1011 .

[0067] The dielectric layer film 1011 includes an insulating polymer compound or a composite layer of polymer and oxide, and functions as an insulating layer. The dielectric layer film 1011 is located between the hydrophobic layer film 1012 and the driving electrode 90 .

[0068] The hydrophobic layer film 1012 includes various perfluorinated molecules, including Teflon, Cytop, and Fluoropel, and plays a hydrophobic role. The hydrophobic layer film 1012 is located on the surface of the dielectric layer film 1011.

[0069] The hydrophobic film 104 and the hydrophobic layer 1012 are made of the same material.

[0070] The discrete hydrophobic film and the AM-TFT array substrate are discrete and manufactured separately. When in use, the discrete hydrophobic film is directly attached to the driving electrode 90 of the AM-TFT array substrate. After use, it can be directly torn off from the surface of the AM-TFT array substrate and thrown away. The underlying AM-TFT array substrate can be reused.

[0071] The manufacturing method of the discrete hydrophobic membrane 101 is as follows:

[0072] S1: Cleaning and blowing silicon wafers: ultrasonically clean the silicon wafers with acetone, isopropyl alcohol and water in sequence and blow dry with nitrogen;

[0073] S2: Spin-coating polyvinyl alcohol resin (PVA) on the surface of the silicon wafer as a sacrificial layer film;

[0074] S3: depositing a polymer compound or a composite layer of a polymer and an oxide on the surface of the PVA as a dielectric layer film 1011, such as a Parylene C (poly(chloroparaxylene)) film or a laminated film thereof with an oxide;

[0075] S4: A metal frame is attached to the surface of the dielectric layer film 1011, and then the silicon wafer is immersed in an aqueous solution, and the Parylene C film is transferred to the fixed frame, and then the dielectric layer film 1011 is annealed;

[0076] S5: using a spin-coating method to deposit a fluorinated molecular hydrophobic film on the surface of the dielectric layer film 1011 .

[0077] The oxides in the composite layer of polymer and oxide used as dielectric film 1011 in step S3 include SiO2, Al2O3, HfO2, and ZrO2; the thickness of dielectric film 1011 is 500 nanometers to 20 micrometers. The thickness of fluorinated polymer film is 10 nanometers to 100 nanometers.

[0078] The digital microfluidic chip of the present invention uses high-voltage thin-film transistors, which can provide a voltage of more than 200V, which is beneficial to improving the versatility of the digital microfluidic chip; the high-voltage thin-film transistors can achieve a higher on-current and can apply AC signals, thereby increasing the service life of the digital microfluidic chip.

[0079] The above disclosure is only a preferred embodiment of the present invention, and certainly cannot be used to limit the scope of the rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A digital microfluidic chip comprising an active matrix thin film transistor array substrate, characterized in that: The active matrix thin film transistor array substrate further comprises a discrete hydrophobic film, an upper cover plate, a hydrophobic film deposited on the bottom of the upper cover plate, and a liquid droplet and silicone oil injected between the discrete hydrophobic film and the hydrophobic film; the active matrix thin film transistor array substrate comprises a plurality of high-voltage thin film transistors, each high-voltage thin film transistor controls a liquid droplet, and comprises a first TFT and a second TFT connected in series, and a source-drain connection electrode connecting the first TFT and the second TFT in series, wherein the first TFT and the second TFT are symmetrically arranged; The first TFT and the second TFT each include a gate electrode, a channel region located above the gate electrode, channel contact electrodes respectively contacting both sides of the channel region, a source electrode connected to the channel contact electrode located on one side of the channel region, and a drain electrode connected to the channel contact electrode located on the other side of the channel region; the drain electrode of the first TFT is connected to the source electrode of the second TFT; The end of the source electrode has a protrusion extending toward the center of the corresponding channel region, and the protrusion is the excess area after the source electrode and the channel contact electrode located below the source electrode overlap in space; the end of the drain electrode also has a protrusion extending toward the center of the corresponding channel region, and the protrusion is the excess area after the drain electrode and the channel contact electrode located below the drain electrode overlap in space.

2. The digital microfluidic chip according to claim 1, characterized in that: The length of the first protrusion of the source of the first TFT is equal to the length of the second protrusion of the drain of the second TFT, and the length of the second protrusion of the drain of the first TFT is equal to the length of the first protrusion of the source of the first TFT.

3. The digital microfluidic chip according to claim 1, characterized in that: The plurality of high-voltage thin film transistors further include a source-drain connection electrode electrically connected to the drain of the first TFT and the source of the second TFT.

4. The digital microfluidic chip according to claim 3, characterized in that: The multiple high-voltage thin-film transistors also include a contact hole connected to each channel contact electrode and a third contact hole connecting adjacent channel contact electrodes; the source and drain are both connected to the corresponding channel contact electrodes through the corresponding contact holes, and the source-drain connection electrode is connected to the drain of the first TFT and the source of the second TFT through the third contact hole.

5. The digital microfluidic chip according to claim 4, characterized in that: Multiple high-voltage thin-film transistors also include a gate dielectric layer, a first oxide insulating layer and a second oxide insulating layer; the gate dielectric layer covers the gate, and the channel region is located on the gate dielectric layer; the first oxide insulating layer covers the channel contact electrode and the channel region; the second oxide insulating layer covers the source and drain, the source-drain connecting electrode and the first oxide insulating layer.

6. The digital microfluidic chip according to claim 5, characterized in that: The active matrix thin film transistor array substrate also includes a planar layer covering multiple high-voltage thin film transistors, a shielding electrode located on the planar layer and on the gate of the thin film transistor, an insulating layer located on the shielding electrode and the planar layer, and a driving electrode located on the insulating layer and passing through the insulating layer to contact the drain of the thin film transistor.

7. The digital microfluidic chip according to claim 1, characterized in that: The discrete hydrophobic film and the active matrix thin film transistor array substrate are discrete and manufactured separately.

8. The digital microfluidic chip according to claim 1, characterized in that: The discrete hydrophobic film includes a dielectric layer film and a hydrophobic layer film located on the dielectric layer film.

9. The digital microfluidic chip according to claim 8, characterized in that: The dielectric layer film includes an insulating polymer compound or a composite layer of a polymer and an oxide.

10. The digital microfluidic chip according to claim 8, characterized in that: The thickness of the dielectric layer film is 500 nanometers to 20 micrometers.

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