Display substrate, manufacturing method thereof and display device

Abstract

A display substrate, a manufacturing method thereof and a display device, the display substrate comprising: a sub-pixel, a plurality of data lines and a plurality of power lines; the sub-pixel comprising: a driving circuit; the driving circuit comprising: a transistor and a capacitor; the display substrate comprising: a substrate and, on the substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer; the second metal layer comprising: a second pole plate of the capacitor; the second pole plate of the capacitor being connected with a second pole plate of the capacitor in a first adjacent driving circuit located in the same row; the third insulating layer comprising: a first via hole and a second via hole; the third metal layer comprising: a power line; the power line comprising at least three power supply parts: a first power supply part, a second power supply part and a third power supply part; the second power supply part connecting the first power supply part and the third power supply part; the third metal layer being electrically connected with the second metal layer through the first via hole, and the third metal layer being electrically connected with the active layer of the transistor through the second via hole.

Description

[0001] This application is a divisional application of the application filed on October 29, 2019, with application number 201911038883.4 and invention title "A display substrate and its manufacturing method, and a display device". Technical Field

[0002] This article relates to the field of display technology, specifically to a display substrate and its manufacturing method, and a display device. Background Technology

[0003] Organic light-emitting diode (OLED) display substrates are different from traditional liquid crystal display (LCD) substrates. They possess advantages such as active light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-thinness, and low cost. Therefore, they have become one of the important developments in next-generation display devices and are receiving increasing attention.

[0004] To achieve high-frequency driving of OLED display substrates, a dual-data-line OLED display substrate has been proposed in related technologies, where each column of sub-pixels is connected to two data lines. However, because the power lines and data lines in the OLED display substrates of these related technologies are relatively close to each other, the load on the data lines is large, resulting in high power consumption of the OLED display substrate and a long data signal writing time provided by the data lines. Summary of the Invention

[0005] This application provides a display substrate and its manufacturing method, as well as a display device, which reduces the load on the data line, thereby reducing the power consumption of the display substrate and shortening the data signal writing time.

[0006] In a first aspect, this application provides a display substrate, comprising: sub-pixels arranged in an array, multiple data lines and multiple power lines; at least one sub-pixel includes: a driving circuit; the driving circuit includes: a transistor and a capacitor; the capacitor includes: a first electrode plate and a second electrode plate disposed opposite to each other; the display substrate includes: a substrate and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer sequentially stacked on the substrate;

[0007] The active layer includes: the active layer of at least one transistor in a driving circuit;

[0008] The first metal layer includes: the first electrode of the capacitor;

[0009] The second metal layer includes: a second plate of a capacitor; the second plate of the capacitor in the driving circuit is connected to the second plate of the capacitor in the first adjacent driving circuit located in the same row;

[0010] The third insulating layer includes: a first via and a second via;

[0011] The third metal layer includes: a power line; the power line includes at least three power sections: a first power section, a second power section, and a third power section; the second power section connects the first power section and the third power section; the data line is arranged parallel to the extending direction of the first power section and the second power section.

[0012] The third metal layer is electrically connected to the second metal layer through the first via, and the third metal layer is electrically connected to the active layer of the transistor through the second via.

[0013] In some possible implementations, the driving circuit includes: a first transistor to a seventh transistor, wherein the first terminal of the fifth transistor is connected to a power supply line, and the active layer of the transistor in at least one driving circuit includes: the active layer of the first transistor to the seventh transistor, an active layer protrusion, and a power supply connection portion; the active layer of at least one transistor includes: a channel portion and a first conductor portion and a second conductor portion located on both sides of the channel portion, the first terminal of the transistor is connected to the first conductor portion, and the second terminal of the transistor is connected to the second conductor portion;

[0014] For at least one driving circuit, the first conductor portion of the fifth transistor is connected to the active layer bump and the power connection portion, respectively, wherein the first conductor portion, the active layer bump, and the power connection portion of the fifth transistor are configured to write a power signal, wherein the power signal is a signal of the power line.

[0015] In some possible implementations, for at least one driving circuit, the active layer bump and the power connection portion are located on both sides of the first conductor portion of the fifth transistor.

[0016] In some possible implementations, the active layer protrusion is located on the side of the first conductor portion of the fifth transistor away from the active layer of the sixth transistor, and the power connection portion is located on the side of the first conductor portion of the fifth transistor close to the active layer of the sixth transistor.

[0017] In some possible implementations, an active layer bump in at least one drive circuit is connected to an active layer bump in a second adjacent drive circuit located in the same row.

[0018] In some possible implementations, the power line is electrically connected to the power connection portion through the second via.

[0019] In some possible implementations, the second metal layer further includes: a connecting electrode; the second power supply unit is connected to the connecting electrode through a first via, and the third power supply unit is connected to the second plate of the capacitor through the first via.

[0020] In some possible implementations, the first metal layer further includes: multiple gate lines, multiple reset signal lines, and multiple light emission control signal lines;

[0021] The orthographic projection of the first power supply unit on the substrate coincides with the orthographic projections of the initial signal line and the reset signal line on the substrate;

[0022] The orthographic projection of the second power supply unit on the substrate does not overlap with the orthographic projections of the second plate of the capacitor and the gate line on the substrate, and the orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projections of the connection electrode and the active layer of the first transistor on the substrate.

[0023] The orthographic projection of the third power supply unit on the substrate at least partially overlaps with the orthographic projections of the gate line, the second substrate of the capacitor, and the light emission control signal on the substrate.

[0024] In some possible implementations, a sixth via is formed on the first insulating layer, the second insulating layer, and the third insulating layer, exposing the first conductor portion of the active layer of the sixth transistor;

[0025] For at least one drive circuit, the dummy line of the first power supply unit passes through the sixth via.

[0026] In some possible implementations, the second metal layer further includes: an initial signal line; the first insulating layer, the second insulating layer, and the third insulating layer also have a third via that exposes the second conductor portion of the active layer of the seventh transistor; and the third insulating layer also has an eighth via that exposes the initial signal line.

[0027] For at least one drive circuit, the dummy line of the third power supply unit passes through the third via and the eighth via.

[0028] In some possible implementations, the angle between the first power supply unit and the second power supply unit is greater than or equal to 90 degrees and less than 180 degrees;

[0029] The angle between the second power supply unit and the third power supply unit is greater than or equal to 90 degrees and less than 180 degrees.

[0030] In some possible implementations, the width of the first power supply section is greater than or equal to the width of the third power supply section;

[0031] The width of the first power supply section is greater than or equal to the width of the second power supply section.

[0032] In some possible implementations, the data line is located in the third metal layer.

[0033] In some possible implementations, the data line includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line are respectively located on both sides of the power line;

[0034] For the i-th row driving circuit, the distance between the first power supply section and the first sub-data line is greater than the distance between the first power supply section and the second sub-data line, and the distance between the third power supply section and the first sub-data line is less than the distance between the third power supply section and the second sub-data line;

[0035] For the (i+1)th row driving circuit, the distance between the first power supply section and the first sub-data line is less than the distance between the first power supply section and the second sub-data line, and the distance between the third power supply section and the first sub-data line is greater than the distance between the third power supply section and the second sub-data line.

[0036] In some possible implementations, the pixel structures of adjacent sub-pixels are symmetrically arranged along the midline of the pixel structures of adjacent sub-pixels.

[0037] In some possible implementations, adjacent power lines are symmetrically arranged along the centerline between adjacent power lines.

[0038] In some possible implementations, for at least one driving circuit, the second plate of the capacitor includes: an integrally formed body portion and a protrusion portion;

[0039] The protrusion is located on one side of the main body, and the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate.

[0040] The orthographic projection of the main body on the substrate partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the main body has a through hole that exposes the first electrode plate of the capacitor.

[0041] In some possible implementations, the connecting electrode includes: an integrally formed first connecting portion and a second connecting portion;

[0042] The first connecting portion extends in the same direction as the data line, and the second connecting portion extends in the same direction as the gate line.

[0043] The orthographic projection of the first connection portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate, and the orthographic projection of the second connection portion on the active layer of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate.

[0044] The dummy line of the first connection passes through the protrusion of the second plate of the capacitor.

[0045] In some possible implementations, the first metal layer further includes: a gate electrode of a second transistor, the gate electrode of the second transistor being integrally formed with the gate line, the gate electrode of the second transistor including: a first branch segment and a second branch segment connected to each other;

[0046] The first branch segment extends in the same direction as the data line, and the second branch segment extends in the same direction as the gate line.

[0047] The dummy line of the first branch segment passes through the second connection portion of the connecting electrode.

[0048] In some possible implementations, at least one drive circuit located in the i-th row is connected to the first sub-data line;

[0049] At least one drive circuit located in the (i+1)th row is connected to the second sub-data line; 1≤i≤M, and i is an odd number.

[0050] In some possible implementations, the t-th power line and the (t+1)-th power line include: the first sub-data line of the t-th data line and the first sub-data line of the (t+1)-th data line, or the second sub-data line of the t-th data line and the second sub-data line of the (t+1)-th data line.

[0051] In some possible implementations, the first sub-data line of the j-th data line is located on the side of the j-th power line closer to the (j-1)-th column of the drive circuit, and the second sub-data line of the j-th data line is located on the side of the j-th power line closer to the (j+1)-th column of the drive circuit.

[0052] The first sub-data line of the (j+1)th data line is located on the side of the (j+1)th power line closest to the (j+2)th column drive circuit, and the second sub-data line of the (j+1)th data line is located on the side of the (j+1)th power line closest to the (j)th column drive circuit, 1≤j≤N, and j is an odd number.

[0053] In some possible implementations, the orthographic projections of the first sub-data line and the second sub-data line onto the substrate at least partially overlap with the orthographic projections of the initial signal line, the reset signal line, the gate line, and the light emission control signal line onto the substrate.

[0054] In some possible implementations, the width of the first power supply section is greater than the width of the first sub-data line and also greater than the width of the second sub-data line.

[0055] In some possible implementations, for at least one driving circuit, the active layers of all transistors are a single-piece structure.

[0056] The active layer of the sixth transistor in the driving circuit located in row s and column t is connected to the active layer of the seventh transistor in the driving circuit located in row s+1 and column t; 1≤s≤M, 1≤t≤N, where M is the number of rows of the driving circuit and N is the number of columns of the driving circuit.

[0057] The active layer protrusion of the driving circuit located in row i and column j+1 is connected to the active layer protrusion of the driving circuit located in row i and column j+2; the active layer protrusion of the driving circuit located in row i+1 and column j is connected to the active layer protrusion located in row i+1 and column j+1; 1≤i≤M, 1≤j≤N, and i and j are odd numbers.

[0058] In some possible implementations, the first plate of the capacitor includes: a first side and a second side disposed opposite to each other; for at least one driving circuit, the gate line and the reset signal line are located on the first side of the first plate of the capacitor, the reset signal line is located on the side of the gate line away from the first plate of the capacitor, and the light emission control signal line is located on the second side of the first plate of the capacitor.

[0059] The first metal layer further includes: the gate electrode of the first transistor to the gate electrode of the seventh transistor, wherein the gate electrode of the first transistor is disposed across the active layer of the first transistor, the gate electrode of the second transistor is disposed across the active layer of the second transistor, the gate electrode of the third transistor is disposed across the active layer of the third transistor, the gate electrode of the fourth transistor is disposed across the active layer of the fourth transistor, the gate electrode of the fifth transistor is disposed across the active layer of the fifth transistor, the gate electrode of the sixth transistor is disposed across the active layer of the sixth transistor, and the gate electrode of the seventh transistor is disposed across the active layer of the seventh transistor.

[0060] The gate electrode of the first transistor, the gate electrode of the seventh transistor, and the reset signal line are integrally formed; the gate electrode of the second transistor, the gate electrode of the fourth transistor, and the gate line are integrally formed; the gate electrode of the third transistor and the first plate of the capacitor are integrally formed; and the gate electrode of the fifth transistor, the gate electrode of the sixth transistor, and the light emission control signal line are integrally formed.

[0061] In some possible implementations, for at least one driving circuit, the first insulating layer, the second insulating layer and the third insulating layer are further provided with a fourth via and a fifth via, and the second insulating layer and the third insulating layer are provided with a seventh via;

[0062] The fourth via exposes the active layer of the fourth transistor, the fifth via exposes the active layer of the second transistor, the sixth via exposes the active layer of the sixth transistor, and the seventh via exposes the first plate of the capacitor.

[0063] In some possible implementations, the third metal layer further includes: the first and second terminals of the first transistor, the first and second terminals of the second transistor, the first terminal of the fourth transistor, the second terminal of the fifth transistor, the second terminal of the sixth transistor, and the first and second terminals of the seventh transistor;

[0064] For at least one driving circuit, the second electrode of the first transistor and the second electrode of the seventh transistor are integrally formed, and the orthographic projection of the second electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer, the initial signal line and the reset signal line of the seventh transistor on the substrate.

[0065] The first electrode of the first transistor and the second electrode of the second transistor are integrally formed, and the orthographic projection of the first electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer and gate line of the second transistor on the substrate.

[0066] The second electrode of the sixth transistor and the second electrode of the seventh transistor are integrally formed, and the orthographic projection of the second electrode of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate;

[0067] The first electrode of the fourth transistor in the driving circuit located in row i is integrally formed with the first sub-data line, and the first electrode of the fourth transistor in the driving circuit located in row i+1 is integrally formed with the second sub-data line. The orthographic projection of the first electrode of the fourth transistor on the substrate and the orthographic projection of the active layer of the fourth transistor on the substrate at least partially overlap.

[0068] In some possible implementations, the dummy line of the first pole of the fourth transistor is projected onto the substrate through the active layer protrusion.

[0069] In some possible implementations, the orthographic projection of the second electrode of the second transistor onto the substrate overlaps with the orthographic projection of the seventh via onto the substrate.

[0070] The dummy line of the second terminal of the second transistor passes through the second power supply section.

[0071] Secondly, this application also provides a display device, including the above-mentioned display substrate, as well as a timing controller, a data driver, a scan driver, and a light-emitting driver; the display substrate includes: data lines, gate lines, and light-emitting control signal lines;

[0072] The timing controller is electrically connected to the data driver, the scan driver, and the light-emitting driver, respectively;

[0073] The data driver is connected to the data line, the scan driver is connected to the gate line, and the light-emitting driver is connected to the light-emitting control signal line.

[0074] Thirdly, this application also provides a method for manufacturing a display substrate, used to manufacture the aforementioned display substrate, the method comprising:

[0075] Provide a base;

[0076] An active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer are sequentially formed on the substrate.

[0077] This application provides a display substrate and its manufacturing method, as well as a display device. The display substrate includes: sub-pixels arranged in an array, multiple data lines, and multiple power lines; at least one sub-pixel includes: a driving circuit; the driving circuit includes: a transistor and a capacitor; the capacitor includes: a first electrode plate and a second electrode plate disposed opposite to each other; the display substrate includes: a substrate and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer sequentially stacked on the substrate; the active layer includes: the active layer of at least one transistor in the driving circuit; the first metal layer includes: the first electrode plate of the capacitor; the second metal layer includes: the second electrode plate of the capacitor; the second electrode plate of the capacitor in the driving circuit is located on the same... The second plate of the capacitor in the first adjacent driving circuit of the row is connected; the third insulating layer includes: a first via and a second via; the third metal layer includes: a power line; the power line includes at least three power sections: a first power section, a second power section, and a third power section; the second power section connects the first power section and the third power section; the data line is arranged parallel to the extending direction of the first power section and the second power section; the third metal layer is electrically connected to the second metal layer through the first via, and the third metal layer is electrically connected to the active layer of the transistor through the second via. Therefore, the technical solution provided in this application increases the distance between some power lines and data lines, reduces the load on the data lines, thereby reducing the power consumption of the display substrate and shortening the writing time of the data signal.

[0078] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application may be realized and obtained by means of the embodiments described in the description, claims, and drawings. Attached Figure Description

[0079] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0080] Figure 1 This is a schematic diagram of the structure of the display substrate provided in the embodiments of this application;

[0081] Figure 2 A top view of multiple sub-pixels provided in an embodiment of this application;

[0082] Figure 3 A side view of multiple sub-pixels provided in an embodiment of this application;

[0083] Figure 4 Equivalent circuit diagram of the driving circuit provided in the embodiments of this application;

[0084] Figure 5 This is a top view of a sub-pixel in a display substrate provided in an embodiment of this application;

[0085] Figure 6 This is a top view of another portion of the sub-pixels in the display substrate provided in an embodiment of this application;

[0086] Figure 7 This is a top view of another portion of the sub-pixels in the display substrate provided in an embodiment of this application;

[0087] Figure 8 A flowchart illustrating a method for manufacturing a display substrate according to an embodiment of this application;

[0088] Figure 9 A schematic diagram illustrating the fabrication of the active layer of the display substrate provided in an embodiment of this application;

[0089] Figure 10 This is a schematic diagram illustrating the fabrication of the first insulating layer and the first metal layer of the display substrate provided in an embodiment of this application;

[0090] Figure 11 This is a schematic diagram illustrating the fabrication of the second insulating layer and the second metal layer of the display substrate provided in an embodiment of this application.

[0091] Figure 12 This is a schematic diagram illustrating the fabrication of the third insulating layer provided in an embodiment of this application. Detailed Implementation

[0092] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0093] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0094] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0095] Unless otherwise defined, the technical or scientific terms used in the embodiments of this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0096] The OLED display substrate of the related technology includes multiple sub-pixels, power lines, and data lines. Each sub-pixel includes a capacitor, which includes a first electrode plate and a second electrode plate disposed opposite to each other. The second electrode plate of the capacitor is connected to the power line, and the second electrode plates of the capacitors of adjacent sub-pixels are interconnected. The power lines and data lines are disposed on the same layer.

[0097] In related OLED display substrates, the second plates of capacitors in all sub-pixels located in the same row are reused as power connection lines. This ensures that the power signal supplied by the power lines to each sub-pixel is identical, preventing display defects in the OLED display substrate. Specifically, the extension direction of the power connection lines is perpendicular to the extension direction of the data lines. However, due to the significant overlap between the power connection lines and data lines, and their close proximity, the data lines experience a higher load, leading to higher power consumption in the OLED display substrate and a longer data signal writing time.

[0098] To address the aforementioned technical problems, this application provides a display substrate, a method for manufacturing the same, and a display device, as detailed below:

[0099] A display substrate includes: sub-pixels arranged in an array, multiple data lines and multiple power lines; at least one sub-pixel includes: a driving circuit; the driving circuit includes: a transistor and a capacitor; the capacitor includes: a first electrode plate and a second electrode plate disposed opposite to each other; the display substrate includes: a substrate and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer sequentially stacked on the substrate;

[0100] The active layer includes: the active layer of at least one transistor in a driving circuit;

[0101] The first metal layer includes: the first electrode of the capacitor;

[0102] The second metal layer includes: a second plate of a capacitor; the second plate of the capacitor in the driving circuit is connected to the second plate of the capacitor in the first adjacent driving circuit located in the same row;

[0103] The third insulating layer includes: a first via and a second via;

[0104] The third metal layer includes: a power line; the power line includes at least three power sections: a first power section, a second power section, and a third power section; the second power section connects the first power section and the third power section; the data line is arranged parallel to the extending direction of the first power section and the second power section.

[0105] The third metal layer is electrically connected to the second metal layer through the first via, and the third metal layer is electrically connected to the active layer of the transistor through the second via.

[0106] In one exemplary embodiment, the driving circuit includes: a first transistor to a seventh transistor, wherein the first electrode of the fifth transistor is connected to a power supply line, and the active layer of the transistor in at least one driving circuit includes: the active layer of the first transistor to the seventh transistor, an active layer protrusion, and a power supply connection portion; the active layer of at least one transistor includes: a channel portion and a first conductor portion and a second conductor portion respectively located on both sides of the channel portion, the first electrode of the transistor is connected to the first conductor portion, and the second electrode of the transistor is connected to the second conductor portion;

[0107] For at least one driving circuit, the first conductor portion of the fifth transistor is connected to the active layer bump and the power connection portion, respectively, wherein the first conductor portion, the active layer bump, and the power connection portion of the fifth transistor are configured to write a power signal, wherein the power signal is a signal of the power line.

[0108] In one exemplary embodiment, for at least one driving circuit, the active layer bump and the power connection portion are respectively located on both sides of the first conductor portion of the fifth transistor.

[0109] In one exemplary embodiment, the active layer protrusion is located on the side of the first conductor portion of the fifth transistor away from the active layer of the sixth transistor, and the power connection portion is located on the side of the first conductor portion of the fifth transistor close to the active layer of the sixth transistor.

[0110] In one exemplary embodiment, an active layer protrusion in at least one driving circuit is connected to an active layer protrusion in a second adjacent driving circuit located in the same row.

[0111] In one exemplary embodiment, the power line is electrically connected to the power connection portion through the second via.

[0112] In one exemplary embodiment, the second metal layer further includes: a connecting electrode; the second power supply unit is connected to the connecting electrode through a first via, and the third power supply unit is connected to the second plate of the capacitor through the first via.

[0113] In one exemplary embodiment, the first metal layer further includes: a plurality of gate lines, a plurality of reset signal lines, and a plurality of light emission control signal lines;

[0114] The orthographic projection of the first power supply unit on the substrate coincides with the orthographic projections of the initial signal line and the reset signal line on the substrate;

[0115] The orthographic projection of the second power supply unit on the substrate does not overlap with the orthographic projections of the second plate of the capacitor and the gate line on the substrate, and the orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projections of the connection electrode and the active layer of the first transistor on the substrate.

[0116] The orthographic projection of the third power supply unit on the substrate at least partially overlaps with the orthographic projections of the gate line, the second substrate of the capacitor, and the light emission control signal on the substrate.

[0117] In one exemplary embodiment, a sixth via is formed on the first insulating layer, the second insulating layer, and the third insulating layer, exposing a first conductor portion of the active layer of the sixth transistor;

[0118] For at least one drive circuit, the dummy line of the first power supply unit passes through the sixth via.

[0119] In one exemplary embodiment, the second metal layer further includes: an initial signal line; the first insulating layer, the second insulating layer, and the third insulating layer further have a third via that exposes a second conductor portion of the active layer of the seventh transistor; and the third insulating layer further has an eighth via that exposes the initial signal line.

[0120] For at least one drive circuit, the dummy line of the third power supply unit passes through the third via and the eighth via.

[0121] In one exemplary embodiment, the included angle between the first power supply unit and the second power supply unit is greater than or equal to 90 degrees and less than 180 degrees;

[0122] The angle between the second power supply unit and the third power supply unit is greater than or equal to 90 degrees and less than 180 degrees.

[0123] In one exemplary embodiment, the width of the first power supply unit is greater than or equal to the width of the third power supply unit;

[0124] The width of the first power supply section is greater than or equal to the width of the second power supply section.

[0125] In one exemplary embodiment, the data line is located in the third metal layer.

[0126] In one exemplary embodiment, the data line includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line are respectively located on both sides of the power line;

[0127] For the i-th row driving circuit, the distance between the first power supply section and the first sub-data line is greater than the distance between the first power supply section and the second sub-data line, and the distance between the third power supply section and the first sub-data line is less than the distance between the third power supply section and the second sub-data line;

[0128] For the (i+1)th row driving circuit, the distance between the first power supply section and the first sub-data line is less than the distance between the first power supply section and the second sub-data line, and the distance between the third power supply section and the first sub-data line is greater than the distance between the third power supply section and the second sub-data line.

[0129] In one exemplary embodiment, the pixel structures of adjacent sub-pixels are symmetrically arranged along the midline of the pixel structures of adjacent sub-pixels.

[0130] In one exemplary embodiment, adjacent power lines are symmetrically arranged along the centerline between adjacent power lines.

[0131] In one exemplary embodiment, for at least one driving circuit, the second plate of the capacitor includes: an integrally formed main body portion and a protrusion portion;

[0132] The protrusion is located on one side of the main body, and the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate.

[0133] The orthographic projection of the main body on the substrate partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the main body has a through hole that exposes the first electrode plate of the capacitor.

[0134] In one exemplary embodiment, the connecting electrode includes: an integrally formed first connecting portion and a second connecting portion;

[0135] The first connecting portion extends in the same direction as the data line, and the second connecting portion extends in the same direction as the gate line.

[0136] The orthographic projection of the first connection portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate, and the orthographic projection of the second connection portion on the active layer of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate.

[0137] The dummy line of the first connection passes through the protrusion of the second plate of the capacitor.

[0138] In one exemplary embodiment, the first metal layer further includes: a gate electrode of a second transistor, the gate electrode of the second transistor being integrally formed with the gate line, and the gate electrode of the second transistor including: a first branch segment and a second branch segment connected to each other.

[0139] The first branch segment extends in the same direction as the data line, and the second branch segment extends in the same direction as the gate line.

[0140] The dummy line of the first branch segment passes through the second connection portion of the connecting electrode.

[0141] In one exemplary embodiment, at least one driving circuit located in the i-th row is connected to the first sub-data line;

[0142] At least one drive circuit located in the (i+1)th row is connected to the second sub-data line; 1≤i≤M, and i is an odd number.

[0143] In one exemplary embodiment, the t-th power line and the (t+1)-th power line include: a first sub-data line of the t-th data line and a first sub-data line of the (t+1)-th data line, or a second sub-data line of the t-th data line and a second sub-data line of the (t+1)-th data line.

[0144] In one exemplary embodiment, the first sub-data line of the j-th data line is located on the side of the j-th power line near the (j-1)-th column drive circuit, and the second sub-data line of the j-th data line is located on the side of the j-th power line near the (j+1)-th column drive circuit.

[0145] The first sub-data line of the (j+1)th data line is located on the side of the (j+1)th power line closest to the (j+2)th column drive circuit, and the second sub-data line of the (j+1)th data line is located on the side of the (j+1)th power line closest to the (j)th column drive circuit, 1≤j≤N, and j is an odd number.

[0146] In one exemplary embodiment, the orthographic projections of the first sub-data line and the second sub-data line onto the substrate at least partially overlap with the orthographic projections of the initial signal line, the reset signal line, the gate line, and the light emission control signal line onto the substrate.

[0147] In one exemplary embodiment, the width of the first power supply section is greater than the width of the first sub-data line and also greater than the width of the second sub-data line.

[0148] In one exemplary embodiment, for at least one driving circuit, the active layers of all transistors are integrally formed.

[0149] The active layer of the sixth transistor in the driving circuit located in row s and column t is connected to the active layer of the seventh transistor in the driving circuit located in row s+1 and column t; 1≤s≤M, 1≤t≤N, where M is the number of rows of the driving circuit and N is the number of columns of the driving circuit.

[0150] The active layer protrusion of the driving circuit located in row i and column j+1 is connected to the active layer protrusion of the driving circuit located in row i and column j+2; the active layer protrusion of the driving circuit located in row i+1 and column j is connected to the active layer protrusion located in row i+1 and column j+1; 1≤i≤M, 1≤j≤N, and i and j are odd numbers.

[0151] In one exemplary embodiment, the first plate of the capacitor includes: a first side and a second side disposed opposite to each other; for at least one driving circuit, a gate line and a reset signal line are located on the first side of the first plate of the capacitor, the reset signal line is located on the side of the gate line away from the first plate of the capacitor, and the light emission control signal line is located on the second side of the first plate of the capacitor.

[0152] The first metal layer further includes: the gate electrode of the first transistor to the gate electrode of the seventh transistor, wherein the gate electrode of the first transistor is disposed across the active layer of the first transistor, the gate electrode of the second transistor is disposed across the active layer of the second transistor, the gate electrode of the third transistor is disposed across the active layer of the third transistor, the gate electrode of the fourth transistor is disposed across the active layer of the fourth transistor, the gate electrode of the fifth transistor is disposed across the active layer of the fifth transistor, the gate electrode of the sixth transistor is disposed across the active layer of the sixth transistor, and the gate electrode of the seventh transistor is disposed across the active layer of the seventh transistor.

[0153] The gate electrode of the first transistor, the gate electrode of the seventh transistor, and the reset signal line are integrally formed. The gate electrode of the second transistor, the gate electrode of the fourth transistor, and the gate line are integrally formed. The gate electrode of the third transistor and the first plate of the capacitor are integrally formed. The gate electrode of the fifth transistor, the gate electrode of the sixth transistor, and the light-emitting control signal line are integrally formed.

[0154] In one exemplary embodiment, for at least one driving circuit, the first insulating layer, the second insulating layer and the third insulating layer are further provided with a fourth via and a fifth via, and the second insulating layer and the third insulating layer are provided with a seventh via;

[0155] The fourth via exposes the active layer of the fourth transistor, the fifth via exposes the active layer of the second transistor, the sixth via exposes the active layer of the sixth transistor, and the seventh via exposes the first plate of the capacitor.

[0156] In one exemplary embodiment, the third metal layer further includes: a first electrode and a second electrode of a first transistor, a first electrode and a second electrode of a second transistor, a first electrode of a fourth transistor, a second electrode of a fifth transistor, a second electrode of a sixth transistor, and a first electrode and a second electrode of a seventh transistor;

[0157] For at least one driving circuit, the second electrode of the first transistor and the second electrode of the seventh transistor are integrally formed, and the orthographic projection of the second electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer, the initial signal line and the reset signal line of the seventh transistor on the substrate.

[0158] The first electrode of the first transistor and the second electrode of the second transistor are integrally formed, and the orthographic projection of the first electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer and gate line of the second transistor on the substrate.

[0159] The second electrode of the sixth transistor and the second electrode of the seventh transistor are integrally formed, and the orthographic projection of the second electrode of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate;

[0160] The first electrode of the fourth transistor in the driving circuit located in row i is integrally formed with the first sub-data line, and the first electrode of the fourth transistor in the driving circuit located in row i+1 is integrally formed with the second sub-data line. The orthographic projection of the first electrode of the fourth transistor on the substrate and the orthographic projection of the active layer of the fourth transistor on the substrate at least partially overlap.

[0161] In one exemplary embodiment, the orthogonal projection of the dummy line of the first pole of the fourth transistor onto the substrate passes through the active layer protrusion.

[0162] In one exemplary embodiment, the orthographic projection of the second electrode of the second transistor onto the substrate overlaps with the orthographic projection of the seventh via onto the substrate.

[0163] The dummy line of the second terminal of the second transistor passes through the second power supply section.

[0164] Some embodiments of this application provide a display substrate, Figure 1 This is a schematic diagram of the structure of the display substrate provided in an embodiment of this application. Figure 2 This is a top view of multiple sub-pixels provided in an embodiment of this application. Figure 3 A side view of multiple sub-pixels provided in the embodiments of this application, such as Figures 1-3As shown, the display substrate provided in this application embodiment includes: a substrate 10 and a plurality of sub-pixels P disposed on the substrate 10, a plurality of power lines VDD and a data line D disposed on the same layer as the power lines VDD. Each sub-pixel P includes: a driving circuit; the driving circuit includes: a transistor and a capacitor. The capacitor includes: a first electrode C1 and a second electrode C2 disposed opposite to each other. The active layer 20 of the transistor is located on the side of the second electrode C2 of the capacitor closer to the substrate 10, and the power line VDD is located on the side of the second electrode C2 of the capacitor away from the substrate 10.

[0165] Specifically, for each sub-pixel, the power line VDD is connected to the second plate C2 of the capacitor and the active layer 20 of the transistor, respectively. The second plate C2 of the capacitor in each sub-pixel is connected to the second plate C2 of the capacitor of an adjacent sub-pixel in the same row. The active layer 20 of the transistor in each sub-pixel is connected to the active layer 20 of the transistor of another adjacent sub-pixel in the same row. It should be noted that... Figure 2 This explanation uses 8 sub-pixels as an example.

[0166] Specifically, such as Figure 1 As shown, the display substrate in this embodiment includes M rows and N columns of sub-pixels, N columns of data lines D1 to DN, N columns of power lines VDD1 to VDDN, M rows of gate lines G1 to GM, M-1 rows of light emission control signal lines EM1 to EMM-1, M rows of reset signal lines Reset, and M rows of initial signal lines Vinit. The display substrate also includes: a data driver for providing data signals to the data lines, a scan driver for providing scan signals to the gate lines, a light emission driver for providing light emission control signals to the light emission control signal lines, and a timing controller for providing drive signals to the data driver, scan driver, and light emission driver.

[0167] Optionally, such as Figure 1 and Figure 2 It can be seen that the i-th column sub-pixel is connected to the i-th column data line and the i-th column power line, and 1≤i≤N.

[0168] Each column of data lines includes: a first sub-data line and a second sub-data line. The first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines Di are located on both sides of the i-th column of sub-pixels, respectively. The i-th column of power lines VDDi is located between the first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines Di. Figure 2 This explanation uses the first two rows of the first four columns as an example.

[0169] Specifically, such as Figure 1 and 2As shown, adjacent sub-pixels in the same column are connected to different sub-data lines. That is, if the sub-pixel in the i-th row and j-th column is connected to the first sub-data line DOj in the j-th column, then the sub-pixel in the (i+1)-th row and j-th column is connected to the second sub-data line DEj in the j-th column. If the sub-pixel in the i-th row and j-th column is connected to the second sub-data line DEj in the j-th column, then the sub-pixel in the (i+1)-th row and j-th column is connected to the first sub-data line DOj in the j-th column.

[0170] In this embodiment, the arrangement of the first and second sub-data lines in adjacent data lines is opposite. That is, when the first sub-data line DOi of the i-th column data line Di is located on the first side of the i-th column sub-pixel and the second sub-data line DEi of the i-th column data line Di is located on the second side of the i-th column sub-pixel, the second sub-data line DEi+1 of the (i+1)-th column data line Di+1 is located on the first side of the (i+1)-th column sub-pixel and the first sub-data line DOi+1 of the (i+1)-th column data line Di+1 is located on the second side of the (i+1)-th column sub-pixel; or when the first sub-data line DOi of the i-th column data line Di is located on the second side of the i-th column sub-pixel and the second sub-data line DEi of the i-th column data line Di is located on the first side of the i-th column sub-pixel, the second sub-data line DEi+1 of the (i+1)-th column data line Di+1 is located on the second side of the (i+1)-th column sub-pixel and the first sub-data line DOi+1 of the (i+1)-th column data line Di+1 is located on the first side of the (i+1)-th column sub-pixel.

[0171] Figure 4 The equivalent circuit diagram of the driving circuit provided in the embodiments of this application is as follows: Figure 4 As shown, Figure 4 The following description uses the driving circuit included in the i-th column sub-pixel and the (i+1)-th column sub-pixel as an example. The driving circuit provided in this application embodiment is a 7T1C structure. The driving circuit includes: a first transistor T1 to a seventh transistor T7 and a capacitor C, wherein the capacitor C includes a first plate C1 and a second plate C2.

[0172] Specifically, the gate electrode of the first transistor T1 is connected to the reset signal line Reset, the source electrode of the first transistor T1 is connected to the initial signal line Vinit, and the drain electrode of the first transistor T1 is connected to the first plate C1 of capacitor C. The gate electrode of the second transistor T2 is connected to the gate line G, the source electrode of the second transistor T2 is connected to the first plate C1 of capacitor C, and the drain electrode of the second transistor T2 is connected to the drain electrode of the sixth transistor T6. The gate electrode of the third transistor T3 is connected to the first plate C1 of capacitor C, the source electrode of the third transistor T3 is connected to the drain electrode of the fourth transistor T4, the drain electrode of the third transistor T3 is connected to the drain electrode of the sixth transistor T6, and the gate electrode of the fourth transistor T4 is connected to the gate line G. The source electrode of transistor T4 is connected to the data line D; the gate electrode of the fifth transistor T5 is connected to the light emission control signal line EM; the source electrode of the fifth transistor T5 is connected to the power supply line VDD; the drain electrode of the fifth transistor T5 is connected to the source electrode of the third transistor T3; the gate electrode of the sixth transistor T6 is connected to the light emission control signal line EM; the drain electrode of the sixth transistor T6 is connected to the anode of the light-emitting device; the gate electrode of the seventh transistor T7 is connected to the reset signal line Reset; the source electrode of the seventh transistor T7 is connected to the initial signal line Vinit; the drain electrode of the seventh transistor T7 is connected to the anode of the light-emitting device; the second plate C2 of the capacitor is connected to the power supply line VDD; and the cathode of the light-emitting device OLED is connected to the low-level power supply terminal VSS.

[0173] In this embodiment, the third transistor T3 is a driving transistor, and the other transistors besides the third transistor T3 are switching transistors. The first transistor T1 to the seventh transistor T7 provided in this embodiment can all be P-type transistors or N-type transistors. This application embodiment does not make any limitation on this.

[0174] Specifically, the general working process of the driving circuit includes: reset phase, where the reset signal line provides an effective level and the initial signal provided by the initial signal line initializes the driving circuit; write phase, where the gate line provides an effective level and writes the data signal provided by the data line into the driving circuit; and light emission phase, where the light emission control signal line provides an effective level and provides driving current to the light emission device to drive the light emission device to emit light.

[0175] Specifically, such as Figure 2 and Figure 3 As shown, the display substrate provided in this application embodiment further includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a gate line G, a reset signal line Reset, a light emission control signal line EM, and an initial signal line Vinit, which are sequentially disposed on the substrate 10.

[0176] Among them, the gate line G, the reset signal line Reset, the light emission control signal line EM, the first plate C1 of the capacitor and the gate electrode of the transistor are arranged on the same layer, the second plate C2 of the capacitor and the initial signal line Vinit are arranged on the same layer, and the data line D, the power supply line VDD and the source and drain electrodes of the transistor are arranged on the same layer.

[0177] The first insulating layer 11 is disposed between the active layer 20 of the transistor and the gate electrode of the transistor, the second insulating layer 12 is disposed between the gate electrode of the transistor and the second plate C2 of the capacitor, and the third insulating layer 13 is disposed between the second plate C2 of the capacitor and the data line.

[0178] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate. The rigid substrate can be one or more of glass and metal sheets, but is not limited to. The flexible substrate can be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited to.

[0179] Optionally, the gate electrode, source and drain electrodes, data line D, and power line VDD of the transistor are all made of metal, such as silver, aluminum, or copper. This application does not limit this in any way.

[0180] Optionally, the active layer 20 may be made of polycrystalline silicon, but this embodiment does not limit this.

[0181] In this embodiment, the second plates of interconnected capacitors and the active layers of interconnected transistors ensure that the power signals supplied to the power lines of all sub-pixels in the same row are the same, thereby avoiding display defects on the display substrate and ensuring the display effect of the display substrate.

[0182] The display substrate provided in this application includes: a substrate and multiple sub-pixels, multiple columns of power lines, and data lines disposed on the substrate. Each sub-pixel includes: a driving circuit; the driving circuit includes: a transistor and a capacitor; the capacitor includes: a first electrode plate and a second electrode plate disposed opposite to each other; the active layer of the transistor is located on the side of the second electrode plate of the capacitor closer to the substrate, and the power line is located on the side of the second electrode plate of the capacitor away from the substrate; for each sub-pixel, the power line is connected to the second electrode plate of the capacitor and the active layer of the transistor respectively; the second electrode plate of the capacitor of each sub-pixel is connected to the second electrode plate of the capacitor of an adjacent sub-pixel located in the same row; and the active layer of the transistor of each sub-pixel is connected to the active layer of the transistor of another adjacent sub-pixel located in the same row. This application embodiment uses the second electrode plate of the capacitor and the active layer of the transistor as a power connection line to transmit the power signal of the power line. Since the distance between the active layer of the transistor and the data line is greater than the distance between the second electrode plate of the capacitor and the data line, the technical solution provided in this application increases the distance between some power connection lines and data lines, reduces the load on the data line, thereby reducing the power consumption of the display substrate and shortening the data signal writing time.

[0183] Optionally, in this embodiment, as Figure 2 As shown, the active layers 20 of adjacent sub-pixels located in the same column are interconnected.

[0184] Optionally, such as Figure 2 As shown, the pixel structure of the sub-pixel located in the i-th row and j-th column is the same as that of the sub-pixel located in the (i+1)-th row and j+1-th column.

[0185] like Figure 2 As shown, adjacent power lines are symmetrical to each other. Specifically, the i-th column power line VDDi and the (i+1)-th column power line VDDi+1 are symmetrically arranged along the data line extension direction. In this embodiment, the power line VDD is a polygonal line.

[0186] Specifically, such as Figure 2 As shown in the embodiment of this application, each pixel in the display substrate includes four sub-pixels, and the pixel includes a first pixel and a second pixel.

[0187] In the first pixel, the second plate of the capacitor in the i-th sub-pixel is connected to the second plate of the capacitor in the (i+1)-th sub-pixel, and the active layer of the transistor in the i-th sub-pixel is disconnected from the active layer of the transistor in the (i+1)-th sub-pixel. The active layer of the transistor in the second sub-pixel is connected to the active layer of the transistor in the third sub-pixel, and the second plate of the capacitor in the second sub-pixel is disconnected from the second plate of the capacitor in the third sub-pixel.

[0188] In the second pixel, the second plate of the capacitor in the second sub-pixel is connected to the second plate of the capacitor in the third sub-pixel, the active layer of the transistor in the second sub-pixel is disconnected from the active layer of the transistor in the third sub-pixel, the active layer of the transistor in the i-th sub-pixel is connected to the active layer of the transistor in the (i+1)-th sub-pixel, and the second plate of the capacitor in the i-th sub-pixel is disconnected from the second plate of the capacitor in the (i+1)-th sub-pixel.

[0189] Where i is an odd number less than 4.

[0190] It should be noted that, Figure 2 This example uses two pixels arranged along a column direction. The pixel at the top is the first pixel, and the pixel at the bottom is the second pixel. This application does not limit this in any way. Since the pixel structure of adjacent sub-pixels is symmetrical in this application, in the display substrate provided in this application, the first pixel is arranged between adjacent second pixels, and the second pixel is arranged between adjacent first pixels.

[0191] Figure 5 This is a top view of a portion of a sub-pixel in a display substrate provided in an embodiment of this application. Figure 6 This is a top view of another portion of the sub-pixels in the display substrate provided in an embodiment of this application. Figure 7 This is a top view of another portion of the sub-pixels in the display substrate provided in the embodiments of this application. It should be noted that... Figure 5 The provided display substrate does not include power lines, data lines, and source / drain electrodes of transistors. Figure 6 The provided display substrate only includes the film layer containing the second electrode plate of the capacitor and the film layer containing the data lines. Figure 7 The provided display substrate only includes the active layer of the transistors and the film layer containing the data lines, such as... Figure 5 As shown in the embodiment of this application, a first via V1 is provided on the third insulating layer of the display substrate.

[0192] Specifically, in combination Figure 5 and Figure 6 In each sub-pixel, the orthographic projection of the second plate C2 of the capacitor onto the substrate covers the orthographic projection of the first via V1 onto the substrate, and the power line is connected to the second plate C2 of the capacitor through the first via V1.

[0193] Optionally, the number of first vias V1 is at least one. Specifically, the more first vias V1 there are, the better the conductivity between the power line and the second plate of the capacitor.

[0194] Optionally, such as Figure 5 As shown, in the display substrate provided in this application embodiment, a second via V2 is provided in the first insulating layer, the second insulating layer and the third insulating layer.

[0195] Specifically, in combination Figure 5 and Figure 7 In each sub-pixel, the orthographic projection of the second via V2 on the substrate overlaps with the orthographic projection of the active layer 20 on the substrate, and the power line is connected to the active layer 20 of the transistor through the second via V2.

[0196] Optionally, the number of second vias V2 is at least one. The more vias there are, the better the conductivity of the components connected through the vias.

[0197] Figures 5-7 This example uses two first vias V1 and one second via V2 for illustration, but the embodiments in this application do not impose any limitations on this.

[0198] This application embodiment also provides a method for manufacturing a display substrate, including: providing a substrate; and sequentially forming an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer on the substrate.

[0199] Based on the same inventive concept, this application also provides a method for manufacturing a display substrate, used to manufacture the display substrate provided in the above embodiments. Figure 8 A flowchart illustrating the method for manufacturing a display substrate provided in the embodiments of this application is shown below. Figure 8 As shown, the method for manufacturing a display substrate provided in this application embodiment specifically includes the following steps:

[0200] Step 100: Provide a substrate.

[0201] Step 200: Form multiple sub-pixels, multiple columns of power lines, and data lines set on the same layer as the power lines on the substrate.

[0202] Each sub-pixel includes: a driving circuit; the driving circuit includes: a transistor and a capacitor; the capacitor includes: a first electrode plate and a second electrode plate disposed opposite to each other; the active layer of the transistor is located on the side of the second electrode plate of the capacitor closer to the substrate, and the power line is located on the side of the second electrode plate of the capacitor away from the substrate.

[0203] For each sub-pixel, the power line is connected to the second plate of the capacitor and the active layer of the transistor, respectively. The second plate of the capacitor of each sub-pixel is connected to the second plate of the capacitor of an adjacent sub-pixel in the same row. The active layer of the transistor of each sub-pixel is connected to the active layer of the transistor of another adjacent sub-pixel in the same row.

[0204] The method for manufacturing the display substrate provided in this application embodiment is used to manufacture the display substrate provided in the above embodiment. Its implementation principle and effect are similar, and will not be described again here.

[0205] Taking the formation of two pixels arranged along the data line extension direction as an example, where each pixel includes four sub-pixels, for ease of explanation, this application refers to the film layer where the first electrode of the capacitor is located as the first metal layer, the film layer where the second electrode of the capacitor is located as the second metal layer, and the film layer where the power line is located as the third metal layer. Figure 9 This is a schematic diagram illustrating the fabrication of the active layer of the display substrate provided in an embodiment of this application. Figure 10 This is a schematic diagram illustrating the fabrication of the first insulating layer and the first metal layer of the display substrate provided in an embodiment of this application. Figure 11 This is a schematic diagram illustrating the fabrication of the second insulating layer and the second metal layer of the display substrate provided in an embodiment of this application. Figure 12 This is a schematic diagram of the fabrication of the third insulating layer provided in an embodiment of this application, combined with... Figures 9-12 The following further describes the method for manufacturing the display substrate provided in the embodiments of this application, with specific details as follows:

[0206] Step 101: Provide a substrate 10, and form an active layer 20 on the substrate, such as... Figure 9 As shown.

[0207] Step 102: Form a first insulating layer on the active layer 20, and form a first metal layer 30 on the first insulating layer, specifically as follows: Figure 10 As shown.

[0208] The first metal layer includes: a gate line G, a reset signal line Reset, a light emission control signal line EM, and the first plate C1 of a capacitor.

[0209] Step 103: Form a second insulating layer on the first metal layer, and then form a second metal layer on the second insulating layer, specifically as follows: Figure 11 As shown.

[0210] The second metal layer includes the initial signal line Vinit and the second plate C2 of the capacitor.

[0211] Step 104: Form a third insulating layer on the second metal layer, specifically as follows: Figure 12 As shown.

[0212] Specifically, the third insulating layer provides a first via for exposing the second plate of the capacitor, and the first, second, and third insulating layers also include a second via for exposing the active layer.

[0213] Step 105: Form a third metal layer on the third insulating layer, specifically as follows... Figure 2 As shown.

[0214] The third metal layer includes the data line D, the power line VDD, and the source and drain electrodes of the transistor.

[0215] Based on the same inventive concept, this application also provides a display device, wherein the display device includes a display substrate.

[0216] In one exemplary embodiment, the display device may further include: a timing controller, a data driver, a scan driver, and a light-emitting driver; the display substrate includes: data lines, gate lines, and light-emitting control signal lines.

[0217] In one exemplary embodiment, the timing controller is electrically connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a data line, the scan driver is connected to a gate line, and the light-emitting driver is connected to a light-emitting control signal line.

[0218] Optionally, the display substrate is an OLED display substrate.

[0219] Specifically, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This embodiment of the invention is not limited to this.

[0220] The display substrate is the same as the display substrate provided in the aforementioned embodiments, and its implementation principle and effect are similar, so it will not be described again here.

[0221] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0222] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: The array consists of sub-pixels, multiple data lines, and multiple power lines. At least one sub-pixel includes: a driving circuit; the driving circuit includes: a transistor and a capacitor; the capacitor includes: a first electrode plate and a second electrode plate disposed opposite to each other; the display substrate includes: a substrate and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer sequentially stacked on the substrate; the driving circuit includes: a first transistor to a seventh transistor, wherein the first electrode of the fifth transistor is connected to a power supply line; The active layer includes: the active layer of a transistor in at least one driving circuit; the active layer of a transistor in at least one driving circuit includes: the active layer of a first transistor to a seventh transistor, an active layer bump, and a power connection portion; the active layer of at least one transistor includes: a channel portion and a first conductor portion and a second conductor portion located on both sides of the channel portion respectively, the first electrode of the transistor is connected to the first conductor portion, the second electrode of the transistor is connected to the second conductor portion, for at least one driving circuit, the first conductor portion of the fifth transistor is connected to the active layer bump and the power connection portion respectively, wherein the first conductor portion, the active layer bump, and the power connection portion of the fifth transistor are configured to write a power signal, wherein the power signal is a power line signal; The first metal layer includes: the first electrode of the capacitor; The second metal layer includes: a second plate of a capacitor; the second plate of the capacitor in the driving circuit is connected to the second plate of the capacitor in the first adjacent driving circuit located in the same row, and the second plate of the capacitor in the driving circuit is spaced apart from the second plate of the capacitor in the second adjacent driving circuit located in the same row. The third insulating layer includes: a first via and a second via; The third metal layer includes: a power line; the power line includes at least three power sections: a first power section, a second power section, and a third power section; the second power section connects the first power section and the third power section; the data line is arranged parallel to the extending direction of the first power section and the second power section. The third metal layer is electrically connected to the second metal layer through the first via, and the third metal layer is electrically connected to the active layer of the transistor through the second via.

2. The display substrate according to claim 1, characterized in that, For at least one driving circuit, the active layer bump and the power connection portion are located on both sides of the first conductor portion of the fifth transistor.

3. The display substrate according to claim 2, characterized in that, The active layer protrusion is located on the side of the first conductor portion of the fifth transistor away from the active layer of the sixth transistor, and the power connection portion is located on the side of the first conductor portion of the fifth transistor close to the active layer of the sixth transistor.

4. The display substrate according to claim 3, characterized in that, At least one active layer protrusion in a driving circuit is connected to an active layer protrusion in a second adjacent driving circuit located in the same row.

5. The display substrate according to any one of claims 1 to 4, characterized in that, The power cord is electrically connected to the power connection part through the second through hole.

6. The display substrate according to claim 1, characterized in that, The second metal layer further includes: a connecting electrode; the second power supply unit is connected to the connecting electrode through a first via, and the third power supply unit is connected to the second plate of the capacitor through a first via.

7. The display substrate according to claim 6, characterized in that, The first metal layer further includes: multiple gate lines, multiple reset signal lines, and multiple light emission control signal lines; The orthographic projection of the first power supply unit on the substrate coincides with the orthographic projections of the initial signal line and the reset signal line on the substrate; The orthographic projection of the second power supply unit on the substrate does not overlap with the orthographic projections of the second plate of the capacitor and the gate line on the substrate, and the orthographic projection of the second power supply unit on the substrate at least partially overlaps with the orthographic projections of the connection electrode and the active layer of the first transistor on the substrate. The orthographic projection of the third power supply unit on the substrate at least partially overlaps with the orthographic projections of the gate line, the second substrate of the capacitor, and the light emission control signal on the substrate.

8. The display substrate according to claim 1, characterized in that, A sixth via is formed on the first insulating layer, the second insulating layer, and the third insulating layer, exposing the first conductor portion of the active layer of the sixth transistor; For at least one drive circuit, the dummy line of the first power supply unit passes through the sixth via.

9. The display substrate according to claim 1, characterized in that, The second metal layer further includes: an initial signal line; the first insulating layer, the second insulating layer, and the third insulating layer are further provided with a third via that exposes the second conductor portion of the active layer of the seventh transistor; the third insulating layer is further provided with an eighth via that exposes the initial signal line. For at least one drive circuit, the dummy line of the third power supply unit passes through the third via and the eighth via.

10. The display substrate according to claim 1, characterized in that, The angle between the first power supply unit and the second power supply unit is greater than or equal to 90 degrees and less than 180 degrees; The angle between the second power supply unit and the third power supply unit is greater than or equal to 90 degrees and less than 180 degrees.

11. The display substrate according to claim 1, characterized in that, The width of the first power supply section is greater than or equal to the width of the third power supply section; The width of the first power supply section is greater than or equal to the width of the second power supply section.

12. The display substrate according to claim 1, characterized in that, The data line is located in the third metal layer.

13. The display substrate according to claim 7, characterized in that, The data line includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line are respectively located on both sides of the power line; For the i-th row driving circuit, the distance between the first power supply section and the first sub-data line is greater than the distance between the first power supply section and the second sub-data line, and the distance between the third power supply section and the first sub-data line is less than the distance between the third power supply section and the second sub-data line; For the (i+1)th row driving circuit, the distance between the first power supply section and the first sub-data line is less than the distance between the first power supply section and the second sub-data line, and the distance between the third power supply section and the first sub-data line is greater than the distance between the third power supply section and the second sub-data line.

14. The display substrate according to claim 1, characterized in that, The pixel structures of adjacent sub-pixels are symmetrically arranged along the midline of the pixel structures of adjacent sub-pixels.

15. The display substrate according to claim 1, characterized in that, Adjacent power lines are symmetrically arranged along the centerline between them.

16. The display substrate according to claim 6, characterized in that, For at least one driving circuit, the second plate of the capacitor includes: an integrally formed main body and a protrusion; The protrusion is located on one side of the main body, and the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate. The orthographic projection of the main body on the substrate partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the main body has a through hole that exposes the first electrode plate of the capacitor.

17. The display substrate according to claim 16, characterized in that, The connecting electrode includes: an integrally formed first connecting part and a second connecting part; The first connecting portion extends in the same direction as the data line, and the second connecting portion extends in the same direction as the gate line. The orthographic projection of the first connection portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate, and the orthographic projection of the second connection portion on the active layer of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate. The dummy line of the first connection passes through the protrusion of the second plate of the capacitor.

18. The display substrate according to claim 7, characterized in that, The first metal layer further includes: a gate electrode of a second transistor, the gate electrode of the second transistor being integrally formed with the gate line, and the gate electrode of the second transistor including: a first branch segment and a second branch segment connected to each other; The first branch segment extends in the same direction as the data line, and the second branch segment extends in the same direction as the gate line. The dummy line of the first branch segment passes through the second connection portion of the connecting electrode.

19. The display substrate according to claim 13, characterized in that, At least one drive circuit located in the i-th row is connected to the first sub-data line; At least one drive circuit located in the (i+1)th row is connected to the second sub-data line; 1 i M, where i is an odd number.

20. The display substrate according to claim 13, characterized in that, The t-th power line and the (t+1)-th power line include: the first sub-data line of the t-th data line and the first sub-data line of the (t+1)-th data line, or the second sub-data line of the t-th data line and the second sub-data line of the (t+1)-th data line.

21. The display substrate according to claim 13, characterized in that, The first sub-data line of the j-th data line is located on the side of the j-th power line closest to the (j-1)-th column of the drive circuit, and the second sub-data line of the j-th data line is located on the side of the j-th power line closest to the (j+1)-th column of the drive circuit. The first sub-data line of the (j+1)th data line is located on the side of the (j+1)th power line closest to the (j+2)th column drive circuit, and the second sub-data line of the (j+1)th data line is located on the side of the (j+1)th power line closest to the jth column drive circuit. j N, and j is an odd number.

22. The display substrate according to claim 13, characterized in that, The orthographic projections of the first sub-data line and the second sub-data line onto the substrate at least partially overlap with the orthographic projections of the initial signal line, the reset signal line, the gate line, and the light emission control signal line onto the substrate.

23. The display substrate according to claim 13, characterized in that, The width of the first power supply section is greater than the width of the first sub-data line and also greater than the width of the second sub-data line.

24. The display substrate according to claim 7, characterized in that, For at least one driving circuit, the active layers of all transistors are integrally molded structures. The active layer of the sixth transistor in the driving circuit located in row s and column t is connected to the active layer of the seventh transistor in the driving circuit located in row s+1 and column t; 1 s M, 1 t N and M are the number of rows of the drive circuit, and N is the number of columns of the drive circuit; The active layer protrusion of the driving circuit located in row i and column j+1 is connected to the active layer protrusion of the driving circuit located in row i and column j+2. The active layer protrusion of the driving circuit located in row i+1 and column j is connected to the active layer protrusion located in row i+1 and column j+1. 1 i M, 1 j N, where i and j are odd numbers.

25. The display substrate according to claim 24, characterized in that, The first plate of the capacitor includes: a first side and a second side disposed opposite to each other; for at least one driving circuit, the gate line and the reset signal line are located on the first side of the first plate of the capacitor, the reset signal line is located on the side of the gate line away from the first plate of the capacitor, and the light emission control signal line is located on the second side of the first plate of the capacitor. The first metal layer further includes: the gate electrode of the first transistor to the gate electrode of the seventh transistor, wherein the gate electrode of the first transistor is disposed across the active layer of the first transistor, the gate electrode of the second transistor is disposed across the active layer of the second transistor, the gate electrode of the third transistor is disposed across the active layer of the third transistor, the gate electrode of the fourth transistor is disposed across the active layer of the fourth transistor, the gate electrode of the fifth transistor is disposed across the active layer of the fifth transistor, the gate electrode of the sixth transistor is disposed across the active layer of the sixth transistor, and the gate electrode of the seventh transistor is disposed across the active layer of the seventh transistor. The gate electrode of the first transistor, the gate electrode of the seventh transistor, and the reset signal line are integrally formed; the gate electrode of the second transistor, the gate electrode of the fourth transistor, and the gate line are integrally formed; the gate electrode of the third transistor and the first plate of the capacitor are integrally formed; and the gate electrode of the fifth transistor, the gate electrode of the sixth transistor, and the light emission control signal line are integrally formed.

26. The display substrate according to claim 25, characterized in that, For at least one driving circuit, the first insulating layer, the second insulating layer and the third insulating layer are further provided with a fourth via and a fifth via, and the second insulating layer and the third insulating layer are provided with a seventh via; The fourth via exposes the active layer of the fourth transistor, the fifth via exposes the active layer of the second transistor, the sixth via exposes the active layer of the sixth transistor, and the seventh via exposes the first plate of the capacitor.

27. The display substrate according to claim 26, characterized in that, The third metal layer further includes: the first and second terminals of the first transistor, the first and second terminals of the second transistor, the first terminal of the fourth transistor, the second terminal of the fifth transistor, the second terminal of the sixth transistor, and the first and second terminals of the seventh transistor; For at least one driving circuit, the second electrode of the first transistor and the second electrode of the seventh transistor are integrally formed, and the orthographic projection of the second electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer, the initial signal line and the reset signal line of the seventh transistor on the substrate. The first electrode of the first transistor and the second electrode of the second transistor are integrally formed, and the orthographic projection of the first electrode of the first transistor on the substrate at least partially overlaps with the orthographic projection of the active layer and gate line of the second transistor on the substrate. The second electrode of the sixth transistor and the second electrode of the seventh transistor are integrally formed, and the orthographic projection of the second electrode of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate; The first electrode of the fourth transistor in the driving circuit located in row i is integrally formed with the first sub-data line, and the first electrode of the fourth transistor in the driving circuit located in row i+1 is integrally formed with the second sub-data line. The orthographic projection of the first electrode of the fourth transistor on the substrate and the orthographic projection of the active layer of the fourth transistor on the substrate at least partially overlap.

28. The display substrate according to claim 27, characterized in that, The orthogonal projection of the dummy line of the first pole of the fourth transistor onto the substrate passes through the active layer protrusion.

29. The display substrate according to claim 27, characterized in that, The projection of the second electrode of the second transistor onto the substrate overlaps with the projection of the seventh via onto the substrate. The dummy line of the second terminal of the second transistor passes through the second power supply section.

30. A display device, characterized in that, include: The display substrate as described in any one of claims 1 to 29, and the timing controller, data driver, scan driver, and light-emitting driver; The display substrate includes: data lines, gate lines, and light emission control signal lines; The timing controller is electrically connected to the data driver, the scan driver, and the light-emitting driver, respectively; The data driver is connected to the data line, the scan driver is connected to the gate line, and the light-emitting driver is connected to the light-emitting control signal line.

31. A method for manufacturing a display substrate, characterized in that, The substrate is configured to be used for manufacturing a display substrate as described in any one of claims 1 to 29; Provide a base; An active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer are sequentially formed on the substrate.

Images