A power-on reset circuit

Abstract

The invention provides a power-on reset circuit, comprising a hysteresis voltage generating circuit, a reset signal generating circuit and a sampling delay and discharge circuit; a first PMOS source and one end of a third resistor in the hysteresis voltage generating circuit are connected to a power supply voltage; a first PMOS drain is connected to the other end of the third resistor and one end of a second resistor; the other end of the second resistor is connected to one end of the first resistor; one end of a resistor R0 in the reset signal generating circuit is connected to the power supply voltage; the other end of the resistor R0 is connected to a buffer input end and a first NMOS drain; the sampling delay and discharge circuit comprises one end of a fourth resistor connected to the power supply voltage; the other end of the fourth resistor is connected to a second PMOS source; the second PMOS drain is connected to a second NMOS drain and an upper plate of a capacitor; the other end of the second resistor and one end of the first resistor are connected to a first NMOS gate together; the output end of the buffer is connected to a second PMOS gate, a second NMOS gate and a first PMOS gate; the input end of an inverter is connected to an upper plate of a capacitor; and its output end is a signal output end.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a power-on reset circuit. Background Art

[0002] Power on reset (POR) is an initial application that provides a constant and measurable voltage to a microprocessor or microcontroller. The POR system ensures that the microprocessor or microcontroller starts powering on under the same conditions every time. The present invention attempts to further improve the performance of POR through a new architecture design, making its application more reliable and having a wider range of application areas.

[0003] like Figure 1 As shown, Figure 1 The schematic diagram of the existing POR structure circuit is shown in FIG. The circuit includes a hysteresis voltage generating circuit 40, a reset signal generating circuit 50, and a sampling delay and discharge circuit 60. Basic principle: When the power supply VDD rises, the gate V2 of PM5 follows the power supply voltage to rise, and PM5 is cut off at this time. When the gate voltage VN of the switch tube NM1 reaches its Vth, NM1 is turned on, and the power supply voltage at this time is the upper flip point voltage (Vtrigger rise). After NM1 is turned on, the V1 voltage is pulled down to the ground, and the V2 voltage is pulled down to the ground. At this time, PM6 is turned on, and the capacitor CAP is charged through PM4 and PM6 until the V0 voltage exceeds the Vth of the n-tube in INV, and the RESET signal is pulled low. The time when the RESRT signal is high is called Delay time. When NM1 is turned on, V2 voltage is pulled to ground, PM5 is turned on, and the current through resistor R2 increases, thereby increasing the gate voltage VN of NM1. When the power supply voltage drops, NM1 will be cut off at a power supply voltage lower than the upper flip point voltage. The power supply voltage at this time is called the lower flip point voltage (Vtrigger fall). The purpose of setting the upper and lower flip points is to prevent the RESET signal from being disturbed and unstable due to the jitter near the flip point voltage during the rise and fall of the VDD voltage.

[0004] The advantage of the existing POR structure is that its reset generation circuit, sampling delay and discharge circuit can flexibly adjust the RESET signal pulse width, and can output a RESET signal with a certain pulse width when the power supply is powered off and powered on in a short time. However, the existing POR structure has limitations in being applied to CMOS processes with relatively large threshold voltages and advanced processes with low power supply voltages. Since the flip point voltage of the existing structure is the sum of the threshold voltage Vth of the switch tube NM1 and the source-drain voltage Vds of PM1, that is, Vtrigger=Vthnm1+Vdspm1, when the threshold voltage of NM1 is high, the circuit flip point voltage increases accordingly. Under corner deviation, the power supply may be powered on, but NM1 cannot be turned on, resulting in the circuit RESET function cannot be realized and the circuit fails. In order to ensure that the current mirror works in the saturation region, if PM1 has a minimum Vdspm1 (about 180mV in the 55FG platform), the flip point voltage can be reduced by adjusting the threshold voltage Vth of the switch tube NM1, which is very limited and requires a large area. Therefore, the application scope of the existing POR structure is limited. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power-on reset circuit for solving the problem in the prior art that the power-on reset flip voltage regulation is limited, thereby causing circuit failure.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a power-on reset circuit, comprising at least:

[0007] Hysteresis voltage generating circuit, reset signal generating circuit and sampling delay and discharge circuit; inverter;

[0008] The hysteresis voltage generating circuit comprises: first to third resistors; a first PMOS; a source of the first PMOS and one end of the third resistor are commonly connected to a power supply voltage VDD; a drain of the first PMOS is connected to the other end of the third resistor and one end of the second resistor; the other end of the second resistor is connected to one end of the first resistor;

[0009] The reset signal generating circuit comprises: a resistor R0, a buffer and a first NMOS; one end of the resistor R0 is connected to the power supply voltage VDD; the other end of the resistor R0 is connected to the input end of the buffer and the drain of the first NMOS;

[0010] The sampling delay and discharge circuit comprises: a fourth resistor, a second PMOS, a second NMOS and a capacitor CAP; one end of the fourth resistor is connected to the power supply voltage VDD; the other end of the fourth resistor is connected to the source of the second PMOS; the drain of the second PMOS is connected to the drain of the second NMOS and the upper plate of the capacitor CAP;

[0011] The other end of the second resistor and one end of the first resistor are connected to the gate of the first NMOS; the output end of the buffer is connected to the gate of the second PMOS, the gate of the second NMOS and the gate of the first PMOS;

[0012] The other end of the first resistor, the source of the first NMOS, the source of the second NMOS and the lower plate of the capacitor CAP are grounded in common;

[0013] The input end of the inverter is connected to the upper plate of the capacitor CAP; the output end of the inverter is the signal output end of the power-on reset circuit.

[0014] Preferably, the power supply voltage VDD is divided by the first to third resistors to generate a voltage VN as the gate voltage of the first NMOS; the first NMOS is a switch tube; and the voltage VN=VDD*R1 / (R1+R2+R3); wherein R1, R2, and R3 are the resistance values ​​of the first to third resistors respectively.

[0015] Preferably, when the power supply voltage VDD rises and is lower than a flip voltage of the power-on reset circuit, the first NMOS is turned off.

[0016] Preferably, when the first NMOS is turned off, the first NMOS is used as a resistor with a large resistance, and the resistance of the resistor is much greater than the resistance of the resistor R0.

[0017] Preferably, when the first NMOS is turned on, the first NMOS gate voltage VN is an up-turning voltage; when the first NMOS is turned off, the first NMOS gate voltage VN is a down-turning voltage.

[0018] Preferably, when the power supply voltage VDD is higher than the up-turn voltage, the first NMOS is turned on; the input voltage V2 of the buffer is pulled down; and the first PMOS is turned on to short-circuit the third resistor.

[0019] Preferably, when the power supply voltage VDD gradually decreases, the down-turn voltage is lower than the up-turn voltage, forming a stable hysteresis window voltage.

[0020] Preferably, the second PMOS and the second NMOS respectively control the charging and discharging of the capacitor CAP in sequence.

[0021] Preferably, when the power supply voltage is lower than the down-turn voltage, the second NMOS is turned on; and the input voltage V0 of the inverter is discharged to the ground through the second NMOS.

[0022] As described above, the power-on reset circuit of the present invention has the following beneficial effects: the present invention avoids the problem of limited application of the power-on reset circuit due to changes in the process platform by designing the structure of the power-on reset circuit and only changing the ratio of the voltage-dividing resistor, while still maintaining the advantages of other structures such as flexible adjustment of the delay time. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the existing POR structure circuit;

[0024] Figure 2 Shown is a schematic diagram of the power-on reset circuit structure of the present invention;

[0025] Figure 3 Shown is a simulation diagram of the flip point of the power-on reset circuit structure of the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] The present invention provides a power-on reset circuit, such as Figure 2 As shown, Figure 2 The schematic diagram of the power-on reset circuit structure of the present invention is shown, and the circuit at least includes:

[0029] A hysteresis voltage generating circuit 10, a reset signal generating circuit 20 and a sampling delay and discharge circuit 30; an inverter INV;

[0030] The hysteresis voltage generating circuit 10 includes: first to third resistors (first resistor R1, second resistor R2, third resistor R3); a first PMOS (PM1); a source of the first PMOS (PM1) and one end of the third resistor R3 are commonly connected to a power supply voltage VDD; a drain of the first PMOS (PM1) is connected to the other end of the third resistor R3 and one end of the second resistor R2; the other end of the second resistor R2 is connected to one end of the first resistor R1;

[0031] The reset signal generating circuit 20 includes: a resistor R0, a buffer BUFF and a first NMOS (NM1); one end of the resistor R0 is connected to the power supply voltage VDD; the other end of the resistor R0 is connected to the input end of the buffer BUFF and the drain of the first NMOS (NM1);

[0032] The sampling delay and discharge circuit 30 includes: a fourth resistor R4, a second PMOS (PM2), a second NMOS (NM2) and a capacitor CAP; one end of the fourth resistor R4 is connected to the power supply voltage VDD; the other end of the fourth resistor R4 is connected to the source of the second PMOS (PM2); the drain of the second PMOS (PM2) is connected to the drain of the second NMOS (NM2) and the upper plate of the capacitor CAP;

[0033] The other end of the second resistor R2 and one end of the first resistor R1 are connected to the gate of the first NMOS (NM1); the output end of the buffer BUFF is connected to the gate of the second PMOS (PM2), the gate of the second NMOS (NM2) and the gate of the first PMOS (PM1);

[0034] The other end of the first resistor R1, the source of the first NMOS (NM1), the source of the second NMOS (NM2) and the lower plate of the capacitor CAP are grounded in common;

[0035] The input end of the inverter INV is connected to the upper plate of the capacitor CAP; the output end of the inverter INV is the signal output end RESET of the power-on reset circuit.

[0036] The present invention further comprises that the power supply voltage VDD of this embodiment is divided by the first to third resistors, and the generated voltage VN is used as the gate voltage of the first NMOS; the first NMOS is a switch tube; and the voltage VN=VDD*R1 / (R1+R2+R3); wherein R1, R2, and R3 are the resistance values ​​of the first to third resistors respectively.

[0037] Further, when the power supply voltage VDD rises and is lower than the flip voltage of the power-on reset circuit, the first NMOS is turned off.

[0038] Furthermore, when the first NMOS is turned off, the first NMOS is used as a resistor with a large resistance, and the resistance of the resistor is much greater than the resistance of the resistor R0.

[0039] Further, when the first NMOS is turned on, the first NMOS gate voltage VN is an upward flip voltage; when the first NMOS is turned off, the first NMOS gate voltage VN is a downward flip voltage.

[0040] Further, when the power supply voltage VDD is higher than the up-turn voltage, the first NMOS is turned on; the input voltage V2 of the buffer is pulled down; and the first PMOS is turned on to short-circuit the third resistor.

[0041] Furthermore, when the power supply voltage VDD gradually decreases, the down-turn voltage is lower than the up-turn voltage, forming a stable hysteresis window voltage.

[0042] Furthermore, the second PMOS and the second NMOS respectively control the charging and discharging of the capacitor CAP in sequence.

[0043] Further, when the power supply voltage is lower than the down-turn voltage, the second NMOS is turned on; and the input voltage V0 of the inverter is discharged to the ground through the second NMOS.

[0044] That is, in the hysteresis voltage generating circuit 10, the power supply voltage VDD is divided by resistors R1, R2, and R3 to generate a voltage VN (gate voltage of the first NMOS) as the gate of the switch tube NM1 (first NMOS), VN=VDD*R1 / (R1+R2+R3). When the voltage of the power supply voltage VDD gradually rises (VDD is lower than the flip voltage of the power-on reset circuit POR), the first NMOS (NM1) is in a cut-off state. At this time, NM1 is equivalent to a large resistor, and its resistance is much larger than the resistance of R0. Therefore, the buffer input voltage V2 changes with the power supply voltage VDD; when the power supply voltage VDD is higher than the upper flip point voltage, the first NMOS (NM1) is turned on, the buffer input voltage V2 is pulled down, and the V2 signal outputs the voltage VP through the buffer (BUFF), and VP is pulled down accordingly. VP serves as the gate output of PM1. PM1 is turned on to short-circuit the third resistor R3, and the current flowing through the first resistor R1 and the second resistor R2 increases, thereby increasing the gate voltage VN of the first NMOS. When the power supply voltage VDD gradually decreases, the lower flip point voltage is lower than the upper flip point voltage, thereby forming a stable hysteresis window voltage.

[0045] The first NMOS (NM1) generates a reset signal V2 (the buffer input voltage V2) by determining the voltage of the first NMOS gate voltage VN, and the output voltage VP is adjusted and amplified by the buffer BUFF.

[0046] The second PMOS (PM2) and the second NMOS (NM2) in the sampling delay and discharge circuit 30 respectively control the charging and discharging of the capacitor CAP, and the charging time is adjusted by adjusting the resistance value of the fourth resistor R4 and the resistance value of the capacitor. During the power-on process, VP follows the power-on, NM2 is turned on, the node V0 is pulled down, and the RESET signal is set high; after the power voltage reaches the upper flip point voltage, VP is pulled down, at this time NM2 is turned off and PM2 is turned on, and the capacitor is charged through R4 and PM2, and the V0 voltage gradually increases. When the V0 voltage reaches the turn-on voltage of the n-type MOS tube inside INV, the output RESET signal is set low to complete the power-on reset process. When VDD is lower than the lower flip point voltage, VP follows the power voltage change, NM2 is turned on, and V0 is discharged to the ground through NM2, so that the RESET signal has sufficient delay time when the power rises next time.

[0047] The source end of PM2 is connected in series with a resistor R4 and a capacitor CAP to form a charging circuit, and a single NMOS tube NM2 forms a discharging circuit.

[0048] The present invention adopts a resistor voltage division method to generate a flip point and a hysteresis voltage window. The flip point voltage is the sum of the first NMOS (NM1) threshold voltage Vth and the voltage division of the second resistor R2 and the third resistor R3. The voltage division of the second resistor R2 and the third resistor R3 is VDD*(R2+R3) / (R1+R2+R3), then the upper flip point voltage Vtrigger rise=Vth+VDD*(R2+R3) / (R1+R2+R3). When the threshold voltage of the CMOS tube of the process platform is relatively large (such as the 55FG platform uses a MOS tube with a high voltage Hvt, and the Vt value of the core MOS tube can reach 530mV), or as the process is reduced, the power supply voltage of the advanced process platform is reduced, but the threshold voltage of the MOS tube is not reduced accordingly, the present invention can reduce the flip point voltage value by reducing the ratio of (R2+R3) / (R1+R2+R3), so that the POR can work normally. The flip point voltage is related to the ratio of (R2+R3) / (R1+R2+R3), and the process deviation has little effect on the flip point voltage. In addition, by performing layout matching design on the resistor R0, the first to fourth resistors R1, R2, R3, and R4, the effect of the process deviation on the delay time can be reduced.

[0049] The present invention has been verified by Virtuoso simulation, and it can be found that the present invention can effectively reduce the up and down flip point voltage in a process environment with a high CMOS threshold voltage. The power supply voltage of the POR structure in Table 1 is 1.2V.

[0050]

[0051] Table 1

[0052] Comparing the up and down flip points of the three corner PORs of the two structures in Table 1, it can be seen that: the current mirrors in the existing POR all work under saturation conditions, and the up and down flip points are high. Under the MAX corner, the up flip point reaches 1090mV, which is close to the power supply voltage, and there is a greater risk; the flip point value of the POR structure of the present invention under the MAX corner is 870.5mV, and the voltage of the up flip point is reduced by about 220mV compared with the existing version. Figure 3 As shown, when the VDD voltage is lower than the flip point voltage, the RESET signal follows the power supply voltage; when the VDD voltage is higher than the flip point voltage, the RESET signal is quickly pulled down.

[0053] In summary, the present invention provides a power-on reset structure design, which can flexibly adjust the up and down flip point voltages by changing the resistor voltage division ratio on different process platforms so that the circuit can work normally, and can also adjust the charging current and capacitor capacitance to adjust the RESET signal pulse width. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power-on reset circuit, characterized in that: At least includes: a hysteresis voltage generating circuit, a reset signal generating circuit and a sampling delay and discharge circuit; an inverter; The hysteresis voltage generating circuit comprises: first to third resistors; a first PMOS; a source of the first PMOS and one end of the third resistor are commonly connected to a power supply voltage VDD; a drain of the first PMOS is connected to the other end of the third resistor and one end of the second resistor; the other end of the second resistor is connected to one end of the first resistor; The reset signal generating circuit comprises: a resistor R0, a buffer and a first NMOS; one end of the resistor R0 is connected to the power supply voltage VDD; the other end of the resistor R0 is connected to the input end of the buffer and the drain of the first NMOS; The sampling delay and discharge circuit comprises: a fourth resistor, a second PMOS, a second NMOS and a capacitor CAP; one end of the fourth resistor is connected to the power supply voltage VDD; the other end of the fourth resistor is connected to the source of the second PMOS; the drain of the second PMOS is connected to the drain of the second NMOS and the upper plate of the capacitor CAP; The other end of the second resistor and one end of the first resistor are connected to the gate of the first NMOS; the output end of the buffer is connected to the gate of the second PMOS, the gate of the second NMOS and the gate of the first PMOS; The other end of the first resistor, the source of the first NMOS, the source of the second NMOS and the lower plate of the capacitor CAP are grounded in common; The input end of the inverter is connected to the upper plate of the capacitor CAP; the output end of the inverter is the signal output end of the power-on reset circuit.

2. The power-on reset circuit according to claim 1, characterized in that: The power supply voltage VDD is divided by the first to third resistors to generate a voltage VN as the gate voltage of the first NMOS; the first NMOS is a switch tube; and the voltage VN=VDD*R1 / (R1+R2+R3); wherein R1, R2, and R3 are the resistance values ​​of the first to third resistors respectively.

3. The power-on reset circuit according to claim 1, characterized in that: When the power supply voltage VDD rises and is lower than the flip voltage of the power-on reset circuit, the first NMOS is turned off.

4. The power-on reset circuit according to claim 3, characterized in that: When the first NMOS is turned off, the first NMOS is used as a resistor with a large resistance, and the resistance of the resistor is much greater than the resistance of the resistor R0.

5. The power-on reset circuit according to claim 1, characterized in that: When the first NMOS is turned on, the first NMOS gate voltage VN is an upward flip voltage; when the first NMOS is turned off, the first NMOS gate voltage VN is a downward flip voltage.

6. The power-on reset circuit according to claim 5, characterized in that: When the power supply voltage VDD is higher than the up-turn voltage, the first NMOS is turned on; the input voltage V2 of the buffer is pulled down; and the first PMOS is turned on to short-circuit the third resistor.

7. The power-on reset circuit according to claim 5, characterized in that: When the power supply voltage VDD gradually decreases, the down-turn voltage is lower than the up-turn voltage, forming a stable hysteresis window voltage.

8. The power-on reset circuit according to claim 1, characterized in that: The second PMOS and the second NMOS respectively control the charging and discharging of the capacitor CAP in sequence.

9. The power-on reset circuit according to claim 5, characterized in that: When the power supply voltage is lower than the down-turn voltage, the second NMOS is turned on; and the input voltage V0 of the inverter is discharged to the ground through the second NMOS.

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