Photoresist development using halide chemistries

Abstract

Development of the photoresist can be useful, for example, for forming a patterned mask in the context of high resolution patterning. Development can be accomplished using a halide-containing chemical such as a hydrogen halide. The metal-containing resist film can be deposited on a semiconductor substrate using dry or wet deposition techniques. The photoresist film can be an EUV-sensitive organic metal oxide-containing or organic metal-containing thin film resist. After exposure, the photopatterned metal-containing resist is developed using a wet or dry development.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] The processing of semiconductor devices such as integrated circuits is a multi-step process involving photolithography. Generally, the process includes depositing material on a wafer and patterning the material via photolithography to form structural features (e.g., transistors and circuitry) of the semiconductor device. The steps of a typical photolithography process known in the art include: preparing a substrate; applying a photoresist, such as by spin coating; exposing the photoresist to light in a desired pattern so that the exposed areas of the photoresist become more soluble or less soluble in a developer solution; developing by applying a developer solution to remove the exposed areas of the photoresist, or the unexposed areas; and subsequent processing, such as by etching or material deposition to create features on the substrate areas where the photoresist was removed.

[0004] The evolution of semiconductor design has created a need for, and is driven by the ability to create smaller and smaller features on semiconductor substrate materials. In "Moore's Law," this technological progress is characterized by a doubling of transistor density in dense integrated circuits every two years. Indeed, chip design and manufacturing have advanced to the point where advanced microprocessors may include billions of transistors and other circuit features on a single chip. Individual features on such chips may be on the order of 22 nanometers (nm) or smaller, and in some cases less than 10 nm.

[0005] One challenge in manufacturing devices with such tiny features is the ability to reliably and reproducibly create photolithography masks with sufficient resolution. Current lithography processes typically use 193 nm ultraviolet (UV) light to expose the photoresist. The fact that the wavelength of the light is significantly larger than the desired feature size to be fabricated on the semiconductor substrate creates an inherent problem. Achieving feature sizes smaller than the wavelength of the light requires the use of complex resolution enhancement techniques, such as multiple patterning. Therefore, there is significant interest and research effort in developing lithography techniques that use shorter wavelengths of light, such as extreme ultraviolet (EUV) radiation, which has a wavelength of 10 nm to 15 nm (e.g., 13.5 nm).

[0006] However, EUV lithography processes can present challenges, including low power output and light loss during patterning. Conventional organic chemical amplified resists (CARs), similar to those used in 193 nm UV lithography, have potential disadvantages when used in EUV lithography, particularly because they have low absorption coefficients in the EUV region, and diffusion of the photoactive chemicals can cause blurring and line edge roughness. Furthermore, in order to provide the etch resistance required to pattern the underlying device layers, small features patterned in conventional CAR materials may form high aspect ratios at the risk of pattern collapse. Therefore, there remains a need for improved EUV photoresist materials having properties such as lower thickness, higher absorptivity, and higher etch resistance.

[0007] The background description provided here is for the purpose of generally presenting the background of the present technology. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present technology to the extent that it is described in this background section and in aspects of the specification that could not be determined as prior art at the time the application was filed. Summary of the invention

[0008] The development of the photoresist can be useful, for example, for forming a patterned mask in the context of high resolution patterning. Using certain developing chemicals, the development can selectively remove exposed or unexposed portions of the resist. The developing chemicals can include halides, such as hydrogen halides, or mixtures of hydrogen and halide gases. In some embodiments, the development is a dry development. In some embodiments, the resist is a metal-containing EUV resist that has been photopatterned. In some embodiments, the dry development process is a plasma-free thermal process.

[0009] Disclosed herein are methods and systems for processing semiconductor substrates. The methods for processing semiconductor substrates include providing a photo-patterned metal-containing resist on a substrate layer of a semiconductor substrate in a processing chamber; and developing the photo-patterned metal-containing resist by selectively removing a portion of the resist by exposing the resist to a developing chemistry comprising a halide to form a resist mask.

[0010] In some implementations, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist. In some implementations, the photopatterned metal-containing EUV resist development includes selectively removing the non-EUV exposed portion of the EUV resist relative to the EUV exposed portion using the development chemical to form the resist mask. In some implementations, the development chemical includes hydrogen halide, hydrogen and halogen gas, organic halide, acyl halide, carbonyl halide, sulfinyl halide, or a mixture thereof. In some implementations, the development chemical includes hydrogen fluoride, hydrogen chloride, hydrogen bromide, or hydrogen iodide. In some implementations, by exposing to the development chemical to develop the photopatterned metal-containing resist, it includes being exposed to a dry development chemical to dry develop the photopatterned metal-containing resist. In some implementations, dry developing the photopatterned metal-containing resist includes applying a remote plasma comprising radicals of the halide to the resist. In some implementations, dry developing the photopatterned metal-containing resist is performed at a temperature between -60°C and 120°C, a chamber pressure between 0.1 mTorr and 500 Torr or between about 0.5 Torr and about 760 Torr, and a gas flow rate of the halide between 100 sccm and 2000 sccm, and the etch selectivity of the resist mask is adjustable at least in part based on the temperature, the chamber pressure, the gas flow rate, or a combination thereof. In some implementations, the temperature is between -20°C and 20°C. In some implementations, the photopatterned metal-containing resist includes an element selected from the group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. In some implementations, the method further includes: after developing the photo-patterned metal-containing resist, exposing the photo-patterned metal-containing resist to an inert gas plasma. In some implementations, the method further includes: depositing a metal-containing EUV resist film on the semiconductor substrate; and before providing the photo-patterned metal-containing resist, non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer.

[0011] Disclosed herein is an apparatus for developing a resist. The apparatus includes a processing chamber having a substrate support; a vacuum line coupled to the processing chamber; and a developing chemical line coupled to the processing chamber. The apparatus also includes a controller configured with instructions for processing a semiconductor substrate, the instructions including code for: providing a photo-patterned metal-containing resist on a substrate layer of the semiconductor substrate in the processing chamber; and developing the photo-patterned metal-containing resist by selectively removing a portion of the resist by exposing the resist to a developing chemical including a halide to form a resist mask.

[0012] In some implementations, the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and wherein the controller includes code for selectively removing the non-EUV exposed portion of the EUV resist relative to the EUV exposed portion using the developing chemical to form the resist mask, wherein the controller is configured with instructions. The instructions include code for developing the photo-patterned metal-containing EUV resist. In some implementations, the device also includes one or more heaters coupled to the substrate support, wherein the one or more heaters include a plurality of independently controllable temperature control zones. In some implementations, the interior of the processing chamber is coated with a corrosion inhibitor. In some implementations, the device also includes a condensation trap coupled to the processing chamber, wherein the condensation trap is configured to remove water from the processing chamber. In some implementations, the device also includes a UV lamp or an IR lamp coupled to the processing chamber, wherein the UV lamp or the IR lamp is configured to cure the photo-patterned metal-containing resist or remove excess halides from the processing chamber.

[0013] Disclosed herein is a method for processing a semiconductor substrate. The method includes providing a dry-deposited photo-patterned metal oxide EUV resist on a substrate layer of a semiconductor substrate in a processing chamber; and dry-developing the photo-patterned metal oxide EUV resist by selectively removing non-EUV exposed portions of the EUV resist by exposing the EUV resist to a dry developing chemistry including hydrogen halide to form a resist hard mask from the EUV exposed portions.

[0014] In some implementations, dry development is performed in a plasma-free thermal process, wherein exposure to the dry development chemistry is performed at a temperature between about -20° C. and about 20° C. In some implementations, the photo-patterned metal oxide EUV resist includes an organotin oxide.

[0015] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of an exemplary method for depositing and developing photoresist is presented according to some embodiments.

[0017] Figure 2A-2C Schematic cross-section diagram showing various processing stages of dry development, according to some embodiments.

[0018] Figure 3 An exemplary dry development mechanism is shown in accordance with some embodiments for the chemical reaction of hydrogen bromide (HBr) with exposed and unexposed portions of the EUV resist.

[0019] Figure 4A A schematic cross-sectional view showing dry development without applying an inert gas plasma according to some embodiments.

[0020] Figure 4B A schematic cross-sectional view showing dry development with inert gas plasma cycled to remove residues, according to some embodiments.

[0021] Figure 5 A graph is shown comparing the etch rates between exposed and unexposed portions of EUV photoresist using helium plasma during dry development.

[0022] Fig. 6A and 6B Scanning electron microscope (SEM) images comparing wet development to dry development with respect to line collapse are shown.

[0023] Fig. 7A and 7B SEM images comparing wet development to dry development in terms of controlling roughness and critical dimension (CD) are shown.

[0024] Figure 8 SEM images comparing wet development to dry development with respect to residue after hard mask opening are shown.

[0025] Fig.9A and 9B Graphs are shown that illustrate the effect of a second post-exposure bake operation on the selectivity of dry development at different pressures and temperatures.

[0026] Fig.10 Several SEM images are shown that illustrate the effect of pressure on EUV resist profile.

[0027] Fig.11A and 11BSEM images of EUV resist at different line / space pitches and different thicknesses are shown.

[0028] Fig.12 A schematic diagram of an exemplary processing station for maintaining a low pressure environment suitable for performing developing, cleaning, reprocessing, descumming, and smoothing operations is depicted according to some embodiments.

[0029] Fig.13 A schematic diagram of an exemplary multi-station processing tool suitable for performing the development, cleaning, reprocessing, descumming, and smoothing operations described herein is depicted.

[0030] Fig.14 Shown is a cross-sectional schematic diagram of an exemplary inductively coupled plasma apparatus useful for practicing certain embodiments and operations described herein.

[0031] Fig.15 Depicted is a semiconductor processing cluster tool architecture having a vacuum integrated deposition and patterning module interfaced with a vacuum transfer module suitable for carrying out the processes described herein. DETAILED DESCRIPTION

[0032] The present disclosure relates generally to the field of semiconductor processing. In particular aspects, the present disclosure is directed to processes and apparatus for developing photoresists (e.g., photoresists containing EUV-sensitive metals and / or metal oxides) using halide chemistries, for example to form patterned masks in the context of EUV patterning.

[0033] Reference is made in detail herein to specific embodiments of the present disclosure. Examples of these specific embodiments are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with these specific embodiments, it should be understood that this is not intended to limit the present disclosure to these specific embodiments. On the contrary, it is intended to encompass changes, modifications and equivalents that may be included in the spirit and scope of the present disclosure. In the following narration, many specific details are set forth to provide a thorough understanding of the present disclosure. The present disclosure may be implemented without some or all of these specific details. In other cases, known processing operations are not described in detail to avoid unnecessarily obscuring the present disclosure.

[0034] introduction

[0035] In semiconductor processing, patterning of thin films is often an important step in semiconductor processing. Patterning involves photolithography. In conventional photolithography (e.g., 193nm photolithography), a pattern is printed by emitting photons from a photon source onto a mask and printing the pattern on a light-sensitive photoresist, thereby generating a chemical reaction in the photoresist that removes certain portions of the photoresist after development to form a pattern.

[0036] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include 22nm, 16nm and lower nodes. For example, at the 16nm node, the width of a typical via or line in a damascene structure is typically no greater than about 30nm. Scaling features on advanced semiconductor integrated circuits (ICs) and other devices drives lithography to improve resolution.

[0037] Extreme ultraviolet (EUV) lithography can expand lithography technology by moving to smaller imaging source wavelengths than can be achieved with conventional lithography methods. EUV light sources at wavelengths of about 10-20 nm, or 11-14 nm (e.g., 13.5 nm wavelength) can be used in leading-edge lithography tools, also known as scanners. EUV radiation is strongly absorbed by various solid and fluid materials (including quartz and water vapor) and therefore operates in a vacuum.

[0038] EUV lithography uses a patterned EUV resist to form a mask used in etching the underlying layer. The EUV resist can be a polymer-based chemically amplified resist (CAR) manufactured by a liquid-based spin coating technique. An alternative to CAR is a metal oxide-containing film that can be directly photopatterned, such as those available from Inpria, Corvallis, OR; and those described in U.S. patent applications US 2017 / 0102612, US 2016 / 021660, and US 2016 / 0116839, at least their disclosures on metal oxide-containing films that can be photopatterned are incorporated herein by reference. Such films can be manufactured by spin coating techniques or dry vapor deposition. Metal oxide-containing films can be directly patterned by EUV exposure in a vacuum environment (i.e., without using a separate photoresist) to provide sub-30nm patterning resolution, such as those described in U.S. Patent 9,996,004, issued on June 12, 2018, and entitled “EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS,” and / or in application PCT / US19 / 31618, filed on May 9, 2019, and entitled “METHODS FOR MAKING EUV PATTERNABLE HARD MASKS,” the disclosures of which (which relate at least to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV photoresist masks) are incorporated herein by reference. Generally, patterning involves exposing an EUV resist with EUV radiation to form an optical pattern in the resist, followed by development to remove a portion of the photoresist according to the optical pattern to form a mask.

[0039] It should also be understood that although the present disclosure relates to lithographic patterning techniques and materials using EUV lithography as an example, it can also be applied to other next-generation lithography technologies. In addition to EUV, which includes the standard 13.5nm EUV wavelength in current use and development, the radiation sources most relevant to this lithography are DUV (deep UV), which generally refers to the use of 248nm or 193nm excimer laser sources; X-rays, which formally include EUV at the lower energy range of the X-ray range; and electron beams, which can cover a wide range of energies. These specific methods may depend on the specific materials and applications used in the semiconductor substrate and the final semiconductor device. Therefore, the methods described in this application are merely exemplary methods and materials that can be used in the present technology.

[0040] Directly photopatternable EUV resists may consist of or contain metals and / or metal oxides mixed in an organic component. Metals / metal oxides are very promising because they can enhance the absorptivity of EUV photons and generate secondary electrons, and / or show enhanced etch selectivity for underlying film stacks and device layers. To date, these resists have been developed using wet (solvent) methods that require moving the wafer to a track where the wafer is exposed to a developing solvent, dried, and baked. Wet development not only limits productivity, but can also cause circuit collapse due to surface tension effects and / or delamination.

[0041] Dry development has been proposed to overcome these problems by eliminating substrate peeling and interface failure. Dry development can improve performance (e.g., preventing line collapse caused by surface tension and peeling in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages may include eliminating the use of organic solvent developers, reduced sensitivity to adhesion issues, increased EUV absorption for improved dose efficiency, and no solubility-based limitations. Dry development can also provide more tunability and give further critical dimension (CD) control, as well as scum removal.

[0042] Dry development has its own challenges, including etch selectivity between unexposed and EUV exposed resist materials, which can result in higher dose-to-size requirements for effective resist exposure when compared to wet development. Suboptimal selectivity can also result in PR corner rounding due to longer exposure to etching gases, which can increase CD variation of the lines in subsequent etch transfer steps.

[0043] EUV resist development

[0044] According to various aspects of the present disclosure, a metal-containing photoresist patterned by light is developed by exposure to a halogen-containing chemical. A metal or metal oxide film containing EUV-sensitive, such as an organic tin oxide, is provided on a semiconductor substrate. The EUV-sensitive metal or metal oxide film is directly patterned by EUV exposure in a vacuum environment. Then, the pattern is developed using a developing chemical to form a resist mask. In some embodiments, the developing chemical is a dry developing chemical. In some embodiments, the dry developing chemical includes hydrogen and a halide. This dry developing technique can be accomplished by flowing a dry developing chemical of hydrogen and a halide while using a mild plasma (high pressure, low power) or a thermal treatment. The present disclosure provides a process and apparatus configured to develop a metal-containing resist as part of a resist mask forming process. Various embodiments include vapor deposition, EUV lithography patterning, and dry development to combine all dry operations. Various other embodiments include combinations of wet and dry processing operations, such as spin-on EUV resist (wet processing) combined with dry development, or other wet or dry processing described herein. Various post-deposition (or post-application) processes are also described, such as bevel and backside cleaning, chamber cleaning, descumming, smoothing, and curing to modify and enhance film properties; and rework processes for photoresists.

[0045] Figure 1 A flow chart of an exemplary method for depositing and developing a photoresist is presented according to some embodiments. The operations of process 100 may be performed in a different order, and / or with different, fewer, or additional operations. Aspects of process 100 may be referred to in Figure 2A-2C , Figure 3 and Figure 4A-4B One or more operations of process 100 may be performed using Figure 12-15 In some embodiments, the operations of process 100 may be implemented at least in part according to software stored in one or more non-transitory computer-readable media.

[0046] At block 102 of the process 100, a photoresist layer is deposited. This may be a dry deposition process (eg, a vapor deposition process), or a wet process (eg, a spin-on deposition process).

[0047] The photoresist may be a metal-containing EUV resist. The EUV-sensitive metal or metal oxide film may be deposited on a semiconductor substrate by any suitable technique, including wet (e.g., spin coating) or dry (e.g., CVD) deposition techniques. For example, the process has been demonstrated for EUV photoresist compositions based on organotin oxides, which may be applied in both commercial spin-coatable formulations (e.g., available from Inpria Corp, Corvallis, OR), and formulations applied using dry vacuum deposition techniques, which are further described below.

[0048] The semiconductor substrate may include any material structure suitable for lithography processing (especially suitable for the manufacture of integrated circuits and other semiconductor devices). In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer on which features ("underlying features") have been formed, which has an irregular surface morphology. As mentioned herein, a "surface" is a surface on which the film of the present disclosure is to be deposited, or a surface to be exposed to EUV during processing. The underlying features may include areas in which materials have been removed (e.g., by etching) during processing, or areas in which materials have been added (e.g., by deposition) before the method of the present disclosure is implemented. Such prior processing may include the method of the present disclosure, or other processing methods in iterative processing, by which two or more feature layers are formed on the substrate.

[0049] EUV-sensitive film can be deposited on semiconductor substrate, and this film can be used as the resist for subsequent EUV lithography and processing.The material included in this EUV-sensitive film will change after being exposed to EUV, such as losing the large side chain substituent (pendant substituent) bonded with metal atoms in rich low-density M-OH materials, so that they are crosslinked (crosslink) into the metal oxide material of more compact MOM bonding.Via EUV patterning, the film region that changes physical or chemical properties relative to unexposed regions is produced.These properties are available in subsequent treatment, such as for dissolving unexposed or exposed regions or for selective deposition materials on exposed or unexposed regions.In some embodiments, under the condition of performing this subsequent treatment, unexposed film has a surface more hydrophobic than exposed film, for example, the removal of material can be performed by utilizing the chemical composition, density and crosslinking difference of film.Removal can be carried out by wet treatment or dry treatment, as further described below.

[0050] In various embodiments, the film is an organometallic material, such as an organotin material including tin oxide, or other metal oxide materials / moieties. The organometallic compound can be prepared by reacting an organometallic precursor with a counter-reactant in the gas phase. In various embodiments, the organometallic compound is formed by mixing a specific composition of an organometallic precursor having a large alkyl or fluoroalkyl group with a counter-reactant and polymerizing the mixture in the gas phase to produce a low-density EUV-sensitive material deposited on a semiconductor substrate.

[0051] In various embodiments, the organometallic precursor includes at least one alkyl group on each metal atom that can be retained under gas phase reactions, while other ligands or ions coordinated to the metal atom can be replaced by corresponding reactants. Organometallic precursors include those having the following chemical formula:

[0052] M a R b L c

[0053] (Chemical formula 1)

[0054] Where: M is an element with a high patterned radiation absorption cross section; R is an alkyl group, such as C n H 2n+1 , wherein preferably n≥2; L is a ligand, ion, or other group reactive with the corresponding reactant; a≥1; b≥1; and c≥1.

[0055] In various embodiments, M has a value equal to or greater than 1×10 7 cm 2 / mol atomic absorption cross section. For example, M can be selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, M is tin. R can be fluorinated, for example, having the chemical formula C n F x H (2n+1) In various embodiments, R has at least one β-hydrogen or β-fluorine. For example, R can be selected from the group consisting of ethyl, isopropyl, n-propyl, tert-butyl, isobutyl, n-butyl, sec-butyl, n-pentyl, isopentyl, tert-pentyl, sec-pentyl, and mixtures thereof. L can be any group that is easily substituted by a corresponding reactant to produce an M-OH group, such as a group selected from the group consisting of amines (e.g., dialkylamino, monoalkylamino), alkoxy, carboxylates, halogens, and mixtures thereof.

[0056] The organometallic precursor can be any of a variety of candidate metal-organic precursors. For example, in the case where M is tin, such precursors include tert-butyl tris(dimethylamino)tin, isobutyl tris(dimethylamino)tin, n-butyl tris(dimethylamino)tin, sec-butyl tris(dimethylamino)tin, isopropyl (tri) dimethylamino tin, n-propyl tris(dimethylamino)tin, ethyl tris(dimethylamino)tin, and similar alkyl (tri) (tert-butoxy) tin compounds, such as tert-butyl tris(tert-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0057] The corresponding reactant has the ability to replace reactive groups, ligands, or ions (e.g., L in the above chemical formula 1) to link at least two metal atoms via chemical bonding. The corresponding reactant may include water, peroxides (e.g., hydrogen peroxide), di- or polyols, fluorinated di- or polyols, fluorinated ethylene glycol, and other sources of hydroxyl groups. In various embodiments, the corresponding reactant is reacted with an organometallic precursor by forming an oxygen bridge between adjacent metal atoms. Other possible corresponding reactants include hydrogen sulfide and hydrogen disulfide that can crosslink metal atoms via sulfur bridges.

[0058] In addition to the organometallic precursors and corresponding reactants, the film may also include optional materials to modify the chemical or physical properties of the film, for example to modify the sensitivity of the film to EUV or to improve etch resistance. Such optional materials may be introduced by doping, for example, during vapor phase formation, before deposition on the semiconductor substrate or after deposition of the film (or both). In some embodiments, a mild remote H 2 Plasma to replace some Sn-L bonds with Sn-H, which can improve the reactivity of the resist under EUV.

[0059] In various embodiments, vapor deposition apparatus and processes known in the art are used to fabricate and deposit EUV patternable films on semiconductor substrates. In such processes, polymerized organometallic materials are formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as discontinuous ALD-like processes in which metal precursors and corresponding reactants are separated in time or space.

[0060] In general, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a corresponding reactant to form a polymerized organometallic material; and depositing the organometallic material on the surface of a semiconductor substrate. In some embodiments, more than one organometallic precursor is included in the vapor stream. In some embodiments, more than one corresponding reactant is included in the vapor stream. It will be appreciated by those skilled in the art that in a substantially continuous process, the mixing and deposition aspects of the process can be performed simultaneously.

[0061] In an exemplary continuous CVD process, two or more gas streams of an organometallic precursor and a source of a corresponding reactant located in a separate inlet path are directed to a deposition chamber of a CVD device, where they are mixed in the gas phase and reacted (e.g., via the formation of a metal-oxygen-metal bond) to form an agglomerated polymeric material. The gas stream can be introduced, for example, using a separate injection port or a dual-plenum nozzle. The device is configured to mix the gas streams of the organometallic precursor and the corresponding reactant in the chamber so that the organometallic precursor can react with the corresponding reactant to form a polymerized organometallic material. Without being limited to the mechanism, function, or use of the present technology, it is believed that the product from this gas phase reaction becomes heavier in molecular weight due to the cross-linking of the metal atoms with the corresponding reactants, and is then condensed or otherwise deposited on a semiconductor substrate. In various embodiments, the steric hindrance of large alkyl groups prevents the formation of a densely packed network and produces a smooth, amorphous, and low-density film.

[0062] The CVD process is typically conducted at a reduced pressure, for example, from 10 mTorr to 10 Torr. In some embodiments, the process is conducted at 0.5 Torr to 2 Torr. In some embodiments, the temperature of the semiconductor substrate is equal to or lower than the temperature of the reactant stream. For example, the substrate temperature may be from 0°C to 250°C, or from room temperature (e.g., 23°C) to 150°C. In various processes, deposition of the polymerized organometallic material on the substrate occurs at a rate inversely proportional to the surface temperature.

[0063] In some embodiments, wet deposition apparatus and processes known in the art are used to fabricate and deposit EUV patternable films on semiconductor substrates, for example, by spin coating to form an organometallic material on the surface of a semiconductor substrate.

[0064] The thickness of the EUV patternable film formed on the surface of the semiconductor substrate can be changed according to the surface characteristics, the materials used, and the processing conditions. In various embodiments, the film thickness can be from 0.5nm to 100nm, and can be of sufficient thickness to absorb most of the EUV light under EUV patterning conditions. The EUV patternable film will have the ability to provide an absorptivity equal to or greater than 30%, thereby significantly reducing the EUV photons available toward the bottom of the EUV patternable film. The higher EUV absorptivity causes more crosslinking and densification near the top of the EUV-exposed film compared to the bottom of the EUV-exposed film. Although insufficient crosslinking may cause the resist to peel off or collapse more easily in wet development, this risk does not exist in dry development. The fully dry lithography method can promote the use of EUV photons more efficiently through a less transparent resist film. Although EUV photons can be used efficiently using an EUV patternable film with a higher overall absorptivity, it should be understood that in some cases the EUV patternable film may be less than about 30%. In contrast, the maximum overall absorptivity of most other resist films is less than 30% (e.g., 10% or less, or 5% or less) to fully expose the resist material at the bottom of the resist film. In some embodiments, the film thickness is from 10nm to 40nm, or from 10nm to 20nm. Without being limited to the mechanism, function, or use of the present disclosure, it is believed that the processing of the present disclosure has fewer restrictions on the surface adhesion properties of the substrate, unlike wet spin coating processes in the art, and therefore can be applied to a wide variety of substrates. In addition, as described above, the deposited film can be closely conformal to the surface features to provide advantages in the formation of masks on substrates (e.g., substrates with underlying features) without "filling in" or otherwise flattening such features.

[0065] At box 104, an optional cleaning process is performed to clean the back side and / or bevel edge of the semiconductor substrate. The cleaning of the back side and / or bevel edge can non-selectively etch the EUV resist film to equally remove films with various oxidation or cross-linking degrees on the back side and bevel edge of the substrate. During the process of applying an EUV patternable film by wet deposition or dry deposition, some unexpected resist material deposition may exist on the bevel edge and / or back side of the substrate. The unexpected deposition may cause undesirable particles, which then move to the top surface of the semiconductor substrate and become particle defects. In addition, the deposition of such bevel edge and back side may cause problems in downstream processing, including contamination of patterning (scanner) and development tools. Traditionally, the deposition of such bevel edge and back side is removed by wet cleaning technology. For spin-coated photoresist materials, this process is called edge bead removal (EBR) and is performed by introducing a solvent flow from above and below the bevel edge when the substrate is rotating. The same treatment described can be applied to soluble organotin oxide based resists deposited by vapor deposition techniques.

[0066] The cleaning of the substrate bevel edge and / or backside may also be a dry cleaning process. In some embodiments, the dry cleaning process involves a vapor and field plasma having one or more of the following gases: HBr, HCl, BCl 3 , SOCl 2 , Cl 2 , BBr 3 , H 2 , O 2 、PCl 3 , CH 4 , methanol, ammonia, formic acid, NF 3 , HF. In some embodiments, the dry cleaning process can use the same chemistry as the dry development process described herein. For example, bevel edge and backside cleaning can use hydrogen halide development chemistry. For backside and bevel edge cleaning processes, the vapor and / or plasma must be confined to specific areas of the substrate to ensure that only the backside and bevel edges are removed without degrading any film on the front side of the substrate.

[0067] The processing conditions can be optimized for bevel edge and backside cleaning. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow rate can cause an increase in etch rate. Suitable processing conditions for dry bevel edge and backside cleaning can be: 100-10000 sccm reactant flow rate (e.g., 500 sccm of HCl, HBr, HI, or H 2 and Cl 2 or Br 2 , BCl 3 or H 2), a temperature of 20° C. to 140° C. (e.g., 80° C.), a pressure of 20-1000 mTorr (e.g., 100 mTorr), a plasma power of 0 to 500 W at a high frequency (e.g., 13.56 MHz), and a time of about 10 to 20 seconds, depending on the photoresist film and composition and properties. It should be understood that although these conditions are suitable for use in some process reactors, such as the Kiyo etch tool available from Lam Research Corporation, Fremont, CA, a variety of process conditions may be used depending on the performance of the process reactor.

[0068] For example, when the original photoresist is damaged or has other defects, the dry cleaning operation can be alternatively extended to completely remove the photoresist or "reprocess" the photoresist, wherein the applied EUV resist is removed and the semiconductor substrate is prepared to apply the photoresist again. The reprocessing of the photoresist should be completed without damaging the underlying semiconductor substrate, so oxygen-based etching should be avoided. Alternatively, variants of the halide-containing chemicals described herein can be used. It should be understood that the reprocessing operation of the photoresist can be applied at any stage during the process 100. Therefore, the reprocessing operation of the photoresist can be applied after depositing the photoresist, after cleaning the bevel edge and the back side, after PAB treatment, after EUV exposure, after PEB treatment, or after development. In some embodiments, the reprocessing of the photoresist can be performed for non-selective removal of the exposed and unexposed areas of the photoresist, but with selectivity to the underlying layer.

[0069] In some embodiments, the reprocessing of the photoresist involves vapor and / or plasma with one or more of the following gases: HBr, HCl, HI, BCl 3 , Cl 2 , BBr 3 , H 2 、PCl 3 , CH 4 , methanol, ammonia, formic acid, NF 3 , HF. In some embodiments, the reprocessing of the photoresist can use the same chemistry as the dry development process described herein. For example, the reprocessing of the photoresist can use hydrogen halide development chemistry.

[0070] The processing conditions can be optimized for reprocessing of photoresists. In some embodiments, higher temperatures, higher pressures, and / or higher reactant flows can result in increased etch rates. Depending on the photoresist film and composition and properties, suitable processing conditions for reprocessing of photoresists can be: 100-500 sccm reactant flow rates (e.g., 500 sccm of HCl, HBr, HI, BCl3 or H 2 and Cl 2 or Br 2 ), a temperature of 20 to 140° C. (e.g., 80° C.), a pressure of 20-1000 mTorr (e.g., 300 mTorr), a plasma power of 300 to 800 W (e.g., 500 W) at a high frequency (e.g., 13.56 MHz), 0 to 200 V b The process conditions are described in detail below. The process conditions are described in detail below. The process conditions are described in detail below. The process conditions are described in detail below. The process conditions are described in detail below. A wafer bias of 1000 nm (a higher bias may be used in the case of harder underlying substrate materials) and a time of about 20 seconds to 3 minutes sufficient to completely remove the EUV resist. It should be understood that although these conditions are suitable for use in some process reactors, such as the Kiyo etch tool available from Lam Research Corporation, Fremont, CA, a variety of process conditions may be used depending on the capabilities of the process reactor.

[0071] At block 106 of process 100, an optional post-application bake (PAB) is performed after deposition of the EUV patternable film and before EUV exposure. The PAB process may involve a combination of thermal treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV patternable film, thereby reducing the EUV dose used to develop the pattern in the EUV patternable film. The temperature of the PAB process may be adjusted and optimized to increase the sensitivity of the EUV patternable film. For example, the process temperature may be between about 90° C. and about 200° C., or between about 150° C. and about 190° C. In some embodiments, the PAB process may be performed at a pressure between atmospheric pressure and vacuum, and at a process duration of about 1 to 15 minutes, such as about 2 minutes. In some embodiments, the PAB process may be performed at a temperature between about 100° C. and 200° C. for about 1 minute to 2 minutes.

[0072] At block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to produce a pattern. Generally, the EUV exposure produces changes in the chemical composition and crosslinks in the metal-containing EUV resist film, thereby creating a contrast in etch selectivity that can be exploited in subsequent development.

[0073] Next, the metal-containing EUV resist film can be patterned by exposing the film to EUV light, typically under a relatively high vacuum. EUV equipment and imaging methods useful herein include methods known in the art. In particular, as described above, an exposed region of the film having changed physical or chemical properties relative to an unexposed region is formed by EUV patterning. For example, in the exposed region, cleavage of the metal-carbon bond may occur, for example, via β-hydrogen elimination, leaving a reactive and usable metal hydride functionality that can be converted to a hydroxide and a cross-linked metal oxide group via a metal-oxygen bridge during a subsequent post-exposure bake (PEB) step. This treatment can be used to form a chemical contrast used for developing a negative tone resist. In general, a larger amount of β-hydrogen in the alkyl group will form a more sensitive film. This can also be explained as a weaker Sn-C bonding with more branches. After exposure, the metal-containing EUV resist film can be baked to form additional crosslinks of the metal oxide film. The difference in properties between the exposed and unexposed areas can be exploited in subsequent processing for dissolving the unexposed areas or for depositing material on the exposed areas. For example, a dry process can be used to develop the pattern to form a mask containing a metal oxide.

[0074] In particular, in various embodiments, particularly when the exposure is performed using EUV under vacuum, terminal hydrocarbyl tin oxides present on the surface are converted to terminal hydride tin oxides in the exposed areas of the imaging layer. However, moving the exposed imaging layer from vacuum into air, or the controlled introduction of oxygen, ozone, H 2 O 2 , or water can cause oxidation of Sn-H on the surface to Sn-OH. The difference in properties between the exposed and unexposed areas can be exploited in subsequent processing, for example by reacting one or more reactants with the irradiated areas, the unirradiated areas, or both, to selectively add materials to the imaging layer or remove materials from the imaging layer.

[0075] Not limited to the mechanism, function, or application of this technology, for example, the dose range is 10mJ / cm 2 Up to 100mJ / cm 2 EUV exposure results in cleavage of Sn-C bonds, resulting in a reduction in alkyl substituents, relief of steric hindrance, and collapse of low-density films. In addition, reactive metal-H bonds generated in β-hydrogen elimination reactions can react with neighboring reactive groups (e.g., hydroxyl groups in the film), resulting in further cross-linking and densification, and forming a chemical contrast between exposed and unexposed areas.

[0076] After exposing the metal-containing EUV resist film to EUV light, a photo-patterned metal-containing EUV resist is provided. The photo-patterned metal-containing EUV resist includes EUV exposed and unexposed areas.

[0077] At block 110 of process 100, an optional post-exposure bake (PEB) is performed to further improve the contrast in the etch selectivity of the photo-patterned metal-containing EUV resist. The photo-patterned metal-containing EUV resist may be thermally treated in the presence of various chemicals to promote cross-linking of the EUV exposed areas, or simply baked on a hot plate in ambient air, for example, at between 150° C. and 250° C. for between 1 and 5 minutes (e.g., 190° C. for 2 minutes).

[0078] In various embodiments, the baking strategy involves carefully controlling the baking environment, the introduction of reactive gases, and / or carefully controlling the rate at which the baking temperature is raised or lowered. Examples of useful reactive gases include, for example, air, H 2 O, H 2 O 2 Steam, CO 2 ,CO,O 2 , O 3 , CH 4 , CH 3 OH, N 2 , H 2 NH 3 、N 2 O, NO, alcohol, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB treatment is designed to (1) drive the complete evaporation of organic fragments generated during EUV exposure, and (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure to metal hydroxides, and (3) promote crosslinking between adjacent Sn-OH groups to form more tightly crosslinked SnO-like 2network. The baking temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature will result in insufficient cross-linking and, therefore, a lower chemical contrast for development at a given dose. Too high a PEB temperature can also have adverse effects, including severe oxidation and film shrinkage in unexposed areas (in this example, the areas that are removed by development of the patterned film to form a mask), and undesirable interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlying layer, both of which can lead to a loss of chemical contrast and an increase in defect density due to insoluble residues. The PEB process temperature may be between about 100°C and about 300°C, between about 170°C and about 290°C, or between about 200°C and about 240°C. In some embodiments, the PEB process may be performed at a pressure between atmospheric pressure and vacuum, and a process duration of about 1 to 15 minutes (e.g., about 2 minutes). In some embodiments, the PEB heat treatment may be repeated to further increase the etch selectivity.

[0079] At block 112 of process 100, the photopatterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, the exposed areas (positive tone) are removed, or the unexposed areas (negative tone) are removed. In some embodiments, development may include selective deposition on the exposed or unexposed areas of the photopatterned metal-containing EUV resist, followed by an etching operation. In various embodiments, these processes may be dry processes or wet processes. In some embodiments, development may be accomplished without igniting a plasma. Alternatively, hydrogen and halides (e.g., H) may be activated in a remote plasma source or by exposure to remote UV radiation. 2 and Cl 2 and / or Br 2 ) flow. The photoresist used for development may include an element selected from the group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The element may have a high patterned radiation absorption cross-section. In some embodiments, the element may have a high EUV absorption cross-section. In some embodiments, the metal-containing EUV resist may have an overall absorption rate greater than 30%. In an all-dry lithography process, this provides a more efficient use of EUV photons, thereby enabling the development of thicker and more EUV-opaque photoresists.

[0080] An example of a development process involves subjecting a thin film of EUV-sensitive photoresist containing an organic tin oxide (e.g., 10-30 nm thick, e.g., 20 nm) to an EUV exposure dose and a post-exposure bake, followed by development. The photoresist film may be deposited, for example, based on a vapor phase reaction of an organic tin precursor (e.g., isopropyl(tris)(dimethylamino)tin) and water vapor, or may be a spin-coated film comprising tin clusters in an organic matrix.

[0081] The photopatterned metal-containing EUV resist can be developed by exposure to a developing chemistry, wherein the developing chemistry is a halide-containing chemistry. In some embodiments, the developing chemistry includes hydrogen and a halide, such as a hydrogen halide (e.g., HBr or HCl), or a hydrogen and halogen gas (e.g., H 2 and Cl 2 ). In some embodiments, the developing chemical includes hydrogen halide, hydrogen and halogen gas, boron trichloride, or a combination thereof. The development of the EUV resist can be accomplished by wet development using a halide-containing chemical or dry development using a hydrogen halide-containing chemical. In embodiments where wet development is used to develop the EUV resist, the wet development can be combined with other wet processing operations, such as wet deposition of the metal-containing EUV resist film (e.g., spin-on deposition). Alternatively, the wet development can be combined with other dry processing operations, such as vapor deposition of the metal-containing EUV resist film (e.g., CVD). In embodiments where dry development is used to develop the EUV resist, the dry development can be combined with other dry processing operations, such as dry deposition of the metal-containing EUV resist film (e.g., CVD). In alternative embodiments where dry development is used to develop the EUV resist, the dry development may be combined with other wet processing operations, such as wet deposition (eg, spin-on deposition) of the metal-containing EUV resist film.

[0082] In some embodiments, the processing of the semiconductor substrate can be combined with all dry steps, which include film formation by vapor deposition, EUV lithography patterning, and dry development. In fact, each of the operations 102-112 in the process 100 can be a dry processing operation. This processing operation can avoid the material and production costs associated with wet processing operations (e.g., wet development). Dry processing can provide more adjustability and improve further control of critical dimensions (CD) and the removal of residues. Wet processing usually involves moisture and / or oxygen, which is more likely to cause residue formation. Wet development is limited by solubility and cluster size, but dry development is not limited by solubility and cluster size. Wet development is more likely to cause pattern collapse and peeling problems, while dry development avoids these problems. In addition, using a full dry processing operation can be beneficial for integration in an interconnected vacuum processing chamber without being exposed to ambient air or trace contaminants contained therein and not being contaminated by ambient air or trace contaminants contained therein. For example, a PEB heat treatment during which the exposed areas are further cross-linked may be performed in the same chamber as development; however, it is understood that the PEB heat treatment may be performed in another chamber.

[0083] The development process can be accomplished by delivering the development chemical in a liquid phase or a vapor phase. In some embodiments, the dry development process can be accomplished by using a mild plasma (high pressure, low power) or a thermal process while flowing a dry development chemical containing a hydrogen halide (e.g., HF, HCl, HBr, or HI). For example, dry development can be accomplished in a thermal process using a dry development chemical (e.g., HCl or HBr). In some embodiments, the hydrogen halide-containing chemical is capable of rapidly removing unexposed material, leaving a pattern of exposed film that can be transferred to the underlying layer by a plasma-based etching process (e.g., a known etching process).

[0084] In a thermal development process, a substrate is exposed to a development chemical (e.g., a Lewis acid) in a process chamber (e.g., an oven). In some embodiments, a vacuum line is coupled to the process chamber for controlling the pressure, and a development chemical line may be coupled to the process chamber for delivering the development chemical to the process chamber. The process chamber may include one or more heaters for controlling the temperature, such as coupling a heater to a substrate support within the process chamber for controlling the substrate temperature. In some embodiments, an anti-corrosion film, such as an organic polymer or an inorganic coating, may be applied to the interior of the chamber. One such coating is polytetrafluoroethylene (PTFE), such as Teflon 1M. Such a material may be used in the thermal processes of the present disclosure without the risk of being removed by plasma exposure.

[0085] In a thermal development process, the photopatterned metal-containing EUV resist is exposed to a developing chemical at a temperature that is optimized for etching selectivity between exposed and unexposed areas. Lower temperatures may increase the contrast in etching selectivity, while higher temperatures may reduce the contrast in etching selectivity. In some embodiments, the temperature may be between about -60°C and about 120°C, between about -20°C and about 60°C, or between about -20°C and about 20°C, for example, about -10°C. The chamber pressure may be adjusted, wherein the chamber pressure may affect the etching selectivity between exposed and unexposed areas during development. In some embodiments, the chamber pressure may be relatively low and not accompanied by dilution, wherein the chamber pressure may be between about 0.1mTorr and about 300mTorr, between about 0.2mTorr and about 100mTorr, or between about 0.5mTorr and about 50mTorr. In some embodiments, the chamber pressure may be between about 20mTorr and about 800mTorr, or between about 20mTorr and about 500mTorr, for example, about 300mTorr. In some embodiments, the chamber pressure may be relatively high, with high flow rate and with dilution, wherein the chamber pressure may be between about 100mTorr and about 760mTorr, or between about 200mTorr and about 760mTorr. The reactant flow rate may be adjusted, wherein the reactant flow rate may affect the etching selectivity between the exposed and unexposed areas during development. In some embodiments, the reactant flow rate may be between about 50sccm and about 2000sccm, between about 100sccm and about 2000sccm, or between about 100sccm and about 1000sccm, for example, about 500sccm. In the case of high flow rate, the reactant flow rate may be between about 1L and about 10L. The duration of exposure in the thermal development process may be adjusted. The duration of exposure may depend on, among other factors, how much photoresist needs to be removed, the developing chemistry, the amount of crosslinking in the resist, and the composition and properties of the resist. In some embodiments, the duration of exposure may be between about 5 seconds and about 5 minutes, between about 10 seconds and about 3 minutes, or between about 10 seconds and about 1 minute.

[0086] The thermal development process may expose the photo-patterned metal-containing EUV resist to certain halide-containing chemicals in the gas phase or liquid phase. In some embodiments, the development chemicals include hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, sulfinyl halides, or mixtures thereof. The hydrogen halides may include, but are not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halide may be HCl, or HBr. The hydrogen and halogen gases may include, but are not limited to, hydrogen and halogen gases. 2 , Cl 2Br 2 , or I 2 Mixed hydrogen (H 2 Boron trichloride (BCl 3 ) can be used in combination with any of the aforementioned hydrogen halides or hydrogen and halogen gases. The organic halides may include but are not limited to C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z , wherein x, y, and z are values ​​equal to or greater than 0. Acyl halides may include, but are not limited to, CH 3 COF、CH 3 COCl, CH 3 COBr, and CH 3 COI. Carbonyl halides may include but are not limited to COF 2 、COCl 2 , COBr 2 , and COI 2 The sulfinyl halide may include but is not limited to SOF 2 , SOCl 2 ,SoBr 2 , and SOI 2 In some embodiments, the halide-containing chemical may be flowed with or without an inert / carrier gas such as He, Ne, Ar, Xe, and N 2 .

[0087] Thermal development processing can be done without plasma. Productivity can be significantly improved by using non-plasma thermal methods because multiple wafers can be batch developed simultaneously in a low-cost thermal vacuum chamber / oven. However, in some embodiments, thermal development processing can be followed by exposure to plasma. Subsequent exposure to plasma can be performed for desorption, deslagging, smoothing, or other processing operations.

[0088] In the plasma development process, the photo-patterned metal-containing EUV resist is exposed to a development chemical, which includes free radicals / ions of one or more gases. The processing chamber used to process the semiconductor substrate can be a plasma generation chamber, or coupled to a plasma generation chamber away from the processing chamber. In some embodiments, dry development can be performed by remote plasma. The plasma generation chamber can be an inductively coupled plasma (ICP) reactor, a variable pressure coupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor using equipment and technology known in the art. An electromagnetic field acts on the one or more gases to generate plasma in the plasma generation chamber. Ions and / or radicals from the remote plasma can interact with the photo-patterned metal-containing EUV resist. In some embodiments, a vacuum line is coupled to the processing chamber for controlling pressure, and a development chemical line can be coupled to the plasma generation chamber for delivering the one or more gases to the plasma generation chamber. The processing chamber may include one or more heaters for controlling temperature, such as a heater coupled to a substrate support in the processing chamber for controlling substrate temperature. In some embodiments, the interior of the process chamber may be coated with an anti-corrosion film, such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), such as Teflon 1M. Such materials can be used in the thermal treatment of the present disclosure without the risk of being removed by plasma exposure.

[0089] In the plasma development process, the metal-containing EUV resist that is photopatterned is exposed to a remote plasma under conditions optimized for etching selectivity between exposed and unexposed areas. The conditions may be optimized for producing a mild plasma, wherein the mild plasma may be characterized by high pressure and low power. The chamber pressure may be adjusted, wherein the chamber pressure may affect the etching selectivity between exposed and unexposed areas during development. In some embodiments, the chamber pressure may be equal to or greater than about 5mTorr, or equal to or greater than about 15mTorr. In some embodiments, the chamber pressure may be relatively high, with a high flow rate and accompanied by dilution, wherein the chamber pressure may be between about 100mTorr and about 760mTorr, or between about 200mTorr and about 760mTorr. The RF power level may be adjusted, wherein the RF power may affect etching selectivity, roughness, descumming, and other development characteristics. In some embodiments, the RF power may be equal to or less than about 1000W, equal to or less than about 800W, or equal to or less than about 500W. The temperature can be adjusted, wherein the temperature can affect various aspects of development, such as etching selectivity. In some embodiments, the temperature can be between about -60 ° C and about 300 ° C, between about 0 ° C and about 300 ° C, or between about 30 ° C and about 120 ° C. The gas flow rate can be adjusted, wherein the gas flow rate can affect the etching selectivity between the exposed and unexposed areas during development. In some embodiments, the gas flow rate is between about 50 sccm and about 2000 sccm, between about 100 sccm and about 2000 sccm, or between about 200 sccm and about 1000 sccm, for example, about 500 sccm. The duration of exposure in the plasma development process can be adjusted. The duration of exposure can especially depend on factors such as how much photoresist needs to be removed, the amount of crosslinking in the developing chemicals, the resist, and the composition and properties of the photoresist. In some embodiments, the duration of exposure can be between about 1 second and about 50 minutes, between about 3 seconds and about 20 minutes, or between about 10 seconds and about 6 minutes.

[0090] The plasma development process may expose the photopatterned metal-containing EUV resist to free radicals of certain halide-containing gases. In some embodiments, the free radicals are generated from a remote plasma source. For example, plasma development may expose the photopatterned metal-containing EUV resist to free radicals of hydrogen and halide gases generated from the remote plasma source. In some embodiments, the halide-containing gas includes hydrogen halide, hydrogen and halogen gas, boron trichloride, organic halide, acyl halide, carbonyl halide, sulfinyl halide, or a mixture thereof. Hydrogen halide may include, but is not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide may be HCl or HBr. The hydrogen and halogen gas may include, but is not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide may be HCl or HBr. The hydrogen and halogen gas may include, but is not limited to, hydrogen fluoride (HF) and hydrogen iodide (HI). 2 ), chlorine (Cl 2 ), bromine (Br 2 ), or iodine gas (I 2 ) mixed with hydrogen (H 2 ). The organic halide may include but is not limited to C x H y F z , C x H y Cl z , C x H y Br z and C x H y I z , wherein x, y, and z are values ​​equal to or greater than 0. The acyl halide may include, but is not limited to, CH 3 COF、CH 3 COCl, CH 3 COBr and CH 3 COI. Carbonyl halides may include but are not limited to COF 2 、COCl 2 , COBr 2 and COI 2 The sulfinyl halide may include but is not limited to SOF 2 , SOCl 2 , SOBr 2 and SOI 2 In some embodiments, the halide-containing gas may be flowed with or without an inert / carrier gas such as He, Ne, Ar, Xe, and N 2 .

[0091] In addition or in lieu of plasma activation, activation of one or more gases may be performed in a dry development process by photoactivation. In some embodiments, photoactivation may be achieved by exposure to ultraviolet (UV) radiation. For example, a processing chamber may include a lamp configured to generate UV radiation, such as a UV lamp. Exposing one or more gases to UV radiation may generate free radicals of the one or more gases, which may be used in dry development of the photopatterned metal-containing EUV resist. The one or more gases may be exposed to UV radiation in a manner that does not expose the photopatterned photoresist to UV radiation. In other words, the photopatterned photoresist is outside the range of the UV lamp. Therefore, the UV lamp may be positioned away from the processing chamber or in a manner that avoids exposing the photopatterned photoresist to UV radiation.

[0092] It should be understood that the aforementioned thermal development, plasma development and photoactivated development methods may be combined with each other. These development methods may be applied simultaneously or sequentially. The development method may be applied while flowing a dry development chemical in a liquid phase or a gas phase, wherein the dry development chemical may include a chemical formula R x Z y Compounds wherein R = B, Al, Si, C, S, SO, with x>0, and Z = Cl, H, Br, F, CH 4 And y>0. The development may result in positive or negative tonality, wherein the R x Z y The substance selectively removes unexposed or exposed material, leaving the exposed or unexposed opposing portions to act as a mask.

[0093] As described above, the etch selectivity during dry development is adjustable by controlling the processing conditions, and the processing conditions are, in particular, adjustable processing conditions such as temperature, pressure, gas flow, gas composition, and plasma power. The desired patterning characteristics can be achieved by adjusting the etch selectivity in a single step or multiple steps. In some embodiments, the etch selectivity during dry development is adjusted across one or more steps to affect the EUV resist profile. More specifically, by applying developing chemicals with different etch selectivities during one or more steps, the amount of taper or the re-entrant angle in the EUV resist profile can be controlled. Deslagging, reprocessing of photoresist, curing, smoothing, and cleaning operations can also be adjusted based on the adjustable etch selectivity.

[0094] Figure 2A-2C Schematic cross-section diagram showing various processing stages of dry development, according to some embodiments. Figure 2A-2C The example shown illustrates negative tone dry development. Figure 2A , the wafer 200 includes a substrate 202, and a substrate layer 204 to be etched. In some embodiments, the substrate layer 204 includes an ashing hard mask (e.g., a spin-on carbon SoC) or other materials, such as silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, the substrate layer 204 can be a layer stack disposed on the substrate 202. The wafer 200 also includes a photo-patterned metal-containing EUV resist film 206. For example, the photo-patterned metal-containing EUV resist film 206 can be an organic metal-containing layer disposed above the substrate layer 204 to be etched. The photo-patterned metal-containing EUV resist film 206 can have a thickness between about 5 nm and about 50 nm, or between about 10 nm and about 30 nm. After photo-patterning in an EUV scanner and / or after PEB processing as described above, the photo-patterned metal-containing EUV resist film 206 can be provided in a processing chamber. The photo-patterned metal-containing EUV resist film 206 includes a non-EUV exposed region 206a and an EUV exposed region 206b. Figure 2B As shown in FIG. 1 , the non-EUV exposed area 206a of the photo-patterned metal-containing EUV resist film 206 can be removed in a dry development process by exposing to a flow of dry development chemicals without igniting a plasma. The dry development chemicals may include halide-containing chemicals, such as hydrogen halide or hydrogen and halogen gas. After the development process by removing the non-EUV exposed area 206a, a resist mask 208 is formed. Subsequently, the substrate layer 204 to be etched can be etched using the resist mask 208 to provide Figure 2C The structure depicted in .

[0095] Figure 3 An exemplary dry development mechanism is described in accordance with some embodiments for the chemical reaction of HBr with exposed and unexposed portions of EUV resist. Figure 3 Possible dry development mechanisms are described, however it should be understood that the present disclosure is not limited to any particular mechanism, function, theory, or use. The organic metal oxide film may have a tetrahedral coordinated structure. The exposed areas have a higher degree of Sn-O-Sn crosslinking, resulting in a higher density and lower / slower reactivity to HBr or HCl. The unexposed areas exhibit a lower density due to the presence of large alkyl substituents that hinder access paths and condensation of Sn-OH groups. In the unexposed areas, the hydrogen halide can more easily protonate the more "basic" and accessible oxygen lone pair electrons characteristic of the more tetrahedral coordinated organic tin oxide hydroxide. Volatile byproducts of RSnX3 (wherein X=Cl or Br) can be rapidly generated and removed from the unexposed areas. In Figure 3In the process, HBr selectively protonates the lone pair of oxygen electrons to form a volatile byproduct of R-Sn-Br. Water is also a byproduct. Removing water can increase the reaction rate. When the alkyl group is isopropyl, at least 2 out of every 3 isopropyl groups will be removed under typical EUV patterning doses, resulting in condensation of the exposed areas after the PEB step to form a higher density SnO 2 The tin-like material exhibits a lower reactivity with hydrogen halides due to the adoption of a more hexacoordinated tin structure in which oxygen atoms are less accessible, resulting in a slower reactivity with hydrogen halides. Figure 3 In the embodiment of the present invention, the exposed areas experience a large decrease in dry etch rate, which is related to the reduction of isopropyl groups to allow condensation into a material with more / most oxygen atoms bonded to 3 (rather than 2) tin atoms, thereby significantly reducing the reaction rate with HBr or HCl.

[0096] In some cases, there may be a residue or scum after development. The residue may be caused by slower etching components in less homogeneous EUV resist formulations, including those applied by spin coating techniques. Such residue may contain high metal concentrations, which may be problematic during subsequent pattern transfer.

[0097] Additionally or alternatively, after development, roughness may form on the sidewalls of etched features in the developed pattern. Some of this may be due to the randomness, or non-optimal Gaussian distribution of light, resulting in partially or fully exposed material in areas where the photoresist should remain unexposed, or vice versa.

[0098] In some embodiments, dry development can be achieved by a deslagging / smoothing operation. In some embodiments, the deslagging and smoothing operation can be an inert gas plasma desorption operation. For example, the inert gas plasma desorption operation can be a helium plasma desorption operation. The inert gas plasma desorption operation can be performed after dry development or in a dry development cycle.

[0099] Figure 4A A cross-sectional schematic diagram showing dry development without applying an inert gas plasma according to some embodiments. The photopatterned metal-containing EUV resist film includes exposed and unexposed areas. Figure 4A As shown in the figure, metal oxides (e.g., SnO x) particles or clusters may occupy the unexposed area. As dry development proceeds, the clusters of the metal oxide become more concentrated. The clusters of the metal oxide are generally difficult to remove. Development is selective for the removal of organic materials. After removing the unexposed area, the clusters of the metal oxide may remain on the surface of the substrate as residue. The metal oxide clusters remaining on the sidewalls of the exposed area may cause roughness.

[0100] Figure 4B A cross-sectional schematic diagram of dry development is shown in accordance with some embodiments in the case of circulating an inert gas plasma to remove residues. The first stage involves dry development to remove most of the unexposed areas of the photopatterned metal-containing EUV resist film. Dry development chemicals may include HBr, for example. The majority may represent at least 70% by volume greater than the unexposed area, 80% by volume greater than the unexposed area, or 90% by volume greater than the unexposed area. Clusters of metal oxides are concentrated at the surface of the remaining unexposed areas of the EUV resist film. The second stage involves applying an inert gas plasma (e.g., helium plasma) with low power and high ion energy for a short duration. Helium plasma removes clusters of metal oxides. In addition, helium plasma removes clusters from sidewalls and smoothes sidewalls. Helium plasma treatment may also be used to assist in hardening or curing the patterned EUV resist film to form a tighter metal oxide hard mask. After the helium plasma treatment, a less selective dry etching step may be used to remove any residues retained in the unexposed areas of the EUV resist film.

[0101] In some embodiments, dry development can be cycled with a helium plasma treatment for one or more cycles until the unexposed areas of the EUV resist film are removed. To enhance the effect, helium plasma deslagging / smoothing can be cycled with dry development (as described above). In this manner, for example, most of the organic components of the unexposed areas of the pattern are removed by dry development, and then a brief helium plasma operation can remove some of the concentrated metal at the surface to open up access to the remaining underlying organic material, which can then be removed in a subsequent dry development operation / cycle. Another helium plasma cycle can be used to remove any remaining metal to leave a clean and smooth feature surface. The cycle can continue until all, or substantially all, of the residues and roughness residues are removed to leave a clean and smooth feature surface.

[0102] The processing conditions used for the descumming and smoothing operations can be controlled during or after development. In some embodiments, the reactant flow rate may be between about 50 sccm and about 1000 sccm, or between about 100 sccm and about 500 sccm, for example, about 500 sccm of He. In some embodiments, the temperature may be between about -60°C and about 120°C, between about -20°C and about 60°C, or between about 20°C and about 40°C, for example, about 20°C. In some embodiments, the chamber pressure may be between about 1 mTorr and about 300 mTorr, between about 5 mTorr and about 100 mTorr, between about 5 mTorr and about 20 mTorr, for example, about 10 mTorr. The plasma power may be relatively low with high ion energy. In some embodiments, the plasma power may be between about 50W and about 1000W, between about 100W and about 500W, or between about 100W and about 300W, for example, about 300W. In some embodiments, the wafer bias is between about 10V and about 500V, between about 50V and about 300V, for example, about 200V. High RF frequencies may be used to generate plasma. In some embodiments, the RF frequency is 13.56MHz. The duration of exposure to inert gas plasma may be relatively short to avoid overexposure to UV radiation during plasma exposure. In some embodiments, the duration of exposure is between about 0.5 seconds and about 5 seconds, between about 1 second and about 3 seconds, for example, about 2 seconds.

[0103] The inert gas plasma treatment for descumming and cleaning unexposed resist residues may have the added benefit of curing the exposed photoresist to harden it, thereby enhancing its hard mask function in subsequent operations for etching the underlying substrate. This resist hardening is achieved by exposing the EUV exposed resist to UV radiation generated by the inert gas plasma, which may continue after descumming / smoothing is completed with the bias turned off. If descumming / smoothing is not required or is not performed, an inert gas plasma cure may be performed instead.

[0104] In some embodiments, inert gas plasma desorption descumming and smoothing can be used in conjunction with a wet development process. Wet development is very selective and has been shown to exhibit a distinct on / off behavior, resulting in the wet development process being unable to remove areas exposed by "stray" EUV photons. Then, residual residues are left after the wet development process, resulting in residues, as well as high line edge and width roughness. Interestingly, due to the adjustability of the dry development process (where the etch rate and selectivity can be adjusted based on multiple adjustment knobs (e.g., time, temperature, pressure, gas / flow)), an inert gas plasma and / or dry development can be further applied to descum and smooth the metal-containing resist lines by removing these partially exposed residues.

[0105] Figure 5 A graph is shown comparing the etching rate between exposed and unexposed portions of an EUV resist using helium plasma during dry development. The EUV resist may be an organotin oxide EUV resist. The unexposed portions are etched at a faster rate than the exposed portions. However, as dry development with HBr proceeds, the etching rate slows. Without being bound by any theory, it is believed that the presence of tin oxide particles / clusters slows the etching rate. By applying helium desorption, more of the unexposed portion of the EUV resist can be etched.

[0106] Fig. 6A and 6B SEM images comparing wet development to dry development with respect to line collapse are shown. Fig. 6A In the present invention, the photo-patterned metal-containing EUV resist is exposed to a wet developing chemical, such as an organic solvent. After the liquid drying step, some pattern line collapse is observed. This may be partly attributed to the surface tension effect from the capillary force. Figure 6B In the process, the photo-patterned metal-containing EUV resist is exposed to a dry developing chemical, such as hydrogen halide gas. Dry developing prevents pattern line collapse or peeling through a gas phase reaction without a liquid drying step.

[0107] Fig. 7A and 7B SEM images comparing wet development to dry development in terms of controlling roughness and critical dimension (CD) are shown. Fig. 7A and 7B In the embodiment of the present invention, an organic tin oxide film is deposited on an ashing hard mask. The organic tin oxide film is exposed to EUV at different doses and different depths of focus. Fig. 7A In the present invention, the organic tin oxide film is wet developed, and Figure 7BDry development was performed in . After wet development, the organotin oxide resist mask had a square profile, while after dry development, the organotin oxide resist mask had a tapered profile. In wet development, line bridging was observed after pattern transfer, while line bridging was not observed after pattern transfer in dry development. Due to surface tension during solvent drying after wet development, line collapse and wiggling were observed at smaller line widths or lower doses. After dry development, line collapse or wiggling did not occur at smaller line widths or lower doses. With dry development, a larger process window can be used for a wider dose and focus range.

[0108] Figure 8 SEM images comparing wet development to dry development with respect to residue after hard mask opening are shown. Figure 8 As shown, more residue was observed after wet development than after dry development. Without being bound by any theory, dry development uses a gas chemistry that does not contain oxygen or moisture oxidation sources, which prevents metal oxide crosslinking of the unexposed EUV resist, thereby preventing residue formation. The residue is similar to the exposed EUV resist with metal oxide crosslinking. Figure 8 In the present invention, descumming and smoothing operations may be performed after wet development or dry development.

[0109] Fig.9A and 9B Several graphs are shown that illustrate the effect of the second post-exposure bake on the selectivity of dry development at different pressures and temperatures. Fig.9A As shown, the second post-exposure bake exhibits improved etch selectivity. Fig. 9B It is shown that during dry development, etch selectivity improves at lower temperatures. In addition, during dry development, etch selectivity improves at lower pressures.

[0110] Fig.10 Multiple SEM images are shown that illustrate the effect of pressure on EUV resist profile. For dry development, pressure changes affect EUV resist profile. Generally speaking, higher pressures enable higher etch rates. However, lower pressures exhibit improved EUV resist profiles. Fig.10 Lower pressures in the process result in straighter EUV resist profiles.

[0111] Fig.11A and 11BSEM images of EUV resist at different line / space pitches and different thicknesses are shown. The EUV resist mask was developed to have a 32nm pitch and a 26nm pitch. The film thickness before development was between 15nm and 40nm. For the 32nm pitch, after development, the thickness of the EUV resist mask was in the range of 7.8nm and 22.5nm. No swing was observed. For the 26nm pitch, after development, the thickness of the EUV resist mask was in the range of 7.9nm and 22.2nm. Due to the undercut at the bottom of the resist, some swing was observed for film thicknesses equal to or greater than 30nm.

[0112] Device

[0113] The apparatus of the present disclosure is configured to develop EUV resist. The apparatus may be configured to perform other processing operations, such as deposition, bevel and backside cleaning, post-application baking, EUV scanning, post-exposure baking, photoresist reprocessing, residue removal, smoothing, curing, and other operations. In some embodiments, the apparatus is configured to perform all dry operations. In some embodiments, the apparatus is configured to perform all wet operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus may include a single wafer chamber or multiple stations located in the same processing chamber. Using multiple stations located in the same processing chamber, various processing operations such as those described in the present disclosure may be performed in different stations located in the same processing chamber. For example, PEB heat treatment may be performed in one station and developed in another station.

[0114] The device configured for developing EUV resist includes a processing chamber with a substrate support. The device may include a vacuum line coupled to the processing chamber for controlling pressure and a developing chemical line coupled to the processing chamber for conveying developing chemicals. In some embodiments, the developing chemical includes a halide-containing gas or a free radical containing a halide gas. In some embodiments, the processing chamber is a plasma generating chamber or is coupled to a plasma generating chamber operated as a remote plasma source. The plasma generating chamber may be an ICP, TCP, or CCP reactor. The device may include one or more heaters for controlling temperature. Such a heater may be arranged in the processing chamber and / or in the substrate support.

[0115] In some embodiments, the interior of the processing chamber is coated with an anti-corrosion film, such as a polymer or inorganic coating. In one example, the interior of the processing chamber is coated with anodized aluminum oxide. In another example, the interior of the processing chamber is coated with yttrium oxide (Y 2 O 3 ).

[0116] In some embodiments, the processing chamber is made of an inexpensive material such as plastic. The processing chamber need not be made of metal or ceramic. The plastic material may be sufficient to withstand halide-containing chemicals during development. Vacuum lines and / or development chemical lines may be coupled to the plastic chamber.

[0117] In some embodiments, a substrate support can be used to process a substrate using a temperature profile having radial and azimuthal components. The substrate support can include a plurality of independently controllable temperature control zones arranged near the substrate position above the temperature control zones. This allows one or more heaters within the substrate support to more accurately and locally control the temperature. The temperature control zones can be arranged in a defined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern for producing a desired temperature distribution. In some embodiments, the temperature control zones can be spatially arranged in an electrostatic chuck to correct for azimuthal non-uniformity or local CD non-uniformity.

[0118] In some embodiments, the apparatus may further include a showerhead for delivering one or more gases into the processing chamber. In some embodiments, the showerhead may supply a plurality of different gases to the reaction area while keeping these gases largely isolated within the showerhead. The showerhead may include a plurality of gas chamber volumes. This enables, among other things, the isolation of chemicals such as precursor gases, carrier gases, developer gases, and purge gases.

[0119] Removing water or moisture from the process chamber can accelerate the reaction of the photo-patterned metal-containing EUV resist with the developing chemicals. In some embodiments, a cold trap can be coupled to the process chamber for removing water vapor byproducts. The cold trap can condense the water vapor byproducts into a liquid or solid form.

[0120] In some embodiments, the apparatus may further include a UV source (e.g., a UV lamp) and / or an IR source (e.g., an IR lamp) for resist curing and dehalogenation. The UV source and / or the IR source may provide exposure to radiation to cure the EUV resist. Additionally or alternatively, the UV source may assist in photoactivation of the developer chemicals. Additionally or alternatively, the UV source may assist in removing halogens. Halogen residues may form on the semiconductor substrate or chamber surface and may be removed by UV exposure.

[0121] Fig.12 A schematic diagram of an embodiment of a processing station 1200 is depicted, having a processing chamber body 1202 for maintaining a low pressure environment suitable for performing the described embodiments of dry developing, cleaning, reprocessing, deslagging and smoothing. Multiple processing stations 1200 may be included in a common low pressure processing tool environment. For example, Fig.13An embodiment of a multi-station processing tool 1300 is depicted, such as the 1300 commercially available from Lam Research Corporation (Fremont, CA). Processing Tools. In some embodiments, one or more hardware parameters of the processing station 1200 (including those discussed in detail below) may be programmatically adjusted by one or more computer controllers 1250.

[0122] The processing stations can be configured as modules in a cluster tool. Fig.15 A semiconductor processing cluster tool architecture with vacuum integrated deposition and patterning modules suitable for performing the embodiments described herein is depicted. Such a cluster processing tool architecture may include resist deposition, resist exposure (EUV scanner), resist development, and etching modules, as described above and below with reference to Fig.14 and 15 Further description.

[0123] In some embodiments, some processing functions may be performed serially in the same module, such as dry development and etching. Embodiments of the present disclosure relate to methods and apparatus for receiving a wafer (including a photo-patterned EUV resist film layer disposed on a layer or layer stack to be etched) into a dry development / etch chamber after photo-patterning in an EUV scanner; dry developing the photo-patterned EUV resist film layer; and then etching the underlying layer using the patterned EUV resist as a mask, as described herein.

[0124] Back to Fig.12 , the processing station 1200 is in fluid communication with a reactant delivery system 1201a for delivering the process gas to the distribution showerhead 1206. The reactant delivery system 1201a optionally includes a mixing vessel 1204 for mixing and / or conditioning the process gas for delivery to the showerhead 1206. One or more mixing vessel inlet valves 1220 can control the introduction of the process gas to the mixing vessel 1204. When plasma exposure is used, plasma can also be delivered to the showerhead 1206 or can be generated in the processing station 1200. As described above, in at least some embodiments, non-plasma thermal exposure is advantageous.

[0125] Fig.12An optional vaporization point 1203 is included for vaporizing liquid reactants to be supplied to a mixing vessel 1204. In some embodiments, a liquid flow controller (LFC) may be provided upstream of the vaporization point 1203 to control the mass flow rate of liquid for vaporization and delivery to the processing station 1200. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller (electrically connected to the MFM).

[0126] The showerhead 1206 distributes the process gas toward the substrate 1212. Fig.12 In the illustrated embodiment, substrate 1212 is positioned below showerhead 1206 and is shown resting on pedestal 1208. Showerhead 1206 may have any suitable shape and may have any suitable number and configuration of ports to distribute process gases to substrate 1212.

[0127] In some embodiments, the pedestal 1208 can be raised or lowered to expose the substrate 1212 to the volume between the substrate 1212 and the showerhead 1206. It should be appreciated that in some embodiments, the pedestal height can be programmatically adjusted via a suitable computer controller 1250. In some embodiments, the showerhead 1206 can have multiple plenum volumes, along with multiple temperature controls.

[0128] In certain embodiments, the susceptor 1208 can be temperature controlled by a heater 1210. In some embodiments, during non-plasma thermal exposure of the photo-patterned resist to a hydrohalide dry developing chemistry (e.g., HBr or HCl), the susceptor 1208 can be heated to a temperature greater than 0° C. and up to 300° C. or higher, such as 50 to 120° C., such as about 65 to 80° C., as described in the disclosed embodiments. In some embodiments, the heater 1210 of the susceptor 1208 can include multiple independently controllable temperature control zones.

[0129] Additionally, in some embodiments, pressure control for process station 1200 may be provided by butterfly valve 1218. Fig.12 In the embodiment shown in FIG. 1 , butterfly valve 1218 regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 1200 can also be regulated by changing the flow rate of one or more gases introduced into process station 1200.

[0130] In some embodiments, the position of the showerhead 1206 can be adjusted relative to the pedestal 1208 to change the volume between the substrate 1212 and the showerhead 1206. In addition, it should be understood that the vertical position of the pedestal 1208 and / or the showerhead 1206 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1208 can include a rotation axis for rotating the orientation of the substrate 1212. It should be understood that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more appropriate computer controllers 1250.

[0131] When plasma may be used, such as in a mild plasma-based dry development embodiment and / or an etching operation performed in the same chamber, the showerhead 1206 and the pedestal 1208 are electrically connected to a radio frequency (RF) power source 1214 and a matching network 1216 to provide power to the plasma. In some embodiments, the energy of the plasma can be controlled by controlling one or more of the pressure of the processing station, the concentration of the gas, the RF source power, the RF source frequency, and the timing of the plasma power pulses. For example, the RF power source 1214 and the matching network 1216 can be operated at any suitable power to form a plasma having a desired composition of free radical species. Examples of suitable powers are up to about 500W.

[0132] In some embodiments, instructions for the controller 1250 may be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting conditions for a process stage may be included in a corresponding recipe stage of a process recipe. In some cases, the process recipe stages may be arranged in sequence so that all instructions for a process stage are executed simultaneously with the process stage. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe stage. For example, instructions for setting the flow rate of a dry developer chemical reactant gas (e.g., HBr or HCl), and time delay instructions for a recipe stage. In some embodiments, the controller 1250 may include the following instructions regarding Fig.13 any features of the system controller 1350.

[0133] As described above, one or more processing stations may be included in a multi-station processing tool. Fig.13A schematic view of an embodiment of a multi-station processing tool 1300 is shown, which has an inbound load lock 1302 and an outbound load lock 1304, one or both of which may include a remote plasma source. A robot 1306 at atmospheric pressure is configured to move a wafer from a box loaded by a cabin 1308 into the inbound load lock 1302 via an atmospheric port 1310. The wafer is placed on a pedestal 1312 in the inbound load lock 1302 by the robot 1306, the atmospheric port 1310 is closed, and the load lock is evacuated. When the inbound load lock 1302 includes a remote plasma source, the wafer can be exposed to a remote plasma treatment in the load lock to treat the silicon nitride surface before being introduced into a processing chamber 1314. In addition, the wafer can also be heated in the inbound load lock 1302, for example to remove moisture and adsorbed gases. Next, the chamber transfer port 1316 leading to the process chamber 1314 is opened and another robot (not shown) places the wafer into the reactor on a susceptor at the first station shown in the reactor for processing. Fig.13 The embodiment depicted in FIG. 1 includes a load lock, but it should be understood that in some embodiments, substrates may be allowed to enter the processing station directly.

[0134] The depicted processing chamber 1314 contains 4 processing stations, Fig.13 In the embodiment shown, numbering is 1 to 4. Each station has a heated base (shown as 1318 for station 1) and a gas pipeline inlet. It should be understood that in some embodiments, each processing station can have different or multiple uses. For example, in some embodiments, the processing station can be switchable between dry development and etching processing modes. Additionally or alternatively, in some embodiments, the processing chamber 1314 can include one or more matching pairs of dry development and etching processing stations. Although the processing chamber 1314 depicted includes 4 stations, it is understood that the processing chamber according to the present disclosure can have any appropriate number of stations. For example, in some embodiments, the processing chamber can have 5 or more stations, while in other embodiments, the processing chamber can have 3 or less stations.

[0135] Fig.13 Some embodiments of a wafer handling system 1390 for transferring wafers within the processing chamber 1314 are depicted. In some embodiments, the wafer handling system 1390 can transfer wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be used. Non-limiting examples include a wafer turntable and a robot for handling wafers. Fig.13Also depicted is an embodiment of a system controller 1350 employed to control processing conditions and hardware states of the processing tool 1300. The system controller 1350 may include one or more memory devices 1356, one or more mass storage devices 1354, and one or more processors 1352. The processor 1352 may include a computer or CPU, analog and / or digital input / output connections, a stepper motor controller board, and the like.

[0136] In some embodiments, the system controller 1350 controls all activities of the processing tool 1300. The system controller 1350 executes system control software 1358 stored in the mass storage device 1354, loaded into the memory device 1356, and executed by the processor 1352. Alternatively, the control logic can be hard-coded in the controller 1350. Application-specific integrated circuits, programmable logic devices (such as field programmable gate arrays, or FPGAs), etc. can be used for these purposes. In the following discussion, whether "software" or "code" is used, functionally equivalent hard-coded logic can be used instead. The system control software 1358 can include instructions for controlling timing, mixing of gases, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperatures, target power levels, RF power levels, substrate pedestals, chuck and / or pedestal positions, and other parameters of the specific process performed by the processing tool 1300. The system control software 1358 can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components for performing various process tool processes.The system control software 1358 may be coded in any suitable computer readable programming language.

[0137] In some embodiments, the system control software 1358 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs associated with the system controller 1350 and stored in the mass storage device 1354 and / or the memory device 1356 may be employed in some embodiments. Examples of programs or program segments for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0138] The substrate positioning program may contain program code for processing tool components used to load a substrate onto the pedestal 1318 and control the spacing between the substrate and other parts of the processing tool 1300.

[0139] The process gas control program may include code for controlling the halogen-containing gas composition (e.g., HBr or HCl gas as described herein) and flow rate and optionally code for flowing the gas into one or more process stations prior to deposition to stabilize the pressure in the process station. The pressure control program may include code for controlling the pressure within the process station by adjusting, for example, a throttle valve in the exhaust system of the process station, gas flow into the process station, and the like.

[0140] The heater control program may contain code for controlling the flow of current to a heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) toward the substrate.

[0141] A plasma control program may include code for setting RF power levels applied to process electrodes within one or more process stations according to embodiments herein.

[0142] The pressure control program may include code for maintaining the pressure within the reaction chamber according to embodiments herein.

[0143] In some embodiments, there may be a user interface associated with the system controller 1350. The user interface may include a display screen, a graphical software display of apparatus and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, and the like.

[0144] In some embodiments, the parameters adjusted by the system controller 1350 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of a recipe, which may be entered using the user interface.

[0145] Signals for monitoring the process may be provided from various process tool sensors by analog and / or digital input connections of the system controller 1350. Signals for controlling the process may be output via analog and digital output connections of the process tool 1300. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain process conditions.

[0146] The system controller 1350 may provide program instructions for performing the above-described deposition processes. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control these parameters to operate dry development and / or etching processes according to various embodiments described herein.

[0147] The system controller 1350 will typically include one or more memory devices and one or more processors configured to execute instructions so that the apparatus will perform the methods described in accordance with the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations in accordance with the disclosed embodiments may be coupled to the system controller 1350.

[0148] In some embodiments, the system controller 1350 is part of a system that can be part of the above-described embodiments. Such a system can include a semiconductor processing device that includes one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operations before, during, and after processing semiconductor wafers or substrates. The electronic device can be referred to as a "controller" that can control various elements or subcomponents of one or more systems. Depending on the type of processing requirements and / or system, the system controller 1350 can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out tools and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0149] In broad terms, the system controller 1350 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. The integrated circuit may include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions transmitted to the system controller 1350 in the form of various separate settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer for completing one or more processing steps during the preparation of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0150] In some embodiments, the system controller 1350 can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to, or a combination of the system. For example, the system controller 1350 can be in the "cloud" or all or part of a wafer fab host system, thereby allowing remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance standards for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some embodiments, a remote computer (e.g., a server) can provide a processing recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some embodiments, the system controller 1350 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be for the type of process to be performed and the type of tool to which the system controller 1350 is configured to connect or control the tool type. Thus, as described above, the system controller 1350 can be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common goal (e.g., the processing and control described herein). An embodiment of a distributed controller for these purposes can be one or more integrated circuits on the chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control the processing within the chamber.

[0151] Without limitation, example systems may include plasma etching chambers or modules, deposition chambers or modules, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, development chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0152] As described above, depending on one or more processing steps to be performed by the tool, the system controller 1350 can communicate with one or more other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to move containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0153] An inductively coupled plasma (ICP) reactor is now described, which may be suitable for use in etching operations in certain embodiments, and etching processes are suitable for use in the practice of certain embodiments. Although an ICP reactor is described herein, it should be understood that a capacitively coupled plasma reactor may also be used in some embodiments.

[0154] Fig.14 1400 is schematically shown in cross-section, and is suitable for practicing certain embodiments or aspects of embodiments (eg, dry developing and / or etching), an example of which is manufactured by Lam Research Corp., Fremont, CA. Reactor. In other embodiments, other tools or tool types having the functionality to perform the dry developing and / or etching processes described herein may be used to implement the protocols.

[0155] The inductively coupled plasma device 1400 includes a main processing chamber structurally defined by a chamber wall 1401 and a window 1411. The chamber wall 1401 may be made of stainless steel, aluminum, or plastic. The window 1411 may be made of quartz, or other dielectric materials. An optional internal plasma grid 1450 divides the main processing chamber into an upper sub-chamber 1402 and a lower sub-chamber 1403. In most embodiments, the plasma grid 1450 may be removed, thereby utilizing the chamber space formed by both the sub-chambers 1402 and 1403. A chuck 1417 is positioned in the lower sub-chamber 1403 near the bottom inner surface. The chuck 1417 is configured to receive and hold a semiconductor wafer 1419 on which etching and deposition processes are performed. The chuck 1417 may be an electrostatic chuck for supporting the wafer 1419 when the wafer 1419 is present. In some embodiments, an edge ring (not shown) surrounds the chuck 1417 and has an upper surface that is substantially coplanar with the top surface of the wafer 1419 (when the wafer is present above the chuck 1417). The chuck 1417 also includes electrostatic electrodes for clamping and unclamping the wafer. Filters and DC clamp power sources (not shown) may be provided for this purpose. Other control systems may also be provided for lifting the wafer 1419 off the chuck 1417. The chuck 1417 may be charged with an RF power source 1423. The RF power source 1423 is connected to the matching circuit 1421 through the connector 1427. The matching circuit 1421 is connected to the chuck 1417 through the connector 1425. In this manner, the RF power source 1423 is connected to the chuck 1417. In various embodiments, the bias power supply of the electrostatic chuck may be set to about 50V, or to a different bias power supply depending on the process performed according to the disclosed embodiments. For example, the bias power supply may be between about 20Vb and about 100V, or between about 30V and about 150V.

[0156] Elements for plasma generation include a coil 1433 located above window 1411. In some embodiments, no coil is used in the disclosed embodiments. Coil 1433 is made of a conductive material and includes at least one full turn. Fig.14 The example of the coil 1433 shown in includes three turns. The cross-section of the coil 1433 is shown with symbols, and the coil with the "X" symbol indicates that the coil extends rotationally into the page, and conversely, the coil with the "●" symbol indicates that the coil extends rotationally out of the page. The element for plasma generation also includes an RF power supply 1441 configured to provide RF power to the coil 1433. Generally, the RF power supply 1441 is connected to the matching circuit 1439 through the connector 14414. The matching circuit 1439 is connected to the coil 1433 through the connector 1443. In this way, the RF power supply 1441 is connected to the coil 1433. An optional Faraday shield 1449a is positioned between the coil 1433 and the window 1411. The Faraday shield 1449a can be maintained in a spaced relationship relative to the coil 1433. In some embodiments, the Faraday shield 1449a is disposed directly above the window 1411. In some embodiments, the Faraday shield 1449b is between the window 1411 and the chuck 1417. In some embodiments, the Faraday shield 1449b is not maintained in a spaced relationship with the coil 1433. For example, the Faraday shield 1449b can be directly below the window 1411 without a gap. Each of the coil 1433, the Faraday shield 1449a, and the window 1411 is configured to be substantially parallel to each other. The Faraday shield 1449a can prevent metal or other substances from being deposited on the window 1411 of the processing chamber 1424.

[0157] The processing gas can flow into the processing chamber through one or more main gas inlets 1460 and / or through one or more side gas inlets 1470 located in the upper sub-chamber 1402. Similarly, although not explicitly shown, similar gas inlets can be used to supply processing gas to the capacitively coupled plasma processing chamber. A vacuum pump, for example, a one-stage or two-stage dry mechanical pump and / or a turbomolecular pump 1440, can be used to extract the processing gas from the processing chamber 1424 and maintain the pressure in the processing chamber 1400. For example, the vacuum pump can be used to evacuate the lower sub-chamber 1403 during the ALD cleaning operation. A valve-controlled conduit can be used to connect the vacuum pump fluid to the processing chamber 1424 so as to selectively control the application of the vacuum environment provided by the vacuum pump. During the operation of the plasma treatment process, this can be performed using a closed loop controlled flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown). Similarly, a vacuum pump and a valve that are controlled to be fluidly connected to the capacitively coupled plasma processing chamber can also be used.

[0158] During operation of the device 1400, one or more process gases may be supplied through the gas inlet 1460 and / or 1470. In certain embodiments, the process gas may be supplied only through the main gas inlet 1460, or only through the side gas inlet 1470. In some cases, the gas inlet shown in the figure may be replaced by a more complex gas inlet, such as one or more nozzles. The Faraday shield 1449 and / or the optional grid 1450 may include internal channels and holes that enable the process gas to be delivered to the chamber. One or both of the Faraday shield 1449 and the optional grid 1450 may serve as a nozzle for delivering the process gas. In some embodiments, the liquid evaporation and delivery system may be located upstream of the processing chamber 1424 so that once the liquid reactant or precursor is evaporated, the evaporated reactant or precursor is introduced into the chamber through the gas inlet 1460 and / or 1470.

[0159] RF power is supplied from the RF power supply 1441 to the coil 1433 to cause an RF current to flow through the coil 1433. The RF current flowing through the coil 1433 generates an electromagnetic field around the coil 1433. The electromagnetic field generates an induced current in the upper sub-chamber 1402. The physical and chemical interactions of the generated ions and radicals with the wafer 1419 etch features of the wafer and selectively deposit layers on the wafer 1419.

[0160] If a plasma grid 1450 is used so that both an upper sub-chamber 1402 and a lower sub-chamber 1403 exist, the induced current acts on the gas present in the upper sub-chamber 1402 to produce an electron-ion plasma in the upper sub-chamber 1402. The optional internal plasma grid 1450 limits the amount of hot electrons in the lower sub-chamber 1403. In some embodiments, the device 1400 is designed and operated so that the plasma present in the lower sub-chamber 1403 is an "ion-ion" plasma.

[0161] Both the upper electron-ion plasma and the lower ion-ion plasma may contain cations and anions, but the ion-ion plasma will have a greater ratio of anions to cations. Volatile etching and / or deposition byproducts may be removed from the lower sub-chamber 1403 through port 1422. The chuck 1417 disclosed herein may operate within an elevated temperature range between about 10° C. and about 250° C. The temperature will depend on the processing operation and the specific recipe.

[0162] The apparatus 1400 can be coupled to facilities (not shown) when installed in a clean room or manufacturing plant. Such facilities include piping that provides process gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to the apparatus 1400 when installed in the target manufacturing plant. In addition, the apparatus 1400 can be coupled to a transfer chamber, thereby allowing semiconductor wafers to be transferred into and out of the apparatus 1400 by a robot using, for example, typical automation.

[0163] In some embodiments, a system controller 1430 (which may include one or more physical or logical controllers) controls some or all of the operations of the process chamber 1424. The system controller 1430 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 1400 includes a switching system for controlling flow rate and duration when performing the disclosed embodiments. In some embodiments, the apparatus 1400 may have a switching time of up to about 500 ms or up to about 750 ms. The switching time may depend on the flow chemical composition, recipe selection, reactor architecture, and other factors.

[0164] In some embodiments, the system controller or controller 1430 is part of a system, which can be part of the above examples. Such a system can include semiconductor processing equipment, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. Electronic devices can be integrated into controller 1430, which can control various components or subcomponents of one or more systems. Depending on the processing parameters and / or system type, the system controller can be programmed to control any of the processes disclosed herein, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer delivery to and from tools and other delivery tools and / or load locks connected to a specific system or interfaced with a specific system.

[0165] Broadly speaking, the controller 1430 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions delivered to the controller in the form of various separate settings (or program files) that define operating parameters for performing specific processing on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0166] In some embodiments, the system controller 1430 can be a part of or coupled to a computer that is integrated with the system, coupled, otherwise networked to the system or a combination thereof. For example, the controller can be in the "cloud" or in all or part of a wafer factory (fab) host system, which can allow remote access to wafer processing. The computer can implement remote access to the system to monitor the current progress of manufacturing operations, check the history of past manufacturing operations, study trends or performance standards from multiple manufacturing operations, change the parameters of the current processing, set the processing steps to follow the current processing, or start a new processing. In some examples, a remote computer (such as a server) can provide a processing recipe to the system through a network (which can include a local network or the Internet). The remote computer can include a user interface that enables input or programming of parameters and / or settings, and then the parameters and / or settings are delivered to the system from the remote computer. In some examples, the system controller 1430 receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of processing to be performed and the type of tool, and the controller is configured to interface with the tool or control the tool. Thus, as described above, the system controller 1430 can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., processing and control as described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control processing on the chamber.

[0167] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, track chambers or modules, EUV lithography chambers (scanners) or modules, dry lithography chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0168] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0169] EUVL patterning can be performed using any suitable tool, which is generally referred to as a scanner, such as the TWINSCAN NXE provided by ASML (Veldhoven, NL): Platform. The EUVL patterning tool can be a stand-alone device into which and from which substrates are moved for deposition and etching as described herein. Alternatively, as described below, the EUVL patterning tool can be a module on a larger multi-component tool. Fig.15 A semiconductor processing cluster tool architecture is depicted having vacuum integrated deposition, EUV patterning, and dry development etch modules interfaced with a vacuum transfer module suitable for performing the processes described herein. Although these processes may be performed in the absence of such vacuum integrated devices, such devices may be advantageous in certain embodiments.

[0170] Fig.13 A semiconductor processing cluster tool architecture is depicted, having vacuum integrated deposition and patterning modules interfaced with a vacuum transfer module, suitable for performing the processes described herein. The configuration of a transfer module for "transferring" wafers between multiple storage devices and processing modules may be referred to as a "cluster tool architecture" system. Depending on the requirements of a particular process, the deposition and patterning modules are vacuum integrated. Other modules (e.g., for etching) may also be included on the cluster.

[0171] Vacuum transfer module (VTM) 1538 interfaces with four process modules 1520a-1520d, which can each be optimized to perform a variety of manufacturing processes. As an example, process modules 1520a-1520d can be used to perform deposition, evaporation, ELD, dry development, etching, stripping, and / or other semiconductor processes. For example, module 1520a can be an ALD reactor that is operable to perform non-plasma thermal atomic layer deposition as described herein, such as a Vector tool available from Lam Research Corporation (Fremont, CA). Module 1520b can be a PEALD tool (e.g., Lam Research Corporation, Fremont, CA). ). It should be understood that the drawings are not necessarily drawn to scale.

[0172] Air locks 1542 and 1546 (also referred to as load locks or transfer modules) interface with VTM 1538 and patterning module 1540. For example, as described above, a suitable patterning module may be the TWINSCAN NXE: Platform (provided by ASML, Veldhoven, NL). This tool architecture allows the workpiece (e.g., semiconductor substrate or wafer) to be transported under vacuum so as not to react before exposure. The integration of the deposition module with the lithography tool is facilitated by the fact that the ambient gas (e.g., H 2 O, O 2 EUVL also requires significantly reduced pressure due to the strong optical absorption of incident photons.

[0173] As mentioned above, this integrated architecture is only one possible implementation of the tools used to perform the processes described. These processes can also be performed using more conventional standalone EUVL scanners and deposition reactors (such as Lam Vector tools) as modules, either standalone or integrated in a cluster architecture with other tools (such as etch, strip, etc. (such as Lam Kiyo or Gamma tools)), such as reference Fig.15 as described (but without the integrated patterning module).

[0174] Airlock 1542 may be an "output" load lock, representing the transfer of substrates from the VTM 1538 used by the deposition module 1520a to the patterning module 1540, while airlock 1546 may be an "input" load lock, representing the transfer of substrates from the patterning module 1540 back to the VTM 1538. The input load lock 1546 may also serve as an interface to the exterior of the tool for the entry and exit of substrates. Each process module has a facet that docks the module to the VTM 1538. For example, the deposition process module 1520a has a facet 1536. Within each facet, sensors (e.g., sensors 1-18 shown in the figure) are used to detect the passage of wafers 1526 as they move between the corresponding stations. The patterning module 1540 and airlocks 1542, 1546 may be similarly equipped with additional facets and sensors (not shown).

[0175] The main VTM robot 1522 transfers wafers 1526 between modules, including airlocks 1542 and 1546. In one embodiment, the robot 1522 has one arm, while in another embodiment, the robot 1522 has two arms, each of which has an end effector 1524 to pick up a wafer (such as wafer 1526) for transport. The front-end robot 1544 is used to transfer wafers 1526 from the output airlock 1542 to the patterning module 1540 and from the patterning module 1540 to the input airlock 1546. The front-end robot 1544 can also transfer wafers 1526 between the input load lock and the outside of the tool for the entry and exit of substrates. Since the input airlock module 1546 can match the environment between atmosphere and vacuum, the wafer 1526 can move between these two pressure environments without damage.

[0176] It should be noted that EUVL tools typically operate at a higher vacuum than deposition tools. If this is the case, it is desirable to increase the vacuum environment of the substrate during transfer from deposition to the EUVL tool to allow the substrate to be degassed before entering the patterning tool. The output gas lock 1542 can provide this function by maintaining the transferred wafer at a lower pressure (no higher than the pressure in the patterning module 1540) for a period of time and evacuating any off-gassing so that the optical components of the patterning tool 1540 are not contaminated by off-gassing from the substrate. A suitable pressure for the output off-gas gas lock is no more than 1E-8 Torr.

[0177] In some embodiments, system controller 1550 (which may include one or more entities or logic controllers) controls some or all operations of cluster tools and / or their separate modules. It should be noted that the controller may be local to the cluster architecture, or may be located outside the cluster architecture in the manufacturing floor, or may be located at a remote location and connected to the cluster architecture via a network. System controller 1550 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or a computer, analog and / or digital input / output connections, a stepper motor control board, and other similar components. Multiple instructions for implementing suitable control operations are executed on the processor. These instructions may be stored on a memory device connected to the controller, or may be provided via a network. In certain embodiments, the system controller executes system control software.

[0178] The system control software may include instructions for controlling the timing of the application and scale of aspects of the operation of any tool or module. The system control software may be configured in any appropriate manner. For example, various processing tool component subroutines or control objects may be written to control the operation of the processing tool components required for implementing various processing tool programs. The system control software may be encoded in any suitable computer readable programming language. In some embodiments, the system control software includes input-output control (IOC) sequence instructions to control the various parameters mentioned above. For example, each stage of semiconductor manufacturing processing may include one or more instructions executed by the system controller. For example, instructions for setting the processing conditions of condensation, deposition, evaporation, patterning and / or etching stages may be included in the corresponding recipe stage.

[0179] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include a processing chamber for patterning, deposition, and etching, and a controller including instructions for forming a negative pattern mask. The instructions may include program code for performing the following processes in the processing chamber: exposing the substrate surface by EUV exposure, patterning features in a chemically amplified resist (CAR) on a semiconductor substrate; dry developing the photopatterned resist; and using the patterned photoresist as a mask to etch an underlying layer or layer stack. The development may be performed using a halide-containing chemical.

[0180] It should be noted that the computer controlling the movement of the wafers may be local to the cluster architecture, or may be located external to the cluster architecture on the manufacturing floor, or located at a remote location and connected to the cluster architecture via a network. Fig.12 , 13 or 14 and the controller described above can be used with Fig.15 It is implemented together with the tools in.

[0181] in conclusion

[0182] Disclosed are processes and apparatus in the context of EUV patterning for dry development of metal and / or metal oxide photoresists, for example to form patterned masks.

[0183] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or variations are suggested to those skilled in the art accordingly. Although various details have been omitted for the purpose of clarity, various design alternatives may be implemented. Therefore, the examples should be considered illustrative rather than restrictive, and the present disclosure is not limited to the details set forth herein, but may be modified within the scope of the disclosure.

Claims

1. A method for processing a semiconductor substrate, comprising: providing a photo-patterned metal-containing resist on a substrate layer of a semiconductor substrate in a processing chamber; as well as The photo-patterned metal-containing resist is dry developed by selectively removing a portion of the photo-patterned metal-containing resist by exposure to a dry developing chemistry including a halide to form a resist mask. 2 . The method of claim 1 , wherein the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist.

3. The method of claim 2, wherein the photo-patterned metal-containing EUV resist comprises an unexposed organic-metal oxide-containing portion and an EUV-exposed metal oxide-containing portion, wherein the halide selectively removes the unexposed organic-metal oxide-containing portion relative to the EUV-exposed metal oxide-containing portion to form the photoresist mask.

4. The method according to claim 3, further comprising: The non-EUV exposed portions and the EUV exposed portions of the photo-patterned metal-containing resist are non-selectively removed without removing the substrate layer.

5. The method of claim 1, wherein the dry developing chemistry comprises hydrogen halide, hydrogen and halogen gas, boron trichloride, organic halide, acyl halide, carbonyl halide, sulfinyl halide, or a mixture thereof.

6. The method of claim 5, wherein the dry developing chemical comprises hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), or hydrogen iodide (HI). The method of claim 6 , wherein the dry developing chemistry comprises HBr.

8. The method of claim 5, wherein the dry developing chemistry comprises an acyl halide, a carbonyl halide, a sulfinyl halide, or a mixture thereof.

9. The method of claim 1, wherein the halide is flowed into the process chamber along with a carrier gas, the carrier gas comprising helium (He), neon (Ne), argon (Ar), xenon (Xe), or nitrogen (N2).

10. The method of claim 1, wherein dry developing the photo-patterned metal-containing resist comprises: A remote plasma including radicals of the halide is applied to the photo-patterned metal-containing resist.

11. The method of claim 1 , wherein dry developing the photo-patterned metal-containing resist comprises: The exposure to at least the halide is performed in a plasma-free thermal process.

12. The method of claim 1 , wherein the photo-patterned metal-containing resist is dry developed at a temperature between −60° C. and 120° C., a chamber pressure between 0.1 mTorr and 760 Torr, and a gas flow rate of the halide between 100 sccm and 2000 sccm, wherein the etch selectivity of the resist mask can be adjusted at least in part based on the temperature, the chamber pressure, the gas flow rate, or a combination thereof.

13. The method of claim 12, wherein the temperature is between -20°C and 20°C.

14. The method of claim 12, wherein a profile of the resist mask is controllable based at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof.

15. The method according to any one of claims 1 to 14, wherein the photo-patterned metal-containing resist is an organic metal oxide-containing thin film or an organic metal-containing thin film.

16. The method of claim 15, wherein the photopatterned metal-containing resist comprises an organotin oxide.

17. The method of any one of claims 1 to 14, wherein the photo-patterned metal-containing resist comprises an element selected from the group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium.

18. The method of any one of claims 1 to 14, wherein providing the photo-patterned metal-containing resist comprises vapor depositing a metal-containing resist film on the substrate layer.

19. The method of any one of claims 1 to 14, wherein providing the photo-patterned metal-containing resist comprises: A metal-containing resist film is spin-coated on the substrate layer.

20. The method of any one of claims 1 to 14, wherein the photo-patterned metal-containing resist has a thickness between 10 nm and 50 nm.

21. The method according to any one of claims 1 to 14, further comprising: After dry developing the photo-patterned metal-containing resist, the photo-patterned metal-containing resist is exposed to an inert gas plasma.

22. The method according to claim 21, further comprising: The following operations are repeatedly performed: dry developing the photo-patterned metal-containing resist and exposing the photo-patterned metal-containing resist to the inert gas plasma.

23. The method according to any one of claims 1 to 14, further comprising: The photo-patterned metal-containing resist is baked at a high temperature before dry developing the photo-patterned metal-containing resist.

24. The method of any one of claims 1 to 14, wherein providing the photo-patterned metal-containing resist comprises: depositing a metal-containing EUV resist film on the semiconductor substrate; non-selectively removing portions of the metal-containing EUV resist film on the back side and bevel edge of the semiconductor substrate; as well as The metal-containing EUV resist film is exposed to EUV light to form the photo-patterned metal-containing resist.

25. The method according to any one of claims 1 to 14, further comprising: depositing a metal-containing EUV resist film on the semiconductor substrate; as well as Prior to providing the photo-patterned metal-containing resist, the metal-containing EUV resist film is non-selectively removed from the semiconductor substrate without removing the substrate layer.

26. An apparatus for developing a resist, the apparatus comprising: a processing chamber having a substrate support; a vacuum line coupled to the process chamber; a developing chemical line coupled to the process chamber; as well as A controller configured with instructions for processing a semiconductor substrate, the instructions including code for: providing a photo-patterned metal-containing resist on a substrate layer of the semiconductor substrate in the processing chamber; as well as The photo-patterned metal-containing resist is dry developed by selectively removing a portion of the photo-patterned metal-containing resist by exposure to a dry developing chemistry including a halide to form a resist mask.

27. A device according to claim 26, wherein the photo-patterned metal-containing EUV resist includes an unexposed organic-metal oxide-containing portion and an EUV-exposed metal oxide-containing portion, wherein the halide selectively removes the unexposed organic-metal oxide-containing portion relative to the EUV-exposed metal oxide-containing portion to form the resist mask.

28. The apparatus of claim 26, further comprising: One or more heaters are coupled to the substrate support, wherein the one or more heaters include a plurality of independently controllable temperature control zones.

29. The apparatus of claim 26, wherein the interior of the process chamber is coated with a corrosion inhibitor.

30. The apparatus of claim 26, further comprising: A condensation trap is coupled to the process chamber, wherein the condensation trap is configured to remove water from the process chamber.

31. Apparatus according to any one of claims 26 to 30, wherein the processing chamber comprises a plastic material.

32. The device according to any one of claims 26 to 30, further comprising: A UV lamp or an IR lamp is coupled to the process chamber, wherein the UV lamp or the IR lamp is configured to cure the photo-patterned metal-containing resist or remove excess halide from the process chamber.

33. A method for processing a semiconductor substrate, comprising: In a process chamber, providing a dry-deposited photo-patterned metal oxide EUV resist on a substrate layer of a semiconductor substrate; as well as The non-EUV exposed portions of the photo-patterned metal oxide EUV resist are selectively removed by exposure to a dry developing chemistry including HCl and / or HBr to dry develop the photo-patterned metal oxide EUV resist to form a resist hard mask from the EUV exposed portions.

34. The method of claim 33, wherein dry development is performed in a plasma-free thermal process, wherein exposure to the dry developing chemistry is performed at a temperature between -20°C and 20°C.

35. The method of claim 33, wherein the photo-patterned metal oxide EUV resist comprises an organotin oxide.

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