Semiconductor device

Abstract

A semiconductor device includes a first semiconductor chip (11) and a second semiconductor chip (12) supplied with different power supply voltages, a connecting wire (30) connecting the first semiconductor chip (11) and the second semiconductor chip (12), and a sealing resin (40) buried between a first lead frame (21) mounting the first semiconductor chip (11) and a second lead frame (22) mounting the second semiconductor chip (12) and arranged so as to cover the periphery of the first semiconductor chip (11) and the second semiconductor chip (12). The surfaces of the regions of the first lead frame (21) and the second lead frame (22) facing each other are covered with an insulating protective film (50) formed of a material having a higher dielectric breakdown voltage than the sealing resin (40).

Description

Technical Field

[0001] This embodiment relates to a semiconductor device sealed with resin. Background Technology

[0002] Semiconductor devices are known for driving switching elements such as insulated-gate bipolar transistors (IGBTs) or metal / oxide-semiconductor junction field-effect transistors (MOSFETs). The semiconductor device driving the switching element is also called a "gate driver." A gate driver has a structure comprising a semiconductor chip that operates at a relatively low supply voltage (hereinafter referred to as the "low-voltage side chip") and a semiconductor chip that drives the switching element and operates at a relatively high supply voltage (hereinafter referred to as the "high-voltage side chip").

[0003] For example, a gate driver is used, comprising: a low-voltage side chip operating at a power supply voltage of approximately 5V relative to ground; and a high-voltage side chip operating at a power supply voltage of approximately 1000V relative to ground, and controlled by the low-voltage side chip to drive switching elements. Such a gate driver can employ a structure including a transformer chip that converts the output electrical signal of the low-voltage side chip into magnetic force, and then converts this magnetic force into an electrical signal output to the high-voltage side chip (see Patent Document 1). Since no electrical signal is directly transmitted between the low-voltage side chip and the high-voltage side chip, dielectric breakdown of the low-voltage side chip can be prevented.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent document 1: Japanese Patent Application Publication No. 2010-80774. Summary of the Invention

[0007] The problem the invention aims to solve

[0008] Semiconductor devices are sealed with resin through processes such as molding. During the molding process, impurities may become trapped inside the sealing resin. In this case, the impurities may enter across the leadframe containing the low-voltage side chip and the leadframe containing the high-voltage side chip, potentially causing dielectric breakdown of the low-voltage side chip. Furthermore, dielectric breakdown of the low-voltage side chip may also occur if impurities become trapped between the bonding wires connected to the low-voltage side chip or the bonding wires connected to the high-voltage side chip.

[0009] The purpose of this embodiment is to suppress dielectric breakdown in a semiconductor device obtained by sealing multiple semiconductor chips with different supplied power voltages in resin.

[0010] Technical means for solving problems

[0011] According to one embodiment of the present invention, a semiconductor device is provided, comprising: a first semiconductor chip and a second semiconductor chip supplied with different power supply voltages; a first lead frame on which the first semiconductor chip is mounted; a second lead frame on which the second semiconductor chip is mounted; bonding wires electrically connecting the first semiconductor chip and the second semiconductor chip; a sealing resin covering the first semiconductor chip and the second semiconductor chip; and an insulating protective film formed of a material having a higher dielectric breakdown voltage than the sealing resin, covering the surfaces of the opposing regions of the first lead frame and the second lead frame.

[0012] Invention Effects

[0013] According to this embodiment, dielectric breakdown can be achieved in a semiconductor device obtained by sealing multiple semiconductor chips with different power supply voltages in resin. Attached Figure Description

[0014] Figure 1 This is a schematic side view showing the structure of the semiconductor device according to the embodiment.

[0015] Figure 2 It is a schematic plan view showing the structure of the semiconductor device in the embodiment.

[0016] Figure 3 This is a schematic diagram illustrating an example of impurity contamination.

[0017] Figure 4 This is a schematic diagram illustrating an example of an impurity in a semiconductor device according to an embodiment.

[0018] Figure 5 This is a schematic diagram illustrating another example of impurity contamination.

[0019] Figure 6 This is a schematic diagram illustrating another example of impurity contamination.

[0020] Figure 7 This is one of the schematic diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0021] Figure 8 This is a schematic diagram (part two) illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0022] Figure 9 This is a schematic diagram (Part 3) illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0023] Figure 10 This is a schematic diagram illustrating an example of the shape of the lead frame of a semiconductor device according to an embodiment.

[0024] Figure 11This is a schematic diagram illustrating another example of the shape of the lead frame of a semiconductor device according to an embodiment.

[0025] Figure 12 This is a circuit example using a semiconductor device implemented in this way.

[0026] Figure 13 This is a schematic cross-sectional view illustrating the structure of a transformer chip in a semiconductor device according to an embodiment.

[0027] Figure 14 It is a schematic plan view showing the structure of the upper coil of the transformer chip.

[0028] Figure 15 It is a schematic plan view showing the structure of the lower coil of a transformer chip.

[0029] Figure 16 It is a schematic plan view showing the configuration of the electrodes of a transformer chip. Detailed Implementation

[0030] Next, the embodiments will be described with reference to the accompanying drawings. In the following description of the drawings, the same or similar parts will be labeled with the same or similar reference numerals. However, the drawings are schematic illustrations, and it should be noted that the relationships between thickness and planar dimensions, the thickness ratios of various parts, etc., may differ from the actual situation. Furthermore, there are naturally parts in the drawings that differ in dimensional relationships or ratios from each other.

[0031] Furthermore, the embodiments shown below are examples of apparatus or methods for embodying technical ideas, and the shape, structure, arrangement, etc., of the constituent components are not limited to the following. Various modifications can be made to this embodiment within the scope of the claims.

[0032] Semiconductor device 1 in the embodiment is as follows Figure 1 The device shown includes a first semiconductor chip 11 that operates when supplied with a first power supply voltage, and a second semiconductor chip 12 that operates when supplied with a second power supply voltage that is higher than the first power supply voltage. The first semiconductor chip 11 is a low-voltage side chip that operates, for example, with a power supply voltage of 5V to 20V relative to ground. On the other hand, the second semiconductor chip 12 is a high-voltage side chip that operates, for example, with a power supply voltage of 600V to 1000V relative to ground. Hereinafter, the region where the first power supply voltage with a relatively lower potential is applied will be referred to as the "low-voltage side region." The region where the second power supply voltage with a relatively higher potential is applied will be referred to as the "high-voltage side region."

[0033] Figure 1In the semiconductor device 1 shown, the first semiconductor chip 11 includes a control chip 111 and a transformer chip 112. The transformer chip 112 converts the electrical signal output from the control chip 111 into magnetic force, and then converts the magnetic force back into an electrical signal. Furthermore, the transformer chip 112 outputs the electrical signal converted from the magnetic force to the second semiconductor chip 12. The second semiconductor chip 12 controls its operation based on the output electrical signal from the control chip 111, driving a switching element that operates at a high power supply voltage. In other words, the semiconductor device 1 is a gate driver that operates by using the second semiconductor chip 12 as a driver chip to drive the switching element.

[0034] Transformer chip 112, etc. Figure 1 The transformer chip 112 is positioned between the controlled chip 111 and the second semiconductor chip 12. The transformer chip 112 is electrically connected to the second semiconductor chip 12 via a bonding wire 30.

[0035] The transformer chip 112 may employ a configuration that includes a receiving-side inductor that converts the electrical signal output from the control chip 111 into magnetic force, and a transmitting-side inductor that converts the magnetic force into an electrical signal output to the second semiconductor chip 12. Since no electrical signal is directly transmitted between the control chip 111 and the second semiconductor chip 12, dielectric breakdown of the control chip 111 due to high voltage supplied to the second semiconductor chip 12 can be prevented.

[0036] A first semiconductor chip 11 is mounted on the chip mounting surface of the first lead frame 21. A control chip 111 and a transformer chip 112 are fixed to the first lead frame 21 using a chip adhesive 60. A second semiconductor chip 12 is mounted on the chip mounting surface of the second lead frame 22. The second semiconductor chip 12 is fixed to the second lead frame 22 using a chip adhesive 60. The material of the chip adhesive 60 can appropriately include silver paste, etc.

[0037] The electrical signal output from the control chip 111 is input to the transformer chip 112 via the connecting wire 315. Furthermore, the electrical signal output from the transformer chip 112 is transmitted to the second semiconductor chip 12 via the connecting wire 30.

[0038] Figure 1The semiconductor device 1 shown is sealed with sealing resin 40. Sealing resin 40 is embedded between the first lead frame 21 and the second lead frame 22, covering the chip mounting surfaces of the first semiconductor chip 11, the second semiconductor chip 12, and the first and second lead frames 21 and 22. Furthermore, the first bonding wire 311, which electrically connects the control chip 111 to the first lead frame 21, and the second bonding wire 321, which electrically connects the second semiconductor chip 12 to the second lead frame 22, are sealed with sealing resin 40. Hereinafter, the bonding wires (connecting bonding wire 315, first bonding wire 311, etc.) used in the electrical connection with the first semiconductor chip 11 in the low-voltage side region will be referred to as "low-voltage side bonding wire 31". Similarly, the bonding wires (connecting bonding wire 30, second bonding wire 321, etc.) used in the electrical connection with the second semiconductor chip 12 in the high-voltage side region will be referred to as "high-voltage side bonding wire 32".

[0039] Figure 1 The shown proximity region A is the region where the low-voltage side region and the high-voltage side region are relatively close. In the semiconductor device 1, the surfaces of the opposing regions of the first lead frame 21 and the second lead frame 22 are covered by an insulating protective film 50 inside the sealing resin 40. That is, in proximity region A, the surfaces of the regions of the first lead frame 21 and the second lead frame 22 opposite to each other, and the surfaces of the regions of the second lead frame 22 and the first lead frame 21 opposite to each other, are covered by the insulating protective film 50. Furthermore, in proximity region A, the surfaces of the opposing regions of the first semiconductor chip 11 and the first lead frame 21 with the bonding wire 30 are covered by the insulating protective film 50. In this way, in the semiconductor device 1, the surfaces of conductive components in proximity region A are covered by the insulating protective film 50. The insulating protective film 50 is made of a material with a dielectric breakdown voltage higher than that of the sealing resin 40.

[0040] For the sealing resin 40, epoxy resins or silicone resins can be used, for example. On the other hand, for the insulating protective film 50, thermoplastic aromatic polyether amide imide containing aromatic hydrocarbons in its basic molecular structure can be used, for example. As sealing resins for semiconductor devices, epoxy resins typically have a dielectric breakdown voltage of around 40 V / mm, while thermoplastic aromatic polyether amide imide has a dielectric breakdown voltage of around 230 kV / mm.

[0041] Alternatively, the sealing resin 40 can be a resin mixed with fillers, and the insulating protective film 50 can be a resin without fillers or a resin with a filler content lower than that of the sealing resin 40. Since charge accumulates at the filler-resin interface, the dielectric breakdown voltage of the resin containing fillers decreases. Therefore, by using a resin with a relatively lower filler content for the insulating protective film 50 compared to the sealing resin 40, the insulating protective film 50 can be made into a material with a higher dielectric breakdown voltage than the sealing resin 40.

[0042] Furthermore, for the insulating protective film 50, a soft material with lower hardness than the sealing resin 40 is preferred. Also, it is preferable to use a material for the insulating protective film 50 that has high adhesion to the sealing resin 40.

[0043] Figure 2 This is a plan view of the semiconductor device 1 according to the embodiment. Figure 2 The semiconductor device 1 shown has a low-voltage side lead terminal 71 and a high-voltage side lead terminal 72, one end of which is disposed inside the sealing resin 40 and the other end of which is exposed outside the sealing resin 40. Multiple low-voltage side leads 71 ​​are electrically connected to a control chip 111 via first bonding wires 312. Additionally, multiple high-voltage side leads 72 are electrically connected to a second semiconductor chip 12 via second bonding wires 322.

[0044] The materials used for the first lead frame 21, the second lead frame 22, the low-voltage side lead terminal 71, and the high-voltage side lead terminal 72 are, for example, copper (Cu). Additionally, the materials used for the bonding wires are, for example, gold (Au) or aluminum (Al).

[0045] The sealing resin 40 is formed through molding or the like. In this process, impurities may become mixed into the sealing resin 40. For example, ... Figure 3 The conductive impurity 100 is mixed into the interior of the sealing resin 40, causing a short circuit between the first lead frame 21 in the low-voltage side region and the second lead frame 22 in the high-voltage side region due to the impurity 100. In this case, if a high power supply voltage is supplied to the second lead frame 22, the first semiconductor chip 11 mounted on the first lead frame 21 may be dielectrically broken down.

[0046] However, in the semiconductor device 1 of the embodiment, such as Figure 4 As shown, an insulating protective film 50, formed of a material with a dielectric breakdown voltage higher than that of the sealing resin 40, covers the surfaces of the opposing regions of the first lead frame 21 and the second lead frame 22. Therefore, even if conductive impurities 100 are mixed into the interior of the sealing resin 40 across the first lead frame 21 and the second lead frame 22, dielectric breakdown of the first semiconductor chip 11 can be suppressed.

[0047] Furthermore, even if the low-voltage side region and the high-voltage side region cannot be short-circuited by the impurity 100 at all, the first semiconductor chip 11 may still be dielectrically broken down because the impurity 100 is mixed between the low-voltage side region and the high-voltage side region, narrowing the distance between the two regions. However, by covering the opposing surfaces of the low-voltage side region and the high-voltage side region with an insulating protective film 50, dielectric breakdown of the first semiconductor chip 11 can be suppressed.

[0048] Furthermore, even if the impurity 100 is not a conductor, its adhesion to the first lead frame 21 or the second lead frame 22 reduces the adhesion between the first lead frame 21 or the second lead frame 22 and the sealing resin 40. This reduced adhesion leads to decreased insulation. However, by covering the surfaces of the first lead frame 21 and the second lead frame 22 with an insulating protective film 50, dielectric breakdown of the first semiconductor chip 11 can be suppressed.

[0049] Furthermore, not only between the first lead frame 21 and the second lead frame 22, such as Figure 5 As shown, if impurities 100 are mixed between the bonding wire 30 and the first semiconductor chip 11, the first semiconductor chip 11 may also be dielectrically broken down.

[0050] However, in semiconductor device 1, the surfaces of the regions opposite to each other, namely the first semiconductor chip 11 and the bonding wire 30, are covered by an insulating protective film 50. Similarly, the surface of the chip adhesive 60 near region A is also covered by the insulating protective film 50. Therefore, it is possible to prevent a short circuit between the first semiconductor chip 11 and the bonding wire 30 via impurities 100. As a result, dielectric breakdown of the first semiconductor chip 11 can be suppressed.

[0051] In addition, such as Figure 6 As shown, if impurities 100 are mixed between the bonding wire 30 and the low-voltage side bonding wire 31 connected to the first semiconductor chip 11, the first semiconductor chip 11 may also be dielectrically broken down.

[0052] However, in semiconductor device 1, the surfaces of the areas opposite to the connecting wires 30 and other bonding wires connected to the first semiconductor chip 11 are also covered by an insulating protective film 50. That is, in region A, the areas of the connecting wire 315 and the connecting wire 30 that are close to each other, as well as the areas of the connecting wire 30 and the connecting wire 315 that are close to the connecting wire 315, are covered by the insulating protective film 50. Therefore, short circuits between the connecting wire 30 and the low-voltage side bonding wire 31 caused by the incorporation of impurities 100 can be prevented, and dielectric breakdown of the first semiconductor chip 11 can be suppressed.

[0053] Furthermore, the situation where the bonding wires bend and come into contact with each other during the formation process of the sealing resin 40 has also been considered. According to the semiconductor device 1, even if the connecting bonding wire 30 and the low-voltage side bonding wire 31 are deformed and come into contact, short circuits can be suppressed.

[0054] The following is an explanation. Figure 1 The semiconductor device 1 shown is manufactured using a method described below. Furthermore, the semiconductor device manufacturing method described below is an example, and various other manufacturing methods, including this variation, can be used to achieve the same result.

[0055] Handheld, as Figure 7 As shown, a chip mounting process and a wire bonding process are performed. Specifically, in the chip mounting process, the control chip 111 and the transformer chip 112 are fixed to the chip mounting surface of the first lead frame 21 using chip adhesive 60. Additionally, the second semiconductor chip 12 is fixed to the chip mounting surface of the second lead frame 22 using chip adhesive 60. Furthermore, in the wire bonding process, the first lead frame 21 and the control chip 111 are connected via a first bonding wire 311, and the second lead frame 22 and the second semiconductor chip 12 are connected via a second bonding wire 321. Moreover, the control chip 111 and the transformer chip 112 are connected via a connecting bonding wire 315, and the transformer chip 112 and the second semiconductor chip 12 are connected via a connecting bonding wire 30.

[0056] Next, as Figure 8 As shown, an insulating protective film 50 is formed on the surface of a specified component contained in the area near A. Specifically, the insulating protective film 50 is formed in such a way that it covers the surfaces of the opposing regions of the first lead frame 21 and the second lead frame 22, as well as the surfaces of the opposing regions of the first semiconductor chip 11 and the first lead frame 21 and the connecting wire 30. For example, the liquid insulating protective film 50 is dripped into the area near A and then cured.

[0057] Next, as Figure 9 As shown, a sealing resin 40 is formed in a designated area of ​​the semiconductor device 1 by molding. Specifically, the sealing resin 40 is formed by embedding it between the first lead frame 21 and the second lead frame 22, covering the area around the first semiconductor chip 11, the second semiconductor chip 12, and the chip mounting surfaces of the first lead frame 21 and the second lead frame 22. Through this method, the process is completed. Figure 1 Semiconductor device 1 is shown.

[0058] In addition, such as Figure 10 As shown, the corners formed by the opposing sides of the first leadframe 21 and the second leadframe 22, and the other side connected to the opposing side, are preferably formed as R-shaped chamfers when viewed from the surface normal of the chip mounting surface. By forming the corners of the first leadframe 21 and the second leadframe 22 as curved surfaces, the electric field concentration at the corners can be mitigated. This improves the insulation withstand voltage of the semiconductor device. Alternatively, the corners of the first leadframe 21 and the second leadframe 22 can also be formed as C-shaped chamfers.

[0059] In addition, such as Figure 11As shown, the corners formed by the opposing side surfaces of the first leadframe 21 and the second leadframe 22 and the main surface connecting to the opposing side surfaces are preferably formed with rounded corners (R-shaped chamfers). That is, the corner formed by the upper surface of the semiconductor chip and the opposing side surface is preferably formed with a rounded corner, and the corner formed by the lower surface opposite the upper surface and the opposing side surface is also formed with a rounded corner. This mitigates the electric field concentration at the corners of the first leadframe 21 and the second leadframe 22, thereby improving the insulation withstand voltage of the semiconductor device.

[0060] exist Figure 12 The diagram shows a circuit example using semiconductor device 1 according to the embodiment. Figure 12 In the circuit example shown, the first transistor T1 and the second transistor T2 are connected in series between the power supply voltage Vgt and the ground potential. The power supply voltage Vgt connected to the first transistor T1 is 600V to 1000V. The potential Vout of the output terminal, which serves as the connection point between the first transistor T1 and the second transistor T2, is set according to the on / off state of the first transistor T1 and the second transistor T2. The first transistor T1 and the second transistor T2 are, for example, IGBTs or MOSFETs.

[0061] The operation of the second transistor T2 is controlled by the semiconductor device 2. The second reference potential Vs2 of the semiconductor device 2 is ground potential, and the second power supply voltage Vg2 is supplied to the semiconductor device 2. The potential of the second power supply voltage Vg2 is in the range of 5V to 20V.

[0062] Semiconductor device 1 controls the operation of the first transistor T1. In semiconductor device 1, a first reference potential Vs1 is set to the output terminal potential Vout and is supplied with a first power supply voltage Vg1. The potential difference between the first reference potential Vs1 and the first power supply voltage Vg1 is, for example, around 5V to 20V. The first reference potential Vs1 is lower when the second transistor T2 is turned on and the first transistor T1 is turned off. On the other hand, the first reference potential Vs1 is higher than the power supply voltage Vgt when the first transistor T1 is turned on and the second transistor T2 is turned off, corresponding to a high potential of around 600V to 1000V. In this way, a higher power supply voltage is supplied to the second semiconductor chip 12 that drives the first transistor T1.

[0063] exist Figure 12 In the circuit example shown, a first transistor T1 connected to a power supply voltage Vgt of, for example, 1000V, is driven via semiconductor device 1. At this time, electrical signals are transmitted between the first semiconductor chip 11 and the second semiconductor chip 12 via a transformer chip 112 that converts electrical signals into magnetic forces. Therefore, dielectric breakdown of the first semiconductor chip 11 can be suppressed.

[0064] By inductively coupling a pair of inductors (coils) consisting of a receiving-side inductor and a transmitting-side inductor to the transformer chip 112, an inductively coupled insulating element for transmitting electrical signals based on insulation states can be appropriately used. In the inductively coupled insulating element, the electrical signal is converted into a magnetic force by the receiving-side inductor, and this magnetic force is converted into an electrical signal by the transmitting-side inductor.

[0065] Figure 13 The diagram illustrates a configuration example of a transformer chip 112. The transformer chip 112 has a structure in which multiple insulating layers 210 are stacked on a semiconductor substrate 200. The semiconductor substrate 200 is, for example, a silicon substrate or a silicon carbide substrate. Figure 13 An example is shown where a 12-layer insulating layer 210 is stacked on a semiconductor substrate 200. However, the number of insulating layers 210 is not limited to 12. The number of insulating layers 210 can be set according to the insulation withstand voltage required by the transformer chip 112, etc.

[0066] The insulating layer 210 has a structure in which an etch stop film 211 is stacked as the lower layer and an interlayer film 212 is stacked as the upper layer. The etch stop film 211 is, for example, a silicon nitride (SiN) film or a silicon carbide (SiC) film. The interlayer film 212 is, for example, a silicon oxide (SiO2) film. However, the bottom insulating layer 210 does not have an etch stop film 211, and the interlayer film 212 is directly disposed on the main surface of the semiconductor substrate 200. The etch stop film 211 formed from the SiN film has tensile stress. The interlayer film 212 formed from the SiO2 film has compressive stress. In addition, by using the etch stop film 211, it is possible to prevent Cu contained in the Cu wiring material described later from diffusing to the interlayer film 212.

[0067] Inside the transformer chip 112, such as Figure 13 The diagram shows a coil 220 consisting of an upper coil 221 and a lower coil 222 as a pair. The upper coil 221 and the lower coil 222 face each other separated by multiple layers of insulating layers 210. The upper coil 221 and the lower coil 222 are made of conductive material and form an elliptical spiral shape when viewed from above.

[0068] like Figure 14 As shown, an inner wiring 221A, connected to the inner end of the upper coil 221, is disposed at the center of the upper coil 221. An outer wiring 221B, connected to the outer end of the upper coil 221, is disposed on the outer side of the upper coil 221. Additionally, as... Figure 15 As shown, an inner wiring 222A for the lower coil 222 is disposed at the center of the lower coil 222 and connected to the inner end of the lower coil 222. An outer wiring 222B for the lower coil 222 is disposed on the outer side of the lower coil 222 and connected to the outer end of the lower coil 222.

[0069] like Figure 13 As shown, the upper coil 221 and the lower coil 222 penetrate one layer of the insulating layer 210 in the film thickness direction. Figure 13 In the example shown, the lower coil 222 is disposed on the fourth insulating layer 210 counting from the semiconductor substrate 200 side, and the upper coil 221 is disposed on the eleventh insulating layer 210. For example, Cu wiring material with Cu as the main component is used in the upper coil 221 and the lower coil 222. On the sides of the upper coil 221 and the lower coil 222, a tantalum (Ta) / tantalum nitride (TaN) / tantalum (Ta) laminate or the like can be formed as a barrier metal layer. Using a barrier metal layer can prevent Cu contained in the Cu wiring material from diffusing to the interlayer film 212.

[0070] A low-voltage electrode layer 241 is disposed on the insulating layer 210 below the insulating layer 210 where the lower coil 222 is disposed. The lower coil inner wiring 222A and the low-voltage electrode layer 241 are electrically connected by a columnar first low-voltage wiring 251 that passes through the middle insulating layer 210. The low-voltage electrode layer 241 is electrically connected to the semiconductor substrate 200 via a ground wiring 260.

[0071] Furthermore, the lower low-voltage wiring 242 is disposed on the insulating layer 210 on which the lower coil 222 is disposed. The low-voltage electrode layer 241 and the lower low-voltage wiring 242 are electrically connected by a columnar second low-voltage wiring 252 that passes through the intermediate insulating layer 210. Additionally, the upper low-voltage wiring 243 is disposed on the insulating layer 210 on which the upper coil 221 is disposed. The lower low-voltage wiring 242 and the upper low-voltage wiring 243 are electrically connected by a columnar third low-voltage wiring 253 that passes through the intermediate insulating layer 210.

[0072] A protective insulating film 290 is disposed on the upper surface of the transformer chip 112. The protective insulating film 290 is a laminated structure in which a coil protective film 292 is disposed on the upper surface of the passivation film 291. On the surface of the uppermost insulating layer 210 exposed from the opening provided in the protective insulating film 290, low-voltage electrodes 240A and high-voltage electrodes 250A are disposed spaced apart from each other. The materials of the low-voltage electrodes 240A and high-voltage electrodes 250A are, for example, aluminum (Al). The passivation film 291 is, for example, a laminated structure of silicon dioxide film / silicon nitride film. The coil protective film 292 is, for example, a polyimide film. The coil protective film 292 is disposed above the coil 220, and the coil 220 is covered by the coil protective film 292 when viewed from above.

[0073] The low-voltage electrode 240A is electrically connected to the upper low-voltage wiring 243 located below, via a columnar fourth low-voltage wiring 254 that passes through the insulating layer 210 located in the middle. That is, in the low-voltage electrode 240A, the upper low-voltage wiring 243, the lower low-voltage wiring 242, and the low-voltage electrode layer 241 are electrically connected to the lower coil inner wiring 222A via the first low-voltage wiring 251 to the fourth low-voltage wiring 254.

[0074] On the other hand, the high-voltage electrode 250A and the upper coil inner wiring 221A disposed below are electrically connected by a columnar high-voltage wiring 261 that passes through the insulating layer 210 in the middle.

[0075] In addition, such as Figure 13 As shown, the shielding layer 270 is configured to surround the coil 220 and to connect the coil 220 to the low-voltage electrode 240A or the high-voltage electrode 250A via wiring. The lower end of the shielding layer 270 and the semiconductor substrate 200 are electrically connected via a shielded ground wiring 275. The wiring and shielding layer 270 disposed inside the transformer chip 112, for example, use a laminated structure of Cu and a barrier metal layer, similar to that of the coil 220.

[0076] Figure 16 This is a plan view showing an example of the electrode configuration of transformer chip 112. Figure 16 The low-voltage electrode 240B shown is omitted from the illustration, but similarly to the structure connecting the inner wiring 222A of the lower coil and the low-voltage electrode 240A, it is electrically connected to the lower coil via wiring disposed inside the transformer chip 112. Similarly, the high-voltage electrode 250B is also omitted from the illustration, but similarly to the structure connecting the inner wiring 221A of the upper coil and the high-voltage electrode 250A, it is electrically connected to the upper coil via wiring disposed inside the transformer chip 112.

[0077] When semiconductor device 1 operates, an electrical signal output from control chip 111 is input to the low-voltage electrodes 240A and 240B of transformer chip 112. This electrical signal is converted into magnetic force by a lower coil 222 formed inside transformer chip 112. This magnetic force is converted into an electrical signal by an upper coil 221 arranged opposite to the lower coil 222. The converted electrical signal is output to the second semiconductor chip 12 via the high-voltage electrodes 250A and 250B of transformer chip 112.

[0078] In this way, in the transformer chip 112, the lower coil 222 functions as a receiving-side inductor, and the upper coil 221 functions as a transmitting-side inductor. Therefore, electrical signals are not directly transmitted between the control chip 111 and the second semiconductor chip 12. As a result, dielectric breakdown of the control chip 111 due to the high voltage supplied to the second semiconductor chip 12 can be prevented.

[0079] As described above, the discussions and drawings that form part of this invention, based on this embodiment, should not be construed as limiting the scope of this embodiment. Various alternative embodiments, examples, and application techniques should be conceived by those skilled in the art according to this invention. This embodiment includes various embodiments not described herein.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor chip is supplied with a first power supply voltage; The second semiconductor chip is supplied with a second power supply voltage that has a higher potential than the first power supply voltage. The first lead frame has a chip mounting surface on which the first semiconductor chip is mounted; The second lead frame has a chip mounting surface on which the second semiconductor chip is mounted; A bonding wire is used to electrically connect the first semiconductor chip and the second semiconductor chip. A sealing resin is disposed between the first lead frame and the second lead frame, and covers the area around the first semiconductor chip, the second semiconductor chip, and the chip mounting surfaces of the first lead frame and the second lead frame, respectively. and An insulating protective film, formed of a material with a dielectric breakdown voltage higher than that of the sealing resin, covers the surfaces of the opposing regions of the first lead frame and the second lead frame within the sealing resin, in a proximity region where the low-voltage side region to which the first power supply voltage is applied is relatively close to the high-voltage side region to which the second power supply voltage is applied.

2. The semiconductor device as described in claim 1, characterized in that: The insulating protective film further covers the surfaces of the first semiconductor chip, the first lead frame, and the areas of the connecting wires that are opposite to each other inside the sealing resin.

3. The semiconductor device as described in claim 1 or 2, characterized in that: The insulating protective film covers the area opposite to the bonding wires connected to the first semiconductor chip, excluding the bonding wires.

4. The semiconductor device as described in claim 1 or 2, characterized in that: The insulating protective film is made of a resin with a relatively low filler content compared to the resin used in the sealing resin.

5. The semiconductor device as described in claim 1 or 2, characterized in that: The insulating protective film is made of a material with a lower hardness than the sealing resin.

6. The semiconductor device as described in claim 1 or 2, characterized in that: The corners formed by the opposing sides of the first lead frame and the second lead frame and the other sides connected to the opposing sides are formed with R-shaped chamfers.

7. The semiconductor device as described in claim 1 or 2, characterized in that: The corners formed by the opposing sides of the first lead frame and the second lead frame and the main surface connected to the opposing sides are formed with R-shaped chamfers.

8. The semiconductor device as described in claim 1 or 2, characterized in that: The first semiconductor chip includes a control chip and a transformer chip. The transformer chip internally converts the electrical signal output by the control chip into magnetic force, then converts the magnetic force back into an electrical signal and outputs it. The second semiconductor chip, which receives the electrical signal output by the transformer chip, is controlled by the control chip, and the drive chip, which acts as a drive switching element, performs its operation.

9. The semiconductor device as claimed in claim 8, characterized in that: The transformer chip is positioned between the control chip and the drive chip. The surface of the transformer chip opposite to the driver chip and the surface of the connecting wire that electrically connects the transformer chip and the driver chip are covered by the insulating protective film.

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