Switch control circuit, semiconductor device

Abstract

The switch control circuit of the present invention controls the switching of the switch element, and includes: a detection circuit, which detects whether the current flowing through the switch element is in an overcurrent state; a first signal output circuit, which outputs a first signal indicating whether the period of the overcurrent state is longer than the first period; and a drive circuit, which turns on the switch element based on a first input signal for turning on the switch element, and turns off the switch element via the first switch based on a second input signal for turning off the switch element when the period of the overcurrent state is shorter than the first period, and turns off the switch element via a second switch having an on-resistance larger than that of the first switch based on the second input signal and the first signal when the period of the overcurrent state is longer than the first period.

Description

Technical Field

[0001] The present invention relates to a switch control circuit and a semiconductor device. Background Art

[0002] There is an overcurrent protection circuit that protects a switching element from an overcurrent flowing through the switching element (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-45598 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] In addition, in an overcurrent protection circuit, when the overcurrent continues for a specified period, the switch element is generally turned off. However, since the overcurrent protection circuit does not operate until the specified period has passed, the switch element may be damaged. If the specified period is shortened to prevent damage to the switch element, the overcurrent protection circuit may also operate due to noise components.

[0008] The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a switch control circuit capable of appropriately protecting a switch element from an overcurrent.

[0009] Technical means for solving technical problems

[0010] A first mode of a switch control circuit of the present invention for solving the above-mentioned problem is a switch control circuit for controlling the switching of a switch element, comprising: a detection circuit for detecting whether a current flowing through the switch element is in an overcurrent state; a first signal output circuit for outputting a first signal indicating whether a period of the overcurrent state is longer than a first period; and a drive circuit for turning on the switch element based on a first input signal for turning on the switch element, and turning off the switch element via a first switch based on a second input signal for turning off the switch element when the period of the overcurrent state is shorter than the first period, and turning off the switch element via a second switch having an on-resistance larger than that of the first switch based on the second input signal and the first signal when the period of the overcurrent state is longer than the first period.

[0011] In addition, a second mode of the switch control circuit of the present invention is a switch control circuit that controls the switching of a switch element, and includes: a detection circuit that detects an overcurrent state in which a current flowing through the switch element is larger than a specified current; a first signal output circuit that outputs a first signal indicating whether the period of the overcurrent state is longer than a first period; a second signal output circuit that outputs a second signal indicating whether the period of the overcurrent state is longer than a second period that is longer than the first period; and a drive circuit that drives the switch element based on the first signal and the second signal, a first input signal for turning on the switch element, and a second input signal for turning off the switch element, wherein the drive circuit drives the switch element during the overcurrent state. When the period of the overcurrent state is longer than the second period, the switching element is turned off based on the second signal indicating that the period of the overcurrent state is longer than the second period, regardless of the first input signal and the second input signal; when the period of the overcurrent state is shorter than the first period, the switching element is turned on based on the first input signal, and the switching element is turned off via the first switch based on the second input signal; when the period of the overcurrent state is longer than the first period and shorter than the second period, the switching element is turned on based on the first input signal, and the switching element is turned off via the second switch having an on-resistance larger than that of the first switch based on the first signal indicating that the period of the overcurrent state is longer than the first period and the second input signal.

[0012] A semiconductor device method of the present invention includes: a switching element; a detection circuit, which detects whether the current flowing through the switching element is in an overcurrent state; a first signal output circuit, which outputs a first signal indicating whether the period of the overcurrent state is longer than the first period; and a driving circuit, which turns on the switching element based on a first input signal for turning on the switching element, turns off the switching element via the first switch based on a second input signal for turning off the switching element when the period of the overcurrent state is shorter than the first period, and turns off the switching element via a second switch having an on-resistance larger than that of the first switch based on the second input signal and the first signal when the period of the overcurrent state is longer than the first period.

[0013] Effects of the Invention

[0014] According to the present invention, a switch control circuit can be provided which can appropriately protect a switch element from an overcurrent. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1is a diagram showing an example of the structure of the power module 10 .

[0016] Figure 2 : is a diagram showing an example of a PWM-controlled drive signal Vldru.

[0017] Figure 3 is a diagram showing an example of the structure of the LVIC 24 .

[0018] Figure 4 is a diagram showing an example of the configuration of the switch control circuit 51 .

[0019] Figure 5 1 is a diagram showing an example of the operation of the switch control circuit 51 .

[0020] Figure 6 1 is a diagram showing an example of the operation of the switch control circuit 51 .

[0021] Figure 7 1 is a diagram showing an example of the operation of the switch control circuit 51 . DETAILED DESCRIPTION

[0022] Cross-reference to related applications

[0023] This application claims priority based on Japanese Patent Application No. 2020-002615 filed on January 10, 2020, and cites the contents thereof.

[0024] At least the following matters are clarified from the description of this specification and the drawings.

[0025] ======Present Implementation Method======

[0026] Figure 1 1 is a diagram showing an example of the structure of a power module 10 which is one embodiment of the present invention. The power module 10 is a semiconductor device for driving a three-phase motor 11, and includes HVICs 21 to 23, LVICs 24, a bridge circuit 30 for power conversion, and terminals HU, HV, HW, LU, LV, LW, P, U, V, W, NU, NV, and NW.

[0027] The bridge circuit 30 includes IGBTs (Insulated Gate Bipolar Transistors) 31 to 36 and FWDs (Free Wheeling Diodes) 41 to 46. The IGBTs 31 to 36 include sensor IGBTs for detecting currents flowing through the IGBTs 31 to 36, but these are omitted for convenience of description.

[0028] The IGBTs 31 and 32 are switching elements of the U phase, and the IGBTs 31 and 32 are provided with FWDs 41 and 42 , respectively.

[0029] The IGBTs 33 and 34 are switching elements of the V phase, and the IGBTs 33 and 34 are provided with FWDs 43 and 44 , respectively.

[0030] The IGBTs 35 and 36 are switching elements of the W phase, and the IGBTs 35 and 36 are provided with FWDs 45 and 46 , respectively.

[0031] A power supply voltage Vdc from a DC power supply 13 is applied to the terminal P, a load, namely, a three-phase motor 11 is provided to the terminals U, V, and W, and the terminals NU, NV, and NW are grounded.

[0032] A capacitor 12 for stabilizing the power supply voltage Vdc is connected between the terminal P and the terminals NU, NV, and NW.

[0033] The HVICs (High Voltage Integrated Circuits) 23 to 23 are integrated circuits for switching the IGBTs 31 , 33 , 35 of the upper arms according to drive signals Vhdru, Vhdrv, Vhdrw input from a microcomputer (not shown) via terminals HU, HV, HW, respectively.

[0034] The LVIC (Low Voltage Integrated Circuit) 24 is an integrated circuit for switching the IGBTs 32 , 34 , 36 of the lower arm according to drive signals Vldru, Vldrv, Vldrw input from a microcomputer (not shown) via terminals LU, LV, LW.

[0035] The microcomputer (not shown) inputs PWM-controlled drive signals Vhdru, Vhdrv, and Vhdrw with varying duty ratios to terminals HU, HV, and HW, respectively. The drive signals Vhdru, Vhdrv, and Vhdrw are signals that turn on the IGBTs 31, 33, and 35, respectively, when they are at a high level (hereinafter referred to as an "H" level), and turn off the IGBTs 31, 33, and 35, respectively, when they are at a low level (hereinafter referred to as an "L" level).

[0036] Terminals LU, LV, and LW receive PWM-controlled drive signals Vldru, Vldrv, and Vldrw, respectively. The drive signals Vldru, Vldrv, and Vldrw are signals that turn on IGBTs 32, 34, and 36 when at an "L" level and turn off IGBTs 32, 34, and 36 when at an "H" level.

[0037] The IGBTs 31 and 32 are complementarily driven by drive signals Vhdru and Vldru, the IGBTs 33 and 34 are complementarily driven by drive signals Vhdrv and Vldrv, and the IGBTs 35 and 36 are complementarily driven by drive signals Vhdrw and Vldrw.

[0038] The microcomputer (not shown) of the present embodiment changes the timing and duty ratio of the drive signals Vhdru, Vhdrv, Vhdrw, Vldru, Vldrv, and Vldrw so that the current flowing through the three-phase motor 11 becomes a sinusoidal wave with phases different by 120 degrees from each other.

[0039] As a result, the period of the "L" level of the drive signal Vldru (i.e., the period during which the IGBT 32 is turned on) is as follows: Figure 2 Changes as shown.

[0040] The terminal COM is a terminal to which a ground voltage is applied, and is connected to, for example, a case (not shown) of the power module 10 .

[0041] <<LVIC24>>

[0042] Figure 3 : is a diagram showing an example of the structure of LVIC24. LVIC24 is configured to include switch control circuits 51 to 53. Switch control circuit 51 drives IGBT32 based on drive signal Vldru input to terminal UIN. Switch control circuit 52 drives IGBT34 based on drive signal Vldrv input to terminal VIN. Switch control circuit 53 drives IGBT36 based on drive signal Vldrw input to terminal WIN. In addition, switch control circuits 51 to 53 are applied with power supply voltage from terminal VCC and ground voltage from terminal GND. In addition, switch control circuits 51 to 53 are configured with the same circuit.

[0043] <<Switch control circuit 51>>

[0044] Figure 4 2 is a diagram showing an example of the configuration of the switch control circuit 51. The switch control circuit 51 includes a detection circuit 61, a first filter circuit 62, a second filter circuit 63, and a drive circuit 64.

[0045] <<<Detection circuit 61>>>

[0046] The detection circuit 61 is a circuit for detecting the current from the emitter of the current sensor IGBT 37. The detection circuit 61 includes a resistor 71, reference voltage circuits 72 and 74, and comparators 73 and 75.

[0047] In addition, the gate terminal of IGBT37 is applied with the same voltage as the voltage applied to the gate terminal of IGBT32, and the collector terminal is connected to the collector terminal of IGBT32. In addition, the ratio of the transistor size of IGBT37 to that of IGBT32 is, for example, 1:10000. Therefore, about one ten-thousandth of the current flowing between the collector and emitter of IGBT32 flows between the collector and emitter of IGBT37. Therefore, the current is output from the emitter terminal of IGBT37 according to the current flowing through IGBT32, so the current output from the emitter terminal of IGBT37 is detected to detect the overcurrent state of IGBT32.

[0048] When the current from the IGBT 37 flows, the resistor 71 generates a voltage Vr corresponding to the current at one end. In addition, the other end of the resistor 71 is grounded. For the sake of convenience, the resistor 71 is described as one, but when there are multiple IGBTs 37 for sensing the current flowing through the IGBT 32, there may be multiple resistors 71 in each of the IGBTs 37. When there are multiple resistors 71, the voltage Vr generated by the resistor 71 that is different for each comparator can be applied to the non-inverting input terminal of the multiple comparators.

[0049] The reference voltage circuit 72 is a circuit that generates a reference voltage VREF2 based on the power supply voltage Vcc, for example, and provides the reference voltage VREF2 to the comparator 73. In addition, the reference voltage circuit 74 also generates a reference voltage VREF3 in the same manner. In addition, the reference voltage VREF2 and the reference voltage VREF3 are the same voltage level in the present embodiment, but may be different voltage levels.

[0050] The comparator 73 is a circuit that compares the voltage Vr with the reference voltage VREF2 and outputs an output signal Vc1 to detect an overcurrent state. The voltage Vr is applied to the non-inverting input terminal of the comparator 73, and the reference voltage VREF2 generated by the reference voltage circuit 72 is applied to the inverting input terminal. In addition, the reference voltage VREF2 is set to be equal to the voltage Vr generated by the resistor 71 when a predetermined current indicating an overcurrent flows through the IGBT 37.

[0051] If the current from the IGBT 37 flows through the resistor 71 and the voltage Vr becomes higher than the reference voltage VREF2, the comparator 73 outputs an output signal Vc1 of the "H" level. On the other hand, if the current from the IGBT 37 flows through the resistor 71 and the voltage Vr becomes lower than the reference voltage VREF2, the comparator 73 outputs an output signal Vc1 of the "L" level. That is, the comparator 73 compares the current flowing through the IGBT 32 with a specified current indicating an overcurrent, and when the current flowing through the IGBT 32 is larger than the specified current, the comparator 73 outputs an output signal Vc1 indicating that the current flowing through the IGBT 32 is in an overcurrent state.

[0052] Similarly, the voltage Vr is applied to the non-inverting input terminal of the comparator 75, and the reference voltage VREF3 generated by the reference voltage circuit 74 is applied to the inverting input terminal. Therefore, the comparator 75 operates in the same manner as the comparator 73.

[0053] Thus, the detection circuit 61 detects whether the current flowing through the IGBT 32 is in an overcurrent state.

[0054] In addition, the detection circuit 61 is described as including the comparators 73 and 75. However, since the reference voltage VREF2 and the reference voltage VREF3 are the same voltage level in the present embodiment, the detection circuit 61 may include only one comparator instead of including the comparators 73 and 75. In addition, in this case, the output signal of one comparator can be input to the first filter circuit 62 and the second filter circuit 63 described later. In addition, the gate terminal of the IGBT32 is equivalent to the "control electrode". In addition, the comparator 73 is equivalent to the "first comparison circuit", and the comparator 75 is equivalent to the "second comparison circuit". In addition, the output signal Vc1 is equivalent to the "first comparison result", and the output signal Vc2 is equivalent to the "second comparison result". In addition, the specified current indicating the overcurrent is equivalent to the "first current value", "the second current value" or the "specified current".

[0055] <<<First filter circuit 62>>>

[0056] The first filter circuit 62 is a circuit that outputs an output signal Vf1 when the output signal Vc1 of the comparator 73 is output for a period longer than the "first period T1". The "first period T1" is longer than the period during which noise is generated when the IGBT 32 is turned on. In addition, when the output signal Vc1 becomes "L" level, the output signal Vf1 becomes "L" level.

[0057] That is, when IGBT32 is turned on and overcurrent flows through IGBT32 during the "first period T1", the output signal Vf1 becomes "H" level, and then, when IGBT32 is turned off and overcurrent no longer flows through IGBT32, the output signal Vf1 becomes "L" level.

[0058] Therefore, the first filter circuit 62 outputs an output signal Vf1 indicating whether the period of the overcurrent state is longer than the "first period T1" based on the output signal Vc1 for detecting whether the current flowing through the IGBT 32 is in the overcurrent state. In addition, the first filter circuit 62 is equivalent to the "first signal output circuit". In addition, the output signal Vf1 is equivalent to the "first signal".

[0059] <<<Second filter circuit 63>>>

[0060] The second filter circuit 63 is a circuit that outputs an output signal Vf2 when the output signal Vc2 of the comparator 75 is output for a period longer than the "second period T2". The "second period T2" is longer than the "first period T1". In addition, when the output signal Vc2 becomes the "L" level, the output signal Vf2 becomes the "L" level.

[0061] That is, when IGBT32 is turned on and overcurrent flows through IGBT32 during the "second period T2", the output signal Vf2 becomes "H" level, and then, when IGBT32 is turned off and overcurrent no longer flows through IGBT32, the output signal Vf2 becomes "L" level.

[0062] Therefore, the second filter circuit 63 outputs an output signal Vf2 indicating whether the period of the overcurrent state is longer than the "second period T2" based on the output signal Vc2 for detecting whether the current flowing through the IGBT 32 is in the overcurrent state. In addition, the second filter circuit 63 is equivalent to the "second signal output circuit". In addition, the output signal Vf2 is equivalent to the "second signal".

[0063] <<<Drive circuit 64>>>

[0064] The drive circuit 64 turns the IGBT 32 on or off based on the output signals Vf1 and Vf2 and the drive signal Vldru. The drive circuit 64 includes a current generating circuit 81 , a discharge circuit 82 , a D flip-flop 83 , a switch circuit 84 , an SR flip-flop 87 , and a timer circuit 88 .

[0065] <<<<Current generating circuit 81>>>>

[0066] The current generating circuit 81 generates a current for charging the capacitance of the gate terminal of the IGBT 32. The current generating circuit 81 includes a voltage dividing circuit 91, an operational amplifier 92, NMOS transistors 93, 97, and 98, a resistor 94, and PMOS transistors 95 and 96.

[0067] The reference voltage Vs generated by the voltage divider circuit 91 based on the reference voltage VREF1 is applied to the non-inverting input terminal of the operational amplifier 92. The inverting input terminal of the operational amplifier 92 is connected to one end of a resistor 94 and a source terminal of an NMOS transistor 93, wherein the resistor 94 is used to detect the current I1 flowing through the NMOS transistor 93 and the PMOS transistor 95.

[0068] Current is supplied from the diode-connected PMOS transistor 95 to the NMOS transistor 93. Then, the operational amplifier 92 controls the NMOS transistor 93 so that the voltage of the inverting input terminal becomes the reference voltage Vs applied to the non-inverting input terminal.

[0069] As a result, a current I1 determined by the reference voltage Vs and the resistance value of the resistor 94 flows through the diode-connected PMOS transistor 95 .

[0070] The PMOS transistors 95 and 96 form a current mirror circuit. Therefore, a current I2 corresponding to the current I1 flowing through the PMOS transistor 95 flows through the PMOS transistor 96 .

[0071] In addition, if at least one of the NMOS transistors 97 and 98 is turned on, the ground voltage is applied to the gate terminal of the NMOS transistor 93, and as a result, the NMOS transistor 93 is turned off, and the currents I1 and I2 do not flow. On the other hand, when the drive signal Vldru and the output signal Vsq of the SR flip-flop 87 described later are at the "L" level, the currents I1 and I2 flow, and the IGBT 32 is turned on. In addition, the drive signal Vldru at the "L" level corresponds to the "first input signal", and the drive signal Vldru at the "H" level corresponds to the "second input signal".

[0072] <<<<Discharge circuit 82>>>>

[0073] The discharge circuit 82 is a circuit for applying a ground voltage to a gate terminal of the IGBT 32 to turn off the IGBT 32. The discharge circuit 82 includes NMOS transistors 101, 102, and 103.

[0074] The drain terminals of the NMOS transistors 101, 102, and 103 are respectively connected to the gate terminal of the IGBT 32, and the source terminals are grounded. The details are described later, but the voltages Vs1, Vs2, and Vs3 controlled based on the drive signal Vldru, the output signal Vdq of the D flip-flop 83 described later, and the output signal Vsq of the SR flip-flop 87 are respectively applied to the gate terminals of the NMOS transistors 101, 102, and 103. In addition, in the present embodiment, the on-resistance of the NMOS transistors 102 and 103 is greater than the on-resistance of the NMOS transistor 101. In addition, the NMOS transistor 101 is equivalent to the "first switch", the NMOS transistor 103 is equivalent to the "second switch", and the NMOS transistor 102 is equivalent to the "third switch".

[0075] <<<<D flip-flop 83>>>>

[0076] The D flip-flop 83 is a circuit that holds the output signal Vf1 of the first filter circuit 62 at the rising edge of the drive signal Vldru (ie, the timing when the IGBT 32 is switched from on to off) and outputs the output signal Vdq. The D flip-flop 83 corresponds to a "first holding circuit".

[0077] <<<<Switch circuit 84>>>>

[0078] The switch circuit 84 is a circuit that controls the voltages Vs1 and Vs2 based on the logic level of the output signal Vdq of the D flip-flop 83 and controls the NMOS transistors 101 and 103. The switch circuit 84 includes AND gate elements 85 and 86.

[0079] When the output signal Vdq is at the "H" level, that is, when the period of the overcurrent state is longer than the "first period T1", the AND gate element 85 controls the voltage Vs2 for driving the NMOS transistor 103 based on the drive signal Vldru, and controls the IGBT 32 via the NMOS transistor 103. On the other hand, when the output signal Vdq is at the "L" level, that is, when the period of the overcurrent state is shorter than the "first period T1", the AND gate element 85 sets the voltage Vs2 to the "L" level and turns off the NMOS transistor 103.

[0080] When the output signal Vdq is at the "H" level, that is, when the period of the overcurrent state is longer than the "first period T1", the voltage Vs1 becomes the "L" level, and the AND gate element 86 turns off the NMOS transistor 101. On the other hand, when the output signal Vdq is at the "L" level, that is, when the period of the overcurrent state is shorter than the "first period T1", the AND gate element 86 controls the NMOS transistor 101 based on the drive signal Vldru, and controls the IGBT32 via the NMOS transistor 101.

[0081] <<<<SR flip-flop 87 and timer circuit 88>>>>

[0082] If a pulse signal is output from the second filter circuit 63 as the output signal Vf2, the SR flip-flop 87 sets the output signal Vsq to the "H" level. In addition, the output signal Vsq is input to the timer circuit 88, and the timer circuit 88 delays the output signal Vsq by the "predetermined period T0" and outputs the output signal Vt0. If the output signal Vt0 is output, the SR flip-flop 87 is reset, and as a result, the SR flip-flop 87 outputs the output signal Vsq at the "L" level. That is, if the period during which the output signal Vsq is at the "H" level is longer than the "predetermined time T0", the output signal Vt0 is output, and the output signal Vsq is reset to the "L" level. In addition, the timer circuit 88 is equivalent to a "reset circuit", and the "predetermined time T0" is equivalent to the "predetermined period".

[0083] In addition, the output signal Vsq is input to the gate terminal of the NMOS transistor 98 of the current generating circuit 81 and the gate terminal of the NMOS transistor 102 of the discharge circuit 82. In addition, when the output signal Vsq is at the "H" level, the NMOS transistor 98 is turned on to stop the generation of the current I2, and the NMOS transistor 102 is turned on to turn off the IGBT 32, regardless of the drive signal Vldru. In addition, the NMOS transistor 102 is turned off during the period when the output signal Vsq of the SR flip-flop 87 maintains the "H" level. In addition, the SR flip-flop 87 is equivalent to the "second holding circuit".

[0084] <Operation of Switch Control Circuit 51>

[0085] <<When the period of the overcurrent state is shorter than the "first period T1" and the "second period T2">>

[0086] Figure 5: is a diagram showing an example of the operation of the switch control circuit 51. Here, the case where the period of the overcurrent state is shorter than the "first period T1" and the "second period T2" is described. It is assumed that the overcurrent state does not occur before time t0, and the output signal Vf1 of the first filter circuit 62 maintains the "L" level. Similarly, it is assumed that the output signal Vf2 of the second filter circuit 63 also maintains the "L" level. Since the output signal Vf1 is at the "L" level, the output signal Vdq of the D flip-flop 83 is at the "L" level. In addition, it is assumed that the output signal Vsq of the SR flip-flop 87 has been reset to the "L" level.

[0087] In this case, the output signal Vdq is at "L" level, so the NMOS transistor 101 is controlled based on the drive signal Vldru, and the NMOS transistor 103 is turned off. The output signal Vsq is at "L" level, so the NMOS transistors 98 and 102 are turned off.

[0088] If the drive signal Vldru becomes the "L" level at time t0, the NMOS transistor 97 is turned off, and the current generating circuit 81 generates the current I2. The signal Vs1 input to the gate terminal of the NMOS transistor 101 becomes the "L" level based on the drive signal Vldru, and the NMOS transistor 101 is turned off. As a result, the current I2 from the current generating circuit 81 is supplied to the gate terminal of the IGBT32. If the current I2 is supplied, the voltage Vg of the gate terminal of the IGBT32 rises at a constant slope. As a result, the IGBT32 is turned on, and the current containing noise flows through the IGBT32 and the parasitic components of the circuit. If the current containing noise flows, the voltage Vr generated by the resistor 71 is temporarily greater than the reference voltage VREF2. As a result, the output signals Vc1 and Vc2 of the comparators 73 and 75 become the "H" level.

[0089] At time t1, the noise when IGBT32 turns on disappears, so the output signals Vc1 and Vc2 of comparators 73 and 75 become "L" level. Here, the period during which the output signal Vc1 is at the "H" level is shorter than the "first period T1", so the output signal Vf1 maintains the "L" level, and as a result, the output signal Vdq maintains the "L" level. Similarly, the period during which the output signal Vc2 is at the "H" level is shorter than the "second period T2", so the output signal Vf2 maintains the "L" level. Therefore, the output signal Vsq maintains the "L" level. In addition, the period from time t0 to t1 is the "noise period Tn", which is equivalent to the "period during which noise is generated when the switching element is turned on".

[0090] If the drive signal Vldru becomes "H" level at time t2, the NMOS transistor 98 remains off, but the NMOS transistor 97 is turned on, so the current generating circuit 81 stops generating the current I2. The signal Vs1 input to the gate terminal of the NMOS transistor 101 becomes "H" level based on the drive signal Vldru, and the NMOS transistor 101 is turned on. In addition, the output signal Vsq is "L" level, and the output signal of the AND gate element 85 is "L" level, so the NMOS transistors 102 and 103 are turned off. Then, the gate terminal of the IGBT 32 is grounded via the NMOS transistor 101, and the IGBT 32 is turned off. As a result, the voltage Vr generated by the resistor 71 becomes the ground voltage.

[0091] At time t3, the drive signal Vldru becomes "H" level again. Thereafter, the operation from time t0 to time t2 is repeated.

[0092] The driving signal Vldru at the “L” level corresponds to the “first input signal”, and the driving signal Vldru at the “H” level corresponds to the “second input signal”.

[0093] Thus, when an overcurrent does not flow through the IGBT 32 , the switch control circuit 51 drives the IGBT 32 based on the drive signal Vldru.

[0094] <<When the period of the overcurrent state is longer than the "first period T1" and shorter than the "second period T2">>

[0095] Figure 6 1 is a diagram showing an example of the operation of the switch control circuit 51. Here, the case where the period of the overcurrent state is longer than the "first period T1" and shorter than the "second period T2" is described. The state of the switch control circuit 51 before time t10 is the same as that of the first period T2. Figure 5 The state before the moment t0 is the same.

[0096] When the drive signal Vldru becomes "L" level at time t10, the switch control circuit 51 and Figure 5 The operation is performed in the same manner as the case at time t0. As a result, the IGBT 32 is turned on, and a current including noise flows through the IGBT 32.

[0097] At time t11, an overcurrent flows through the IGBT 32, so the output signal Vc1 maintains the "H" level from time t10. If the period of the overcurrent state from time t10 exceeds the "first period T1", the output signal Vf1 becomes the "H" level at time t11. At this time, the period of the overcurrent state does not exceed the "second period T2", so the output signal Vf2 maintains the "L" level.

[0098] If the drive signal Vldru becomes "H" level at time t12, the D flip-flop 83 holds the signal Vf1 and sets the output signal Vdq to "H" level. Then, the NMOS transistor 97 is turned on, and the current generating circuit 81 stops generating the current I2. The output signal of the AND gate element 86 becomes "L" level, and therefore, the output signal of the AND gate element 85 becomes "H" level, instead of turning on the NMOS transistor 101, so the signal Vs2 input to the gate terminal of the NMOS transistor 103 becomes "H" level. Then, the gate terminal of the IGBT 32 is grounded via the NMOS transistor 103, and the IGBT 32 is turned off. As a result, the voltage Vr generated by the resistor 71 becomes the ground voltage.

[0099] When the drive signal Vldru becomes "H" level, the IGBT32 is turned off and the current flowing through the IGBT32 disappears. However, the output signal Vf1 indicating that the overcurrent flows through the IGBT32 does not immediately become "L" level, and the D flip-flop 83 can hold the output signal Vf1.

[0100] Furthermore, since the on-resistance of the NMOS transistor 103 is larger than that of the NMOS transistor 101, the amount of voltage change per unit time at the gate terminal of the IGBT 32 when the IGBT 32 is turned off by the NMOS transistor 103 is smaller than when the IGBT 32 is turned off by the NMOS transistor 101. Thus, when the IGBT 32 is turned off, the amount of change per unit time of the current flowing through the IGBT 32 is reduced, and damage to the IGBT 32 due to the surge voltage can be suppressed.

[0101] At time t13, the drive signal Vldru becomes "L" level again. After that, the operation at time t10 to t12 is repeated. However, each time the IGBT 32 is turned on, the period of the overcurrent state exceeds the "first period T1", so the output signal Vdq of the D flip-flop 83 maintains the "H" level after time t13.

[0102] Therefore, when the period of the overcurrent state is longer than the “first period T1 ” and shorter than the “second period T2 ”, the switch control circuit 51 turns on the IGBT 32 based on the drive signal Vldru and turns off the IGBT 32 via the NMOS transistor 103 .

[0103] <<When the period of the overcurrent state is longer than the "first period T1" and the "second period T2">>

[0104] Figure 7 1 is a diagram showing an example of the operation of the switch control circuit 51. Here, the case where the period of the overcurrent state is longer than the "first period T1" and the "second period T2" is described. The state of the switch control circuit 51 before time t20 is the same as Figure 5 The state before the moment t0 is the same.

[0105] When the drive signal Vldru becomes "L" level at time t20, the switch control circuit 51 and Figure 5 As a result, the IGBT 32 is turned on, a current including noise flows through the IGBT 32, and the output signal Vc2 becomes "H" level.

[0106] If the period of the overcurrent state exceeds the "first period T1" and the "second period T2" at time t21, the output signals Vf1 and Vf2 become "H" level, and the output signal Vsq of the SR flip-flop 87 becomes "H" level. As a result, the NMOS transistor 98 is turned on, and the current generating circuit 81 stops generating the current I2. The output signal Vsq becomes "H" level, so the voltage Vs3 input to the gate terminal of the NMOS transistor 102 becomes "H" level, and the NMOS transistor 102 is turned on. In addition, the output signal of the AND gate element 86 is "L" level, so the NMOS transistor 101 is turned off, and the output signal of the AND gate element 85 is "L" level, so the NMOS transistor 103 is turned off. As a result, the gate terminal of the IGBT 32 is grounded via the NMOS transistor 102, and the IGBT 32 is turned off.

[0107] Furthermore, since the on-resistance of the NMOS transistor 102 is larger than that of the NMOS transistor 101, the amount of voltage change per unit time at the gate terminal of the IGBT 32 when the IGBT 32 is turned off by the NMOS transistor 102 is smaller than when the IGBT 32 is turned off by the NMOS transistor 101. As a result, when the IGBT 32 is turned off, the amount of change per unit time of the current flowing through the IGBT 32 is reduced, and damage to the IGBT 32 due to the surge voltage can be suppressed.

[0108] When the voltage Vr generated by the resistor 71 becomes lower than the reference voltage VREF3 at time t22, the output voltage Vc2 becomes "L" level, and the output voltage Vf2 also becomes "L" level.

[0109] When the IGBT 32 is turned off at time t23 , the voltage Vr generated by the resistor 71 becomes the ground voltage.

[0110] Even when the drive signal Vldru becomes the “H” level at time t24 , the output signal Vf1 becomes the “L” level similarly to the output signal Vf2 , and therefore the output signal Vdq maintains the “L” level.

[0111] Since the output signal Vsq is at the “H” level from the time t21 until the “predetermined time T0” has passed, even if the drive signal Vldru is at the “L” level, the IGBT 32 is not turned on and the voltage Vr is kept at the ground voltage.

[0112] When the “predetermined time T0” elapses and the output signal Vsq is reset, the switch control circuit 51 operates again based on whether the period of the overcurrent state is longer than the “first period T1” or the “second period T2”.

[0113] Thus, when the period of the overcurrent state is longer than the “second period T2 ”, the switch control circuit 51 turns off the IGBT 32 during the “predetermined time T0 ”.

[0114] Therefore, the switch control circuit 51 can protect the IGBT 32 from overcurrent.

[0115] ===Others===

[0116] The switch control circuit 51 of the present embodiment is used for the LVIC 24 , but the switch control circuit 51 may also be used for the HVICs 21 to 23 to protect the IGBTs 31 , 33 , and 35 from overcurrent.

[0117] The switch control circuit 51 of the present embodiment has been described as protecting the IGBT 32 from overcurrent, but other than the IGBT, power MOSFETs and the like may be protected from overcurrent.

[0118] ===Summary===

[0119] The power module 10 of the present embodiment has been described above. The switch control circuit 51 switches whether to turn off the IGBT 32 by the NMOS transistor 101 or by the NMOS transistor 103 based on the output signal Vf1 of the first filter circuit 62. The on-resistance of the NMOS transistor 103 is larger than the on-resistance of the NMOS transistor 101, so the amount of change per unit time of the current flowing through the IGBT 32 when the IGBT 32 is turned off is reduced, and as a result, the surge voltage when the IGBT 32 is turned off is suppressed. As a result, the IGBT 32 can be properly protected from the influence of overcurrent.

[0120] If the overcurrent state lasts longer than the first period T1, the first filter circuit 62 sets the output signal Vf1 to the "H" level. By making the first period T1 longer than the period during which noise generated when the IGBT 32 is turned on exists, it is possible to prevent noise from being detected as overcurrent.

[0121] Furthermore, at the rising edge of the drive signal Vldru, the D flip-flop 83 holds the output signal Vf1 of the first filter circuit 62 , thereby appropriately detecting the state of the current flowing through the IGBT 32 when the IGBT 32 is turned off, and performing overcurrent protection.

[0122] Furthermore, when the overcurrent state lasts longer than the second period T2 which is longer than the first period T1, the switch control circuit 51 turns off the IGBT 32 regardless of the drive signal Vldru. This prevents the IGBT 32 from being damaged by overcurrent flowing through it for a long time.

[0123] In addition, the SR flip-flop 87 holds the output signal Vf2 of the second filter circuit 63 and outputs an output signal Vsq of the "H" level. With this output, the switch control circuit 51 turns off the IGBT 32 by using an NMOS transistor 102 having a larger on-resistance than the NMOS transistor 101 instead of the NMOS transistor 101. As a result, the change per unit time of the current flowing through the IGBT 32 when the IGBT 32 is turned off is reduced, and as a result, the surge voltage when the IGBT 32 is turned off is suppressed. As a result, the IGBT 32 can be properly protected from the influence of overcurrent. In addition, by notifying the microcomputer (not shown) of the output signal Vsq of the SR flip-flop 87, the microcomputer (not shown) can be notified that the period of the overcurrent state lasts longer than the "second period T2". On the other hand, the microcomputer (not shown) that receives the notification can change the control of the power module 10 to eliminate the overcurrent state.

[0124] In addition, after receiving the output signal Vsq at the "H" level, the timer circuit 88 outputs the output signal Vt0 after the "predetermined time T0". Based on the output signal Vt0, the SR flip-flop 87 is reset. As a result, even if an overcurrent state occurs, the power module 10 resumes operation after the "predetermined time T0". As a result, the system equipped with the power module 10 operates without stopping operation.

[0125] Furthermore, if the detection circuit 61 includes the comparators 73 and 75 , the detection values ​​of the current flowing through the IGBT 32 can be changed respectively, and more appropriate overcurrent protection can be performed according to the application example.

[0126] In addition, if the switch control circuit 51 is constructed to include a detection circuit 61, a first filter circuit 62, a second filter circuit 63, and a drive circuit 64, overcurrent protection can be more appropriately performed by utilizing the combination of the "first period T1" measured by the first filter circuit 62 and the "second period T2" measured by the second filter circuit 63.

[0127] Furthermore, the power module 10 including the IGBT 32 , the detection circuit 61 , the first filter circuit 62 , the second filter circuit 63 , and the drive circuit 64 is suitable for protecting the IGBT 32 from overcurrent.

[0128] The above-mentioned embodiments are for facilitating understanding of the present invention, and are not intended to limit the present invention. In addition, the present invention can be changed or improved without departing from the gist thereof, and the present invention naturally includes its equivalents.

[0129] Description of symbols

[0130] 10 Power Module

[0131] 11 Three-phase motor

[0132] 12. Capacitor

[0133] 13 DC Power Supply

[0134] 21, 22, 23 HVIC

[0135] 24 LVIC

[0136] 30 Bridge Circuit

[0137] 31~36 IGBT

[0138] 37 IGBT for current sensor

[0139] 41~46 FWD

[0140] 51~53 switch control circuit

[0141] 61 Detection circuit

[0142] 62 1st filter circuit

[0143] 63 Second filter circuit

[0144] 64 drive circuit

[0145] 71, 94 resistor

[0146] 72, 74 Reference voltage circuit

[0147] 73, 75 Comparator

[0148] 81 Current generation circuit

[0149] 82 Discharge circuit

[0150] 83 D Flip Flop

[0151] 84 Switching Circuit

[0152] 85, 86 AND gate element

[0153] 87 SR Trigger

[0154] 88 Timer Circuit

[0155] 91 voltage divider circuit

[0156] 92 Operational Amplifier

[0157] 93, 98, 97, 101, 102, 103 NMOS transistors

[0158] 95, 96 PMOS transistors.

Claims

1. A switch control circuit, The switch of the switch element is controlled, characterized in that: include: A detection circuit, the detection circuit detecting whether the current flowing through the switch element is in an overcurrent state; a first signal output circuit that outputs a first signal indicating whether the period of the overcurrent state is longer than a first period; A driving circuit, the driving circuit comprising a first switch, a second switch having an on-resistance greater than that of the first switch, and a first holding circuit, the driving circuit turning on the switching element based on a first input signal for turning on the switching element, turning off the switching element via the first switch based on a second input signal for turning off the switching element when the period of the overcurrent state is shorter than the first period, receiving the first signal from the first signal output circuit, holding the first signal in the first holding circuit when the second input signal is input, and turning off the switching element via the second switch based on the second input signal and the first signal when the period of the overcurrent state is longer than the first period; as well as A second signal output circuit outputs a second signal indicating whether a period of the overcurrent state is longer than a second period longer than the first period.

2. The switch control circuit according to claim 1, characterized in that: The first period is longer than a period during which noise is generated when the switching element is turned on.

3. The switch control circuit according to claim 2, characterized in that: The first switch is provided between the control electrode of the switch element and the ground. The second switch is provided between the control electrode of the switch element and the ground. The driving circuit includes a switching circuit that turns on the first switch based on the second input signal when the first holding circuit holds the first signal indicating that the period during which the overcurrent state is shorter than the first period, and turns on the second switch based on the second input signal when the first holding circuit holds the first signal indicating that the overcurrent state is longer than the first period.

4. The switch control circuit according to claim 1, characterized in that: The first switch is provided between the control electrode of the switch element and the ground. The second switch is provided between the control electrode of the switch element and the ground. The driving circuit includes a switching circuit that turns on the first switch based on the second input signal when the first holding circuit holds the first signal indicating that the period during which the overcurrent state is shorter than the first period, and turns on the second switch based on the second input signal when the first holding circuit holds the first signal indicating that the overcurrent state is longer than the first period.

5. The switch control circuit according to any one of claims 1 to 4, characterized in that: The drive circuit turns off the switching element based on the second signal indicating that the period of the overcurrent state is longer than the second period, regardless of the first input signal and the second input signal.

6. The switch control circuit according to claim 5, characterized in that: The driving circuit comprises: a second holding circuit that holds the second signal; and A third switch is provided between the control electrode of the switching element and ground, and is turned on during a period in which the second holding circuit holds the second signal which is longer than the second period.

7. The switch control circuit according to claim 6, characterized in that: The driving circuit includes a reset circuit for resetting the state of the second holding circuit when a period during which the second holding circuit holds the second signal indicating a period longer than the second period is longer than a predetermined period.

8. The switch control circuit according to claim 5, characterized in that: The detection circuit comprises: a first comparison circuit that compares the current flowing through the switching element with a first current value and outputs a first comparison result indicating that the current flowing through the switching element is in the overcurrent state when the current flowing through the switching element is greater than the first current value; as well as a second comparison circuit, which compares the current flowing through the switching element with a second current value, and outputs a second comparison result indicating that the current flowing through the switching element is in the overcurrent state when the current flowing through the switching element is larger than the second current value; The first signal output circuit outputs the first signal based on the first comparison result. The second signal output circuit outputs the second signal based on the second comparison result.

9. The switch control circuit according to claim 6 or 7, characterized in that: The detection circuit comprises: a first comparison circuit that compares the current flowing through the switching element with a first current value and outputs a first comparison result indicating that the current flowing through the switching element is in the overcurrent state when the current flowing through the switching element is greater than the first current value; as well as a second comparison circuit, which compares the current flowing through the switching element with a second current value, and outputs a second comparison result indicating that the current flowing through the switching element is in the overcurrent state when the current flowing through the switching element is larger than the second current value; The first signal output circuit outputs the first signal based on the first comparison result. The second signal output circuit outputs the second signal based on the second comparison result.

10. A switch control circuit, The switch of the switch element is controlled, characterized in that: include: a detection circuit for detecting an overcurrent state in which a current flowing through the switching element is greater than a specified current; a first signal output circuit that outputs a first signal indicating whether the period of the overcurrent state is longer than a first period; a second signal output circuit that outputs a second signal indicating whether the period of the overcurrent state is longer than a second period that is longer than the first period; as well as a driving circuit comprising a first switch, a second switch having an on-resistance greater than that of the first switch, and a first holding circuit, and driving the switching element based on the first signal and the second signal, a first input signal for turning on the switching element, and a second input signal for turning off the switching element, When the period of the overcurrent state is longer than the second period, the drive circuit turns off the switch element based on the second signal indicating that the period of the overcurrent state is longer than the second period, regardless of the first input signal and the second input signal. When the period of the overcurrent state is shorter than the first period, the switching element is turned on based on the first input signal, and the switching element is turned off via the first switch based on the second input signal. When the period of the overcurrent state is longer than the first period and shorter than the second period, the first signal is received from the first signal output circuit, and when the second input signal is input, the first signal is held in the first holding circuit, the switching element is turned on based on the first input signal, and the switching element is turned off via the second switch based on the first signal indicating that the period of the overcurrent state is longer than the first period and the second input signal.

11. A semiconductor device, characterized in that: include: Switching elements; A detection circuit, the detection circuit detecting whether the current flowing through the switch element is in an overcurrent state; a first signal output circuit that outputs a first signal indicating whether the period of the overcurrent state is longer than a first period; A driving circuit, the driving circuit comprising a first switch, a second switch having an on-resistance greater than that of the first switch, and a first holding circuit, the driving circuit turning on the switching element based on a first input signal for turning on the switching element, turning off the switching element via the first switch based on a second input signal for turning off the switching element when the period of the overcurrent state is shorter than the first period, receiving the first signal from the first signal output circuit, holding the first signal in the first holding circuit when the second input signal is input, and turning off the switching element via the second switch based on the second input signal and the first signal when the period of the overcurrent state is longer than the first period; as well as A second signal output circuit outputs a second signal indicating whether a period of the overcurrent state is longer than a second period longer than the first period.

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