Communication failure indication between primary controller and secondary controller in primary controlled flyback converter

Abstract

Communication of fault indications between a primary controller and a secondary controller in a secondary controlled flyback converter is described. In one embodiment, an apparatus includes a primary side field effect transistor (FET) coupled to a flyback transformer, the flyback transformer coupled to the primary side FET, and a primary side controller coupled to the flyback transformer. The primary side controller is configured to receive a signal from a secondary side controller across an electrical isolation barrier, apply a pulse signal to the primary side FET to turn on and turn off the primary side FET in response to the signal, communicate information across the flyback transformer to the secondary side controller by changing a first pulse width of the pulse signal to a second pulse width and applying the pulse signal having the second pulse width to the primary side FET.

Description

[0001] Related Applications

[0002] This application is an international application of U.S. Non-Provisional Application No. 16 / 454,616, filed June 27, 2019, the entirety of which is incorporated by reference herein. BACKGROUND

[0003] Various electronic devices (e.g., such as smartphones, tablet computers, notebook computers, laptop computers, hubs, chargers, adapters, etc.) are configured to transfer power through a Universal Serial Bus (USB) connector in accordance with USB Power Delivery (USB-PD) protocols defined in various revisions of the USB-PD specification. For example, in some applications, an electronic device can be configured as a power consumer to receive power through a USB connector (e.g., for battery charging), while in other applications, an electronic device can be configured as a power provider to provide power to another device connected to it through a USB connector. However, the USB-PD specification allows power providers and power consumers to dynamically negotiate the level of voltage and current provided. Fault conditions can occur on the voltage / current provided from the power provider under certain power delivery conditions, as well as other fault conditions can occur on the provided voltage / current received by the power consumer. BRIEF DESCRIPTION OF DRAWINGS

[0004] In the drawings, which are not intended to be to scale, the present disclosure, which is by way of example and not limitation, is illustrated.

[0005] Figure 1 is a block diagram of a secondary controlled flyback converter that communicates bidirectionally through an electrically isolating barrier according to one embodiment.

[0006] Figure 2 is a waveform diagram that illustrates a primary drain signal, a secondary drain signal, a primary FET driver signal, and a synchronous rectification (SR) driver signal used to communicate information from a primary side controller to a secondary side controller of a secondary controlled flyback converter according to one embodiment.

[0007] Figure 3 is a block diagram of a secondary controlled flyback converter having a secondary side controller that communicates information to a primary side controller through an electrically isolating barrier according to one embodiment.

[0008] Figure 4 is a block diagram of a circuit of a primary side controller to detect a signal pattern from a secondary side controller to disable a shutdown logic of the primary side controller according to one embodiment.

[0009] Figure 5is a schematic diagram of a USB-PD power adapter that communicates bidirectionally through an isolation barrier between a primary-side controller and a secondary-side controller, according to one embodiment.

[0010] Figure 6 is a block diagram illustrating a system of a USB device for use in USB power delivery, according to some embodiments.

[0011] Figure 7 is a flowchart of a method of communicating information to a secondary-side controller across an electrical isolation barrier, according to one embodiment.

[0012] Figure 8 is a flowchart of a method of detecting a fault condition and communicating information about the fault condition to a secondary-side controller across an electrical isolation barrier, according to one embodiment.

[0013] Figure 9 is a flowchart of a method of communicating information to a primary-side controller across an electrical isolation barrier, according to one embodiment.

[0014] Figure 10 is a flowchart of a method of detecting a fault condition and communicating information about the fault condition to a primary-side controller across an electrical isolation barrier, according to one embodiment. DETAILED DESCRIPTION

[0015] The following description sets forth numerous specific details such as particular systems, components, methods, and so forth, in order to provide a good understanding of various embodiments of the techniques described herein for communicating information such as fault indications between a primary integrated circuit (IC) and a secondary IC in a flyback converter for secondary control in, for example, USB power delivery applications. It will be apparent, however, to one skilled in the art that at least some embodiments can be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or have been presented in a simple block diagram format in order to avoid unnecessarily obscuring the techniques described herein. Thus, the specific details set forth hereinafter are merely exemplary. Particular implementations can vary from these exemplary details and still be contemplated to be within the spirit and scope of the present application.

[0016] Reference throughout the specification to "an embodiment", "one embodiment", "exemplary embodiment", "some embodiments", and "various embodiments" means that a particular feature, structure, step, operation, or characteristic being referred to is included in at least one embodiment of the application. Furthermore, the appearing of the phrases "embodiment", "one embodiment", "exemplary embodiment", "some embodiments", and "various embodiments" in various places in the specification are not necessarily all referring to the same (one or more) embodiment(s).

[0017] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings illustrate examples of the described technology. These embodiments, which can also be referred to as “examples,” are described in enough detail to enable those skilled in the art to practice the claimed subject matter. The examples can be combined or modified. Other embodiments can be utilized, and structural, logical and electrical changes can be made without departing from the scope and spirit of the claimed subject matter. The detailed description is not intended to limit the scope of the subject matter as set forth in the claims. Rather, the detailed description is intended to describe the embodiments of the subject matter in a way that enables one skilled in the art to practice the subject matter.

[0018] Various embodiments of techniques for communicating a fault indication between a primary integrated circuit (IC) and a secondary IC in a secondary controlled flyback converter coupled to a power line in an electronic device in USB-PD are described herein. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptop computers, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, e-reader devices, etc.), mobile communication devices (e.g., smart phones, cellular telephones, personal digital assistants, messaging devices, palm PCs, etc.), connectivity and charging devices (e.g., hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., cameras, recorders, hand-held scanners, monitors, etc.), and other similar electronic devices that can communicate, battery charge, and / or power delivery using a USB connector (interface).

[0019] A USB-enabled electronic device or system can conform to at least one release of the Universal Serial Bus (USB) specification. Examples of such USB specifications include, but are not limited to, the USB Specification Revision 2.0, the USB 3.0 specification, the USB 3.1 specification, and / or various supplements (e.g., such as On-The-Go or OTG), versions, and errata thereof. The USB specification generally defines the characteristics (e.g., attributes, protocol definitions, transaction types, bus management, programming interfaces, etc.) of a differential serial bus required to design and build standard communication systems and peripheral devices. For example, a USB-enabled peripheral device is attached to a USB-enabled host device through a USB port of the host device to form a USB-enabled system. A USB 2.0 port includes a power supply voltage line (denoted as VBUS) at 5V, a differential data line pair (denoted as D+ or DP, and D- or DN), and a ground line (denoted as GND) for power return. A USB 3.0 port also provides VBUS, D+, D-, and GND lines for backward compatibility with USB 2.0. Additionally, to support a faster differential bus (USB SuperSpeed bus), a USB 3.0 port also provides a differential transmitter data line pair (denoted as SSTX+ and SSTX-), a differential receiver data line pair (denoted as SSRX+ and SSRX-), a power supply line (denoted as DPWR) for power supply, and a ground line (denoted as DGND) for power return. A USB 3.1 port provides the same lines as a USB 3.0 port for backward compatibility with USB 2.0 and USB 3.0 communications, but expands the performance of the SuperSpeed bus through a collection of features known as Enhanced SuperSpeed.

[0020] An updated technology for USB connectors, referred to as USB Type-C, is defined in various releases and / or versions of the USB Type-C specification (e.g., Release 1.0 as of August 11, 2014, Release 1.1 as of April 3, 2015, etc.). The USB Type-C specification defines Type-C receptacles, Type-C plugs, and Type-C cables that can support USB communications as well as power delivery through newer USB power delivery protocols defined in various revisions / versions of the USB-PD specification. Examples of USB Type-C functionality and requirements can include, but are not limited to, data and other communications according to USB 2.0 and USB 3.0 / 3.1, mechanical and performance requirements for Type-C cables, mechanical and performance requirements for Type-C receptacles, mechanical and performance requirements for Type-C plugs, requirements for Type-C to legacy cable assemblies and adapters, requirements for C-Type based device detection and interface configuration, requirements for optimized power delivery for Type-C connectors, etc. According to the USB Type-C specification(s), a Type-C port provides VBUS, D+, D-, GND, SSTX+, SSTX-, SSRX+, and SSRX- lines, among others. In addition, the Type-C port also provides a sideband use (denoted as SBU) line for signaling of sideband functions and a configuration channel (denoted as CC) line for discovery, configuration, and management of connections across Type-C cables. Type-C ports can be associated with Type-C plugs and / or Type-C receptacles. To ease use, Type-C plugs and Type-C receptacles are designed as reversible pairs, operating independent of the plug-to-receptacle orientation. Thus, a standard USB Type-C connector provided as a standard Type-C plug or receptacle provides pins for four VBUS lines, four ground return (GND) lines, two D+ lines (DP1 and DP2), two D- lines (DN1 and DN2), two SSTX+ lines (SSTXP1 and SSTXP2), two SSTX- lines (SSTXN1 and SSTXN2), two SSRX+ lines (SSRXP1 and SSRXP2), two SSRX- lines (SSRXN1 and SSRXN2), two CC lines (CC1 and CC2), and two SBU lines (SBU1 and SBU2), among others.

[0021] Some USB-enabled electronic devices can comply with a particular revision and / or version of the USB-PD specification (e.g., such as Revision 1.0, published on July 5, 2012, Revision 2.0, distributed on August 11, 2014, and the like, or later revisions / versions). The USB-PD specification defines a standard protocol designed to enable maximum functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB Type-C cable via a USB Type-C port. The USB-PD specification also describes the architecture, protocol, power source behavior, parameters, and cable pinout necessary to manage power delivery over a USB Type-C cable at up to 100 W of power. According to the USB-PD specification, a device with a USB Type-C port (e.g., such as a USB-enabled device) can negotiate a larger current and / or a higher or lower voltage over a USB Type-C cable than allowed in older USB specifications (e.g., such as the USB 2.0 specification, the USB 3.1 specification, the USB Battery Charging Specification 1.1 / 1.2 version, and the like). For example, the USB-PD specification defines requirements for a power delivery contract (PD contract) that can be negotiated between a pair of USB-enabled devices. The PD contract can specify a power level and direction of power transfer that can be accommodated by the two devices, and can be dynamically renegotiated (e.g., without the devices unplugging the plug) upon request by either device and / or in response to various events and conditions (e.g., power role swap, data role swap, hard reset, power failure, and the like).

[0022] According to the USB-PD specification, an electronic device is generally configured to deliver power to another device over a power path configured on a USB VBUS line. The device providing power is generally referred to as (or includes) a “provider” (or power source), and the device consuming power is generally referred to as (or includes) a “consumer” (or power sink). The power path generally includes a power switch coupled in series on the VBUS line and configured to turn on and off power delivery.

[0023] A USB-PD power source can be configured to draw power from an alternating current (AC) power adapter or from another AC power source. Thus, as part of an alternating current to direct current (AC-DC) conversion, some implementations can use a large bulk capacitor on the power side of the VBUS line in order to remove the AC component of the power signal. Turn on and turn off of the power switch (also referred to as a power FET) can allow for further circuit protection based on analysis of current and voltage conditions and detection of faults.

[0024] These fault conditions in current systems cannot be communicated between the primary side of the power provider and the secondary side of the power provider without additional communication channels and protocols to synchronize the transmission and reception to avoid data collision on the additional communication channel. For example, in a secondary controlled power adapter (also referred to herein as a secondary controlled power converter), a pulse transformer can be used to transmit pulse width modulation (PWM) pulse information from a secondary side controller (also referred to as a secondary IC or secondary controller) to a primary side controller (also referred to as a primary IC or primary controller) to turn on or turn off the primary side FETs using pulses for rising and falling edges (e.g., +ve and -ve pulses), respectively. When a “1” is defined as a positive pulse and a “0” is defined as a negative pulse, it is not possible to send any other pattern (like 00) from the secondary side controller to the primary side controller unless there is a faster frequency synchronized clock available in the primary side controller to detect the pattern. This requires logic on the primary side and a huge area increase due to higher technology nodes (e.g., 0.5 pm to 1 pm nodes). Therefore, in addition to stopping the PWM pulses, a fault that occurs at the secondary side cannot be communicated. If the primary side controller does not receive the PWM pulses through the pulse transmission, it goes into a soft start mode and performs multiple soft start operations (a few seconds) before latching, which will stop the converter. It should be noted that the pulses can be other types of pulses other than PWM pulses.

[0025] Similarly, to transmit any information (e.g., faults like over voltage (OV), under voltage (UV), over current (OC), short circuit detection, over temperature (OT), or other information like line voltage, peak current limit, etc.) from the primary side controller to the secondary side controller, the system will require another pulse transformer or input buffer in both the primary and secondary side controllers and a protocol to synchronize the transmission and reception to avoid data collision, which will require logic and circuitry in both the controllers. The additional logic and circuitry can increase the die size, especially for the primary side controller due to higher technology nodes. Also, there can be additional cost to use another pulse transformer to communicate the fault from the secondary side controller to the primary side controller or from the primary side controller to the secondary side controller. If a single pulse transformer is used for bidirectional communication, there is additional cost to use bidirectional input and output buffers with collision detection.

[0026] Various embodiments of techniques for communicating fault indications between a primary-side controller and a secondary-side controller in a secondary-controlled flyback converter are described herein. Embodiments described herein can address the above-described and other challenges by providing fault indications across an electrically isolating barrier in a bidirectional manner and without the need for the above-described additional logic and circuitry and complex protocols. In some cases, embodiments can provide bidirectional communication of information (e.g., fault information) between a primary-side controller and a secondary-side controller in a secondary-controlled flyback converter. For example, a hardware or firmware controlled scheme can use a number of consecutive pulses (e.g., +ve or -ve pulses) given across an electrically isolating barrier, such as across a pulse transformer, to define a system shutdown to inform the primary-side controller of a fault that occurred on the secondary-side (i.e., detected by the secondary-side controller). The primary-side controller can shut down immediately in response to the notification and need not perform a soft start again. Similarly, a hardware or firmware controlled scheme can communicate information from the primary-side controller to the secondary-side controller across an electrically isolating barrier, such as across a pulse transformer and a flyback transformer, without adding input and output buffers or complex protocols, as described in more detail below. With bidirectional communication, information can be passed from the primary-side controller to the secondary-side controller and from the secondary-side controller to the primary-side controller, for example, through i) a pulse transformer or ii) a pulse transformer and a flyback transformer, to protect the system or optimize the performance of the system.

[0027] Embodiments described herein can address the above-described and other challenges by providing a serial bus compliant power device, such as a serial bus power delivery (SBPD) device with a power control analog subsystem having hardware, firmware, or any combination to communicate information, including fault information, across an electrically isolating barrier. The SBPD (also referred to herein as a “source device”) can be a USB compliant power device.

[0028] Figure 1is a block diagram of a secondary controlled flyback converter 100 that communicates bidirectionally through an electrically isolating barrier according to one embodiment. The secondary controlled flyback converter 100 can be part of an AC-DC power adapter device. The secondary controlled flyback converter 100 includes a rectifier 102 (e.g., a full-bridge rectifier) coupled between AC input terminals 104 and a rectified DC line 106 (VIN), a flyback transformer 108 (the flyback transformer 108 includes a primary winding coupled to the rectified DC line 106), a primary side power switch 110 (e.g., a primary side field effect transistor (FET), power FET, or primary FET), a secondary side power switch 112 (e.g., a secondary side FET 112, power FET, or secondary FET), a primary side controller 114, and a secondary side controller 116. The rectified DC line 106 is coupled to a first end of the primary winding of the flyback transformer 108. VIN is the voltage on the AC line input after the rectifier 102. A second end of the primary winding is coupled to a primary drain of the primary side FET 110 (also referred to herein as a power switch). A first end of a secondary winding of the flyback transformer 108 is coupled to a direct current (DC) output line 118 (VBUS), and a second end of the secondary winding is coupled to a secondary drain (SR_Drain) of the secondary side FET 112. VBUS is the voltage on the DC output of the flyback transformer 108. SR_Drain is a drain node of the secondary side FET 112. The DC output line 118 and the secondary side FET 110 are coupled to a DC output terminal 120.

[0029] The secondary controlled flyback converter 100 is used for AC-DC conversion with electrical isolation between the input and any output. The secondary controlled flyback converter 100 uses an inductor separate from the flyback transformer 108 with an electrical isolation barrier 122 between the primary side and the secondary side. When the primary side power switch 110 (primary side FET) is closed, the primary side of the flyback transformer 108 is connected to the input voltage source. In this embodiment, the primary side of the flyback transformer 108 is coupled to the rectifier 102. As the primary current and magnetic flux in the flyback transformer 108 increases, energy is stored in the transformer core of the flyback transformer 108. The voltage induced in the secondary winding is negative and is blocked. When the primary side power switch 110 (primary side FET) is opened, the primary current and magnetic flux decrease. The secondary voltage is positive, allowing current to flow out of the flyback transformer 108. The energy from the transformer core provides the output load. An output capacitor can be used to charge and supply energy to the output load. Thus, the flyback transformer 108, based on the control of the primary side power switch 110, can store energy and transfer energy to the output of the secondary controlled flyback converter 100. It should also be noted that the secondary controlled flyback converter 100 can include other components in the input stage, in the output stage, or both. For example, a bulk capacitor can be coupled between the output of the rectifier 102 and a ground node. During operation, the AC input power is rectified and filtered by the rectifier 102 (bridge rectifier) and the bulk capacitor. This results in a DC high voltage bus connected to the primary winding of the flyback transformer 108. Similarly, in the output stage, the secondary winding power is rectified and filtered, for example, by diodes, capacitors, output LC filter, etc., to reduce the output voltage ripple. Other output voltages can also be achieved by adjusting the turns ratio of the flyback transformer and the output stage.

[0030] The secondary controlled flyback converter 100 operates as an isolated power converter. Two main control schemes are voltage mode control and current mode control. Both control schemes use a signal related to the output voltage. In one approach, an optocoupler is coupled to the secondary side controller 116 and sends a signal to the primary side controller 114 to indicate the output voltage. The optocoupler can be used to achieve tight voltage and current regulation.

[0031] Conventional systems allow the primary side controller to initiate an auto-restart operation after a specified period of time (e.g., time > tAR, where tAR is 82 milliseconds) after the secondary side controller has not sent any switching cycle requests. However, some faults can persist for a long duration even if the secondary side controller has detected the fault and taken action. In the worst case, the auto-restart operation after the specified period of time without a request can damage the system. The primary side controller can sense line input voltage / current related information before the secondary side controller. But with one-way communication, such as through an optocoupler, there is no information that can be passed from the primary side controller to the secondary side controller to protect the system or optimize system performance.

[0032] In the illustrated embodiment, the primary side controller 114 (also referred to as a primary IC) and the secondary side controller 116 (also referred to as a secondary IC) are configured for bidirectional communication through the electrical isolation barrier 122, through the electrical isolation barrier 124, or both. In one embodiment, the primary side controller 114 is configured to receive a signal 126 from the secondary side controller 116 across the electrical isolation barrier 124. The primary side controller 114 applies a pulse signal 128 to the primary side FET 110 to turn on and turn off the primary side FET 110 in response to the signal 126. The primary side controller 114 can communicate information to the secondary side controller 116 across the electrical isolation barrier 122 via the flyback transformer 108 by changing a first pulse width of the pulse signal 128 to a second pulse width and applying the pulse signal 128 having the second pulse width to the primary side FET 110.

[0033] In one embodiment, the secondary controlled flyback converter 100 includes a pulse transformer 130 coupled between the primary side controller 114 and the secondary side controller 116. The primary side controller 114 is configured to receive a signal 126 from the secondary side controller 116 as one or more pulses via the pulse transformer 130. The primary side controller 114 can include a receiver, such as a pulse receiver 132, to receive the pulse signal 128 from the secondary side controller 116 across the electrical isolation barrier 124. The pulse receiver 132 can vary the primary side on pulse based on an output of the flyback transformer 108 (e.g., an error amplifier (EA) output). The primary side on pulse is used to turn on the primary side FET 110. Where the EA voltage is higher, a wider PWM pulse is sent from the secondary controller 116 via the pulse transformer 130, which results in a wider primary on pulse being used. The primary side controller 114 can also include a gate driver 134 coupled to the pulse receiver 132 and to the gate of the primary side FET 110. As described herein, the on and off pulses can have a fixed width or a variable width. In one embodiment, the pulse receiver 132 can include a pulse width modulation (PWM) circuit. Alternatively, the pulse receiver 132 can use other types of circuits to receive the pulses across the electrical isolation barrier 124.

[0034] In one embodiment, to apply the pulse signal 128 to the primary side FET 110, the primary side controller 114 is configured to receive an on pulse (PTDRV) from the secondary side controller 116. The primary side controller 114 applies the on pulse to the gate of the primary side FET 110 via the gate driver 134. The on pulse makes the primary drain of the primary side FET 110 low (e.g., corresponding to a first state or a first voltage level representing a digital value of one) and the secondary drain of the secondary side FET 112 high. Subsequently, the primary side controller 114 receives an off pulse from the secondary side controller 116 and applies the off pulse to the gate of the primary side FET 110 via the gate driver 134. The off pulse makes the primary drain of the primary side FET 110 high (e.g., corresponding to a second state or a second voltage level representing a digital value of zero) and the secondary drain of the secondary side FET 112 low. As described with respect to FIG. 1, the primary side controller 114 can include a gate driver 134 to apply the on and off pulses to the gate of the primary side FET 110. Figure 2As illustrated and described, the secondary-side controller 116 is configured to detect the secondary drain going low using negative sense (NSN). Alternatively, the secondary-side controller 116 can include a zero-crossing detection (ZCD) circuit to detect a negative voltage on the secondary drain. The secondary-side controller 116 can determine an amount of time between the start of the off pulse (PTDRV) and the NSN going high. The amount of time corresponds to a fixed time when the pulse signal includes a first pulse width between the on pulse and the off pulse. The amount of time can also correspond to an extended time when the pulse signal includes a second pulse width between the on pulse and the off pulse. For example, if the second pulse width is extended by an amount of time Td, the extended time measured by the secondary-side controller 116 is at least the amount of time Td. In another embodiment, the secondary-side controller 116 can determine that the amount of time is extended by less than a specified amount of time corresponding to the fixed time of the normal mode. When the amount of time is greater than the specified amount of time of the fixed time, the secondary controller 116 can receive information from the primary-side controller 114, such as the fault information described herein.

[0035] In another embodiment, the primary-side controller 114 includes a fault detection circuit 136 to detect a fault condition. The fault condition can occur on the voltage / current provided from the power provider, and the fault condition can occur on the provided voltage / current received by the power consumer. In response to the fault condition detected by the fault detection circuit 136, the primary-side controller 114 transmits information about the fault condition across the electrical isolation barrier 122 to the secondary-side controller 116 via the flyback transformer 108 by changing the first pulse width of the pulse signal to the second pulse width and applying the pulse signal having the second pulse width to the primary-side FET 110, such as shown in FIG. 2. Figure 2 The change in pulse width can be detected by the secondary-side controller 116 to receive the information about the fault condition.

[0036] In yet another embodiment, the fault detection circuit 136 can detect different types of fault conditions and send different information about the respective fault conditions to the secondary-side controller 116. For example, the fault detection circuit 136 can detect a first fault condition in a first situation and a second fault condition in a second situation. The primary-side controller 114 transmits information about the first fault condition across the flyback transformer 108 to the secondary-side controller 116 in response to the detected first fault condition. The primary-side controller 114 transmits information about the second fault condition across the flyback transformer 108 to the secondary-side controller 116 in response to the detected second fault condition.

[0037] In yet another embodiment, to communicate information across the flyback transformer 108 to the secondary side controller 116, the primary side controller 114 changes the first pulse width of the pulse signal to create a particular pattern in the pulse signal 128. The particular pattern in the pulse signal 128 corresponds to a fault condition communicated by the primary side controller 114.

[0038] It should be noted that the embodiments described above with respect to Figure 1 communicating information to the secondary side controller 116. In other embodiments, the secondary side controller 116 can communicate information to the primary side controller 114 through the electrical isolation barrier 124 (e.g., via the pulse transformer 130). Additional details of these embodiments will be described below with respect to Figure 3 communicating information through the flyback transformer 108 can be detected by the secondary side controller 116, for example Figure 2 as shown in the waveform diagram of FIG. 2.

[0039] Figure 2 is a waveform diagram 200 illustrating a primary drain signal 202, a secondary drain signal 204, a primary FET driver signal 206, and a synchronous rectification (SR) driver signal 208 for communicating information from a primary side controller of a secondary controlled flyback converter to a secondary side controller, according to one embodiment. Referring back to Figure 1 , the primary drain signal 202 is the signal on the primary drain of the primary side FET 110, and the primary FET driver signal 206 (PTDRV) is the signal on the gate 128 of the primary side FET 110 provided by the primary side controller 114. The secondary side controller 116 is configured to detect the secondary drain signal 204 going low and eventually zero crossing to become a negative voltage. When the primary drain 202 goes low, the secondary drain signal 204 starts to increase, and when the primary drain 202 starts to go high, the secondary drain signal 204 (SR DRAIN) eventually starts to go low and zero cross in the opposite direction. The SR driver signal 208 is high between the secondary drain signal 204 going negative and then starts to increase to the secondary drain signal 204 zero crossing towards the positive side. The secondary side controller 116 can use a timer (or counter) to keep a count of the amount of time between the primary FET driver signal 206 going low (as controlled by the secondary side controller 116) to the NSN going high (increasing from a minimum value after zero crossing).

[0040] For a secondary controlled flyback converter, the primary FET is turned on and off based on +ve / -ve pulses sent from the secondary side controller 116 via the pulse transformer 130. Turning off the primary FET causes the SR DRAIN signal to go low, which is detected using the NSN, as Figure 2PTDRV signal is a primary FET turn-on pulse sent by the secondary-side controller 116 via the pulse transformer 130. The timer keeps a count of the time between PTDRV going low to NSN going high. In normal conditions, the delay between PTDRV going low to NSN going high will be a fixed amount of time based on external components. For fault conditions, the primary-side controller 114 can lengthen the PTDRV pulse it receives by an extended amount of time Td (e.g., 200 ns, 500 ns, 1 μβ, etc.). The extended amount of time can be programmable. The extended amount of time Td can be detected by the secondary-side controller 116 using the timer between PTDRV going low (on the secondary side) to NSN going high, which is now lengthened by the extended amount of time 210 Td. Thus, the secondary-side controller 116 can learn that the primary-side controller 114 is communicating information, e.g., fault information, across the flyback transformer 108.

[0041] In some embodiments, the primary-side controller 114 can communicate with the secondary-side controller 116 by lengthening the PTDRV pulse width based on a predefined duration (Td) for different fault or information scenarios. This can extend to other possible ways of changing the PTDRV pulse to communicate that information or additional information (e.g., different fault types, etc.). In other embodiments, the primary-side controller 114 can narrow the PTDRV pulse width by pushing out the rising edge. In other embodiments, the PTDRV pulse can be split into two fixed widths (e.g., 100 ns). In other embodiments, the primary-side controller 114 can mask the PTDRV pulse entirely.

[0042] As described above, the secondary-side controller 116 can communicate information to the primary-side controller 114 through the electrical isolation barrier 124, e.g., via a pulse transformer 130 such as described with respect to Figure 3 FIG. 1.

[0043] Figure 3 is a block diagram of a secondary-controlled flyback converter 300 having a secondary-side controller 316 that communicates information to a primary-side controller 314 through an electrical isolation barrier in accordance with one embodiment. Although not all components of the secondary-controlled flyback converter 300 are shown, the secondary-controlled flyback converter 300 is similar to the secondary-controlled flyback converter 100 of FIG. 1, as shown by like reference numbers. Figure 1 To control the flyback transformer via the primary-side power switch (not shown in FIG. 3), the secondary-side controller 316 can send a pulse to the primary-side controller 314 across the electrical isolation barrier 324, e.g., via a pulse transformer 330. Figure 3

[0044] ​Secondary-side controller 316 includes a signal generator 331 to generate pulses to control primary-side FET 110 via pulse transformer 330. For example, signal generator 331 may include pull-up transistors and pull-down transistors. The pull-up and pull-down transistors may be controlled by the control logic or firmware of secondary-side controller 316. During normal mode, signal generator 331 can generate and output a square wave signal. Capacitor 340 is coupled between signal generator 331 and pulse transformer 330. Capacitor 340 generates a positive pulse on the positive transition (i.e., rising edge) of the square wave signal and a negative pulse on the negative transition (i.e., falling edge) of the square wave signal. The positive and negative pulses are transmitted to primary-side controller 314 via pulse transformer 330. Primary-side controller 314 receives the positive and negative pulses to turn the primary-side power switch on and off. Figure 3 (Not shown in the image). Figure 1 An example waveform of a square wave generated by signal generator 331 is shown in the figure. Figure 1 Example waveforms of positive and negative pulses generated by the capacitor are shown. The secondary-side controller 316 can generate a square wave signal during normal operation (e.g., in normal operating mode). The secondary-side controller 316 can detect fault conditions or require information to be transmitted to the primary-side controller 314. In such cases, the secondary-side controller 316 can switch resistor 333 between the pull-up transistor and capacitor 340. It should be noted that resistor 333 can be any type of resistive element. Therefore, the signal generator 331 generates a sawtooth wave signal 334 with a slow rising edge and a falling edge faster than the slow rising edge. Given the edges of the sawtooth wave signal 334, capacitor 340 does not generate a positive pulse for each pulse in the sawtooth wave signal 334, thus producing a pulse signal 336 with two or more consecutive negative pulses. The consecutive negative pulses of pulse signal 336 are transmitted to the primary-side controller 314 via pulse transformer 330. The primary-side controller 314 receives the consecutive negative pulses to detect that the secondary-side controller 316 is transmitting information to the primary-side controller 314. For example, this information may include fault information. In response to the primary-side controller 314 detecting fault information, the primary-side controller 314 may perform an action in response to the fault. Although the pulse signal 336 comprises two consecutive negative pulses (i.e., no inserted positive pulses), which may represent two consecutive "0" values ​​transmitted across the electrical isolation barrier 324, in other embodiments, other specific patterns may be generated by the secondary-side controller 316 and detected by the primary-side controller 314. For example, the secondary-side controller 316 may extend the signal generator 331 to generate two or more consecutive "1" values ​​or even a pattern of 0 and 1 to provide multiple fault conditions or other information from the secondary-side controller 316 to the primary-side controller 314. Other information may include start modes, stop modes, soft faults requiring soft-start operation, soft faults requiring minimum delivery power, etc.

[0045] In some cases, two consecutive 0s require two "-ve" pulses, which does not require any fast clock synchronization on the primary side. The two consecutive 0s can be initiated by the firmware after a fault is confirmed that requires the system to shut down. The pull-up and pull-down transistors can be controlled so that there is a programmable slow pull-up at the input of the pulse transformer 330 followed by a sudden pull-down, resulting in a "-ve" edge without a "+ve" edge. Similarly, another programmable slow pull-up followed by a sudden pull-down will result in another "-ve" edge. It should be noted that the slow pull-up can be achieved by switching a resistor 333 into the pull-up path. Similarly, a resistor in series with the pull-down device can be used to generate consecutive 1s. Alternatively, the slow pull-up can be achieved by a current source based pull-up.

[0046] As shown in FIG. 3B, the secondary side controller 316 sends two consecutive 0s in the pulse signal 336, and the primary side controller 314 receives the two consecutive 0s in the pulse signal 326. The primary side controller 314 can include a circuit for detecting the two consecutive 0s in the pulse signal 326, such as shown in FIG. 4. Figure 3 As shown in FIG. 3B, the secondary side controller 316 sends two consecutive 0s in the pulse signal 336, and the primary side controller 314 receives the two consecutive 0s in the pulse signal 326. The primary side controller 314 can include a circuit for detecting the two consecutive 0s in the pulse signal 326, such as shown in FIG. 4. Figure 4 Alternatively, the primary side controller 314 can include a circuit for detecting other patterns to detect the information being communicated by the secondary side controller 316.

[0047] Figure 4 FIG. 4 is a block diagram of a circuit 400 of a primary side controller for detecting a signal pattern from a secondary side controller to disable shutdown logic of the primary side controller, according to one embodiment. The circuit 400 includes a first flip-flop 402, a second flip-flop 404, and an OR gate 406. The first flip-flop 402 receives a first input value 401 (e.g., 1 'b 1) that, if propagated through both the first flip-flop 402 and the second flip-flop 404, will stop the shutdown logic. The first flip-flop 402 is clocked by a high-to-low pulse 407 corresponding to a 0 pulse 326 in the pulse signal received by the primary side controller (i.e., a negative pulse in FIG. 3B). Figure 3 The second flip-flop 404 receives a second input value 403 from the output of the first flip-flop 402 when the second flip-flop 404 is clocked by a high-to-low pulse 409 corresponding to a 0 pulse 326 in the pulse signal received by the primary side controller (i.e., a negative pulse in FIG. 3B). Figure 3The output value 405 can be output by the second flip-flop 404 when clocked by a high going pulse 407 (a negative pulse in the example shown in FIG. 4). However, if the primary side controller receives an intervening high going pulse (a positive pulse) from the primary controller at the input of the pulse transformer 330 corresponding to a high going pulse 409 between two 407 pulses, the first and second flip-flops are cleared. For example, when the or gate 406 receives the high pulse 409 or the reset signal 411, the or gate 406 can output a reset (or clear) signal to the clear input of both the first flip-flop 402 and the second flip-flop 404. Although Figure 4 One embodiment of the circuit 400 to detect two consecutive zeros with love and detection is shown, but in other embodiments, the circuit 400 can include different logic or circuit components to detect two consecutive zeros or other specific patterns in the pulse signals received by the primary side controller across the electrical isolation barrier.

[0048] In this embodiment, the output value 405 can send a "stop" signal to the shutdown logic of the primary side controller to shut down the converter. For example, the primary side controller can include shutdown logic that can perform a soft start operation under certain conditions, such as when the primary side controller does not receive pulses to switch the primary side switch (e.g., a primary side FET). The shutdown logic can initiate an automatic restart operation after a specified period of time (e.g., time > tAR, where tAR is 82 milliseconds) when the secondary side controller does not send any requests to switch a cycle. However, in some cases, the secondary side controller can send information in a different manner than requests to switch a cycle, such as fault information. To avoid the shutdown logic performing certain actions when the secondary side controller sends information, the shutdown logic can be signaled or instructed by the circuit 400 (e.g., the output value 405) to shut down the AC-DC converter or perform a specific function as desired by the secondary side controller when a specified pattern is detected (e.g., two consecutive zeros as shown in FIG. 4). Figure 4

[0049] Figure 5 ​is a schematic diagram of a USB-PD power adapter 500 that communicates bidirectionally across an isolation barrier between a primary side controller and a secondary side controller according to one embodiment. Instead of opto-isolator feedback, the USB-PD power adapter 500 includes bidirectional communication across the isolation barrier via a pulse transformer 530, a flyback transformer 508, or both. The USB-PD power adapter 500 includes a primary IC controller 514 and a secondary IC controller 516. The secondary IC controller 516 can be disposed in a chip package and includes a USB-PD subsystem configured according to the techniques for gate driver control described herein. The secondary IC controller 516 is configured to negotiate a PD contract with a consumer device (not shown) attached to a USB Type-C port 540 and control a desired VBUS voltage output from the flyback transformer 508 through an output pin (“PWM DRV”). The USB Type-C port 540 is typically associated with a C-type plug, but it should be understood that in various embodiments the USB Type-C port can instead be associated with a C-type receptacle. The flyback transformer 508 is coupled to a rectified DC power supply and an output can be coupled to a secondary side FET 512 (e.g., an SR FET 512). VBUS IN is regulated by an error amplifier connected to a compensation network 550. The compensation network 550 can be a resistor-capacitor (RC) circuit that is specific to the design of the USB-PD power adapter 500. The compensation network 550 can be coupled to receive a feedback signal from a first output pin (“FB”) of the secondary IC controller 516. The compensation network 550 can also be coupled to a second output pin (“EA out”) and a third output pin (“CC Comp”). The flyback transformer 508 can be coupled to a bulk capacitor 533 and a buffer circuit 537. The USB-PD power adapter 500 can also include a pulse transformer 530 (or other feedback control mechanism) for communicating information across the isolation barrier 524.

[0050] The secondary IC controller 516 is coupled to the VBUS line 511 and is configured to control the operation and state of a power switch (e.g., the provider switch 520) when a fault condition is detected by providing a control signal to the gate of the switch. The VBUS line 511 includes a provider switch 520 that is configured as an on / off switching device controlled by a signal from an output pin ("VBUS_Control") of a gate driver in the secondary IC controller 516. The provider switch 520 can correspond to the provider FET described herein. On one side of the provider switch 520, a power supply node 505 on the VBUS line 511 is coupled to a second winding of the flyback transformer 508, which is coupled to a bulk capacitor 535 configured to remove AC components of the power signal. The power supply node 505 is coupled to an input pin ("VBUS IN") of the secondary IC controller 516. On the other side of the provider switch 520, an output node 507 on the VBUS line 511 is coupled to a USB Type-C port 540. The output node 507 is coupled to another input pin ("VBUS C") of the secondary IC controller 516. The GND line of the USB Type-C port 540 is coupled to the secondary power FET 512.

[0051] In operation, the direction of power flow on the VBUS line 511 is from the flyback transformer 508 to a consumer device, such as a laptop computer (not shown), that is attached to the USB Type-C port 540. When a PD contract is negotiated with the consumer device, the secondary IC controller 516 turns on the provider switch 520 to supply power to the consumer device at the negotiated voltage and / or current level(s). When the PD contract is dynamically renegotiated to lower the VBUS voltage and / or current, for example when the consumer device has finished charging its battery and now only needs power to operate, a high-to-low voltage transition on the VBUS line 511 can be required.

[0052] Upon detection of a fault condition, a control signal can be sent to turn off the provider switch 520, thereby disconnecting the USB Type-C port 540 from the flyback transformer 508. The provider switch 520 is turned off by driving the output of VBUS_Control to zero. This disconnection can be caused by an overvoltage condition, an overcurrent condition, or other conditions that can require the USB Type-C port 540 to be disconnected from the flyback transformer 508 to protect the circuitry coupled to the USB Type-C port 540.

[0053] In another embodiment, the auxiliary circuit 570 can be coupled to the primary IC controller 514. An auxiliary output pin ("AUX_IN") and an overvoltage protection auxiliary pin ("OVP_AUX") are coupled to the auxiliary circuit 570. The auxiliary circuit 570 can operate to protect the overvoltage of the VBUS_IN 511 and also power (AUX_IN) the primary IC controller 514 once start-up is complete.

[0054] As described above, the USB-PD power adapter 500 allows for bi-directional communication through the isolation barrier 524, the isolation barrier 522, or both, in a similar manner as described above with respect to Figures 1-4 the primary IC controller 514 can include a detection circuit that receives a signal on an input pin ("Pulse_In") and detects when the secondary IC controller 516 is communicating information. For example, the secondary IC controller 516 can detect a fault condition and can communicate that information to the primary IC controller 514 via the flyback transformer 508 across the isolation barrier 522. In another embodiment, the primary IC controller 514 can communicate information via the flyback transformer 508 across the isolation barrier 522. The primary IC controller 514 can include circuitry to alter the pulses received from the secondary IC controller 516 via the flyback transformer 508. By altering the pulses, the primary IC controller 514 can send information across the flyback transformer 508 via the primary power switch 510. The secondary IC controller 516 can include circuitry to measure the drain of the secondary power switch 512 (SR DRAIN) and can detect when the primary IC controller 514 is communicating information. For example, the primary IC controller 514 can detect a fault condition and can communicate that information to the secondary IC controller 516 via the flyback transformer 508.

[0055] In another embodiment, an AC-DC power adapter device includes a flyback converter (with a flyback transformer) or an isolated power converter coupled between AC terminals and DC terminals. The flyback transformer converts AC power on the AC terminals to DC power on the DC terminals with electrical isolation between the AC terminals and the DC terminals. The AC-DC power adapter device also includes a primary side controller coupled to the flyback transformer and a secondary side controller coupled to the flyback transformer. A primary side power switch (also referred to as a primary side switch FET or primary FET) is coupled to a primary winding of the flyback transformer and the primary side controller. A secondary side power switch is coupled to a secondary winding of the flyback transformer and the secondary side controller. The primary side controller is configured to receive a first signal from the secondary side controller across the electrical isolation barrier and apply a second signal to the primary side power switch to turn on and turn off the primary side power switch in response to the first signal. The primary side controller is also configured to communicate information to the secondary side controller across the flyback transformer by changing a first pulse width of the second signal to a second pulse width and applying the second signal with the second pulse width to the primary side power switch.

[0056] In yet another embodiment, the primary side controller includes a pulse receiver, a fault detection circuit, and a driver. The pulse receiver receives a first signal from the secondary side controller across the electrical isolation barrier. The first signal includes a first turn-on pulse to turn on the primary side power switch and a first turn-off pulse to turn off the primary side power switch. In response, the driver coupled to the pulse receiver and the primary side power switch applies the first turn-on pulse and the first turn-off pulse to the primary side power switch. The fault detection circuit detects a fault condition. In response, the fault detection circuit is configured to cause the pulse receiver to change a first pulse width of a second signal to a second pulse width and cause the driver to apply the second signal with the second pulse width to the primary side power switch. Applying the second signal with the second pulse width to the primary side power switch causes information to be transmitted across the electrical isolation barrier (along with the transmission of energy).

[0057] In yet another embodiment, the AC-DC power adapter device includes a pulse transformer coupled between the primary side controller and the secondary side controller. The primary side controller is configured to receive a first signal as one or more pulses from the secondary side controller via the pulse transformer. The primary side controller can detect when the secondary side controller communicates information via the pulse transformer as described herein.

[0058] The embodiments described herein can be implemented in a power delivery system such as a serial bus compatible power device. Examples of serial bus compatible power devices can include serial bus power delivery (SBPD) devices, USB compatible power devices, and the like. In some embodiments, the SBPD device is a USB-PD device that is compatible with the USB-PD standard or more generally compatible with the USB standard. For example, the SBPD device can be used to provide an output voltage (e.g., Vbus c power voltage) based on an input voltage (e.g., Vbus in power voltage). The SBPD device can include various embodiments described herein to facilitate communication between a primary side controller and a secondary side controller. As described herein, the communication can be unidirectional or bidirectional. The SBPD device can include a power converter 150 (e.g., an AC-DC converter) and a power control analog subsystem (e.g., a USB-PD controller). The power control analog subsystem can include circuitry, functionality, or both for communicating information across an electrical isolation barrier as described herein. The information can include information for different functions such as OV, UV, OCP, SCP, PFC, SR, and the like. The information can include fault information for any of these different functions.

[0059] In embodiments, the SBPD device is connected to a power source such as a wall outlet power source that provides AC power. In other embodiments, the power source can be a different power source such as a battery and can provide DC power to the SBPD device. The power converter can convert power received from the power source (e.g., convert the received power to Vbus in). For example, the power converter can be an AC-DC converter and convert AC power from the power source to DC power. In some embodiments, the power converter is a flyback converter that provides electrical isolation between an input (e.g., primary side) and an output (e.g., secondary side) such as a secondary controlled flyback converter.

[0060] In some embodiments, the SBPD device provides Vbus c to a sink device (e.g., via a communication channel (CC) that specifies a particular output voltage and possibly an output current). The SBPD device can also provide a path to a ground potential (e.g., ground) to the sink device. In some embodiments, the provision of Vbus c is compatible with the USB-PD standard. The power control analog subsystem can receive Vbus in from the power converter. The power control analog subsystem can output Vbus in. In some embodiments, the power control analog subsystem is a USB C type TM controller that is compatible with the USB C type TM standard. The power control analog subsystem can provide a system interrupt in response to Vbus in and Vbus c.

[0061] In some embodiments, any of the components of the SBPD device can be part of an IC, or alternatively, any of the components of the SBPD device can be implemented in its own IC. For example, the power converter and power control analog subsystems can each be discrete ICs with separate packaging and pin configurations.

[0062] In some embodiments, the SBPD device can provide a complete USB Type-C TM and USB-Power Delivery port control solution for notebooks, dongles, monitors, docking stations, power adapters, vehicle chargers, power banks, mobile adapters, etc.

[0063] Figure 6 is a block diagram illustrating a system 600 for a USB device for use in USB power delivery, according to some embodiments. The system 600 can include a peripheral subsystem 610 that includes a number of components for use in USB power delivery (USB-PD). The peripheral subsystem 610 can include a peripheral interconnect 611 that includes a clock module, a peripheral clock (PCLK) 612 for providing clock signals to various components of the peripheral subsystem 610. The peripheral interconnect 611 can be a peripheral bus, such as a single or multi-level Advanced High-Performance Bus (AHB), and can provide a data and control interface between the peripheral subsystem 610, a CPU subsystem 630, and system resources 640. The peripheral interconnect 611 can include controller circuitry, such as a direct memory access (DMA) controller, which can be programmed to transfer data between peripheral blocks without input, control, or burden from the CPU subsystem 630.

[0064] The peripheral interconnect 611 can be used to couple components of the peripheral subsystem 610 to other components of the system 600. Coupled to the peripheral interconnect 611 can be a number of general purpose input / outputs (GPIOs) 615 for sending and receiving signals. The GPIOs 615 can include circuitry configured to implement various functions, such as pull-up, pull-down, input threshold selection, input and output buffer enable / disable, single multiplexing, etc. Other functions can also be implemented by the GPIOs 615. One or more timers / counters / pulse width modulators (TCPWMs) 617 can also be coupled to the peripheral interconnect and include circuitry for implementing timing circuitry (timers), counters, pulse width modulators (PWM) decoders, and other digital functions that can operate on I / O signals and provide digital signals to system components of the system 600. The peripheral subsystem 610 can also include one or more serial communication blocks (SCBs) 619 for implementing serial communication interfaces, such as I2C, serial peripheral interface (SPI), universal asynchronous receiver / transmitter (UART), controller area network (CAN), clock extension peripheral interface (CXPI), etc.

[0065] For USB power delivery applications, the peripheral subsystem 610 can include a USB power delivery subsystem 620 coupled to the peripheral interconnect and including a set of USB-PD modules 621 for use in USB power delivery. The USB-PD modules 621 can be coupled to the peripheral interconnect 611 through a USB-PD interconnect 623. The USB-PD modules 621 can include an analog-to-digital conversion (ADC) module for converting various analog signals to digital signals; an error amplifier (AMP) for regulating the output voltage on the VBUS line according to a PD contract; a high voltage (HV) regulator for converting a supply voltage to a precise voltage (e.g., 3.5-5V) to feed the power system 600; a low-side current sense amplifier (LSCSA) for accurately measuring load current; an over-voltage protection (OVP) module and an over-current protection (OCP) module for providing over-current and over-voltage protection on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field effect transistors (FETs) used in USB power delivery in provider and consumer configurations; and a communication channel PHY (CC BB PHY) module for supporting communication on the C-type communication channel (CC) line. The USB-PD modules 621 can also include a charger detection module for determining the presence of a charging circuit and coupled to the system 600 and a VBUS discharge module for controlling discharge of voltage on the VBUS. The discharge control module can be configured to be coupled to a supply node on the VBUS line or an output (supply sink) node on the VBUS line and discharge the voltage on the VBUS line to a desired voltage level (i.e., a voltage level negotiated in a PD contract). The USB power delivery subsystem 620 can also include pads 627 for external connections and electrostatic discharge (ESD) protection circuitry 629 as can be needed on the C-type port. The USB-PD modules 621 can also include a bidirectional communication module for supporting bidirectional communication with another controller (e.g., between a primary side controller and a secondary side controller of a flyback converter).

[0066] The GPIO 615, TCPWM 617, and SCB 619 can be coupled to an input / output (I / O) subsystem 650, which can include a high-speed (HS) I / O matrix 651 coupled to a plurality of GPIOs 653. The GPIO 615, TCPWM 617, and SCB 619 can be coupled to the GPIOs 653 through the HS I / O matrix 651.

[0067] The system 600 can also include a central processing unit (CPU) subsystem 630 for processing commands, storing program information and data. The CPU subsystem 630 can include one or more processing units 631 for executing instructions and reading from and writing to memory units from a plurality of memories. The processing units 631 can be processors suitable for operation in an integrated circuit (IC) or system on a chip (SOC) device. In some embodiments, the processing units 631 can be optimized for low power operation with extensive clock gating. In such embodiments, various internal control circuitry can be implemented for processing unit operation in various power states. For example, the processing units 631 can include a wake-up interrupt controller (WIC) configured to wake up the processing units from a sleep state, allowing power to be cut off while the IC or SOC is in a sleep state. The CPU subsystem 630 can include one or more memories, including a flash memory 633, a static random access memory (SRAM) 635, and a read only memory (ROM) 637. The flash memory 633 can be a non-volatile memory (NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. The flash memory 633 can include a read accelerator and can improve access times by being integrated within the CPU subsystem 630. The SRAM 635 can be a volatile memory configured to store data and firmware instructions accessible by the processing units 631. The ROM 637 can be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of the system 600. The SRAM 635 and the ROM 637 can have associated control circuitry. The processing units 631 and the memories can be coupled to a system interconnect 639 to route signals to and from the various components of the CPU subsystem 630 to other blocks or modules of the system 600. The system interconnect 639 can be implemented as a system bus such as a single or multi-level AHB. The system interconnect 639 can be configured as an interface that couples the various components of the CPU subsystem 630 to one another. The system interconnect 639 can be coupled to the peripheral interconnect 611 to provide a signal path between the CPU subsystem 630 and components of the peripheral subsystem 610.

[0068] The system 600 can also include a number of system resources 640, including a power module 641, a clock module 643, a reset module 645, and a test module 647. The power module 641 can include a sleep control module, a wake interrupt control (WIC) module, a power-on reset (POR) module, a number of voltage references (REFs), and a PWRSYS module. In some embodiments, the power module 641 can include circuitry that allows the system 600 to draw and / or supply power from / to external sources at different voltage and / or current levels and support the controller operating in different power states, such as running, low power, or sleep. In various embodiments, more power states can be implemented when the system 600 throttles operation to achieve a desired power consumption or output. The clock module 643 can include a clock control module, a watchdog timer (WDT), an internal low-speed oscillator (ILO), and an internal main oscillator (IMO). The reset module 645 can include a reset control module and an external reset (XRES) module. The test module 647 can include modules to control and enter test modes and test control modules for analog and digital functionality (digital test and analog DFT).

[0069] The system 600 can be implemented in a monolithic (e.g., single) semiconductor die. In other embodiments, various portions or modules of the system 600 can be implemented on different semiconductor dies. For example, the memory module of the CPU subsystem 630 can be on-die or separate. In other embodiments, separate die circuitry can be packaged into a single “chip,” or remain separate and disposed on a circuit board (or in a USB cable connector) as separate components.

[0070] The system 600 can be implemented in a number of application contexts to provide USB-PD functionality thereto. In each application context, the IC controller or SOC implementing the system 600 can be set up and configured in an electronic device (e.g., a USB-enabled device) to perform operations in accordance with the techniques described herein. In one example embodiment, the system 600 can be set up and configured in a personal computer (PC) power adapter for a laptop computer, notebook computer, etc. In another example embodiment, the system 600 can be set up and configured in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smartphone, tablet computer, etc.). In another example embodiment, the system 600 can be set up and configured in a wall outlet configured to provide power through USB A- and / or C-type port(s). In another example embodiment, the system 600 can be set up and configured in a car charger configured to provide power through USB A- and / or C-type port(s). In yet another example embodiment, the system 600 can be set up and configured in a power bank that can be charged and then provide power to another electronic device through a USB A- or C-type port. In other embodiments, systems similar to the system 600 can be configured with the power switch gate control circuit described herein and can be set up in various other USB-enabled electronic or electromechanical devices.

[0071] It should be appreciated that the system, such as the system 600 implemented on or as an IC controller, can be set up into different applications, which can differ with respect to the type of power source used and the direction of power delivery. For example, in the case of a car charger, the power source is a car battery that provides DC power, while in the case of a mobile power adapter, the power source is an AC wall outlet. Further, in the case of a PC power adapter, the power delivery flow is from a provider device to a consumer device, while in the case of a power bank, the power delivery flow can be in both directions, depending on whether the power bank is operating as a power provider (e.g., powering another device) or as a power consumer (e.g., charging itself). For these reasons, the various applications of the system 600 should be considered illustrative and not limiting.

[0072] Figure 7 is a flow diagram of a method 700 of communicating information to a secondary side controller across an electrical isolation barrier according to one embodiment. The method 700 can be performed by processing logic that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. In one embodiment, a primary side controller in a primary side controlled AC-DC flyback converter performs the method 700. In another embodiment, Figure 1 the primary side controller 114 of the AC-DC flyback converter 100 performs the method 700. In another embodiment,Figure 3 The primary-side controller 314 executes method 700. In another embodiment, Figure 5 The primary IC controller 514 executes method 700. In another embodiment, Figure 6 The peripheral subsystem 610 executes method 700. In some cases, the operation of method 700 can be distributed between the primary-side controller and the secondary-side controller.

[0073] refer to Figure 7 Method 700 begins with the processing logic receiving a signal from the secondary-side controller across the electrical isolation barrier (block 702). In response to a signal for turning the primary-side power switch on and off, the processing logic applies a pulse signal to the primary-side power switch (e.g., a primary-side FET) of the flyback transformer in the AC-DC flyback converter coupled to the secondary control (block 704). The processing logic transmits information across the flyback transformer to the secondary-side controller by changing the first pulse width of the pulse signal to a second pulse width and applying a pulse signal with the second pulse width to the primary-side power switch (block 706), and method 700 ends.

[0074] In another embodiment, the processing logic receives a signal from the secondary-side controller across an electrical isolation barrier. In response to this signal, the processing logic generates a first pulse signal, the first pulse signal comprising one or more pulses having a first pulse width. The processing logic generates a second pulse signal that alters the first pulse width of at least one pulse of the first pulse signal. The processing logic outputs the second pulse signal to the primary switching FET of the power converter to transmit information from the primary-side controller to the secondary-side controller across the electrical isolation barrier.

[0075] In another embodiment, the processing logic generates one or more pulses having a first pulse width in response to a signal. The processing logic modifies the first pulse width by generating one or more additional pulses having a second pulse width. The processing logic detects a fault condition. The processing logic transmits information about the fault condition to the secondary-side controller across the flyback transformer by applying one or more additional pulses having a second pulse width.

[0076] In yet another embodiment, the processing logic receives the signal from the secondary-side controller by receiving the signal from the secondary-side controller across an electrical isolation barrier via a pulse transformer coupled between the primary-side controller and the secondary-side controller. The signal includes pulse information for turning on and off the primary-side FETs. In some cases, the pulse receiver generates a pulse signal having one or more pulses having a first pulse width in response to the signal received from the secondary-side controller across the electrical isolation barrier. The processing logic can change the first pulse width of the pulse signal to a second pulse width by generating the pulse signal having one or more additional pulses having the second pulse width.

[0077] In another embodiment, to apply the pulse signal having the second pulse width, the processing logic drives the gate of the primary-side FETs with one or more pulses having the second pulse width. The one or more pulses having the second pulse width turn on and off the primary-side FETs to control the flyback transformer.

[0078] In another embodiment, to transmit information to the secondary-side controller across the flyback transformer, the processing logic changes the first pulse width of the pulse signal to generate a particular pattern in the pulse signal. The particular pattern in the pulse signal corresponds to a fault condition.

[0079] In another embodiment, the processing logic detects a first fault condition and a second fault condition. The processing logic is to transmit information to the secondary-side controller across the flyback transformer by changing the first pulse width of the pulse signal to generate a first particular pattern in the pulse signal in response to detecting the first fault condition. The first particular pattern in the pulse signal corresponds to the first fault condition. The processing logic can also change the first pulse width of the pulse signal to generate a second particular pattern in the pulse signal in response to detecting the second fault condition. The second particular pattern in the pulse signal corresponds to the second fault condition.

[0080] In another embodiment, to transmit information to the secondary-side controller across the flyback transformer, the processing logic transmits the information from the primary-side controller to the secondary-side controller without clock synchronization between the primary-side controller and the secondary-side controller. In another embodiment, the processing logic transmits the information from the primary-side controller to the secondary-side controller without setting input buffers and output buffers between the primary-side controller and the secondary-side controller.

[0081] Figure 8is a flowchart of a method 800 of detecting a fault condition and communicating information about the fault condition to a secondary-side controller across an electrical isolation barrier according to one embodiment. The method 800 can be performed by processing logic that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. In one embodiment, the primary-side controller in an AC-DC flyback converter of a secondary-controlled performs the method 800. In another embodiment, Figure 1 the primary-side controller 114 of the AC-DC flyback converter of Figure 3 the primary-side controller 314 of the AC-DC flyback converter of Figure 5 the primary IC controller 514 of the AC-DC flyback converter of Figure 6 the peripheral subsystem 610 of the AC-DC flyback converter of In some cases, the operations of the method 800 can be distributed between the primary-side controller and the secondary-side controller.

[0082] Referring to Figure 8 the method 800 begins with the processing logic receiving a signal from a secondary-side controller across a pulse transformer (a first electrical isolation barrier) (block 802). In response to the signal for turning on and off a primary-side switch, the processing logic applies a pulse signal to a primary-side power switch that controls a flyback transformer (block 804). The processing logic determines whether a fault condition has occurred (block 805). When no fault condition has occurred at block 805, the processing logic returns to block 802 to receive another signal from the secondary-side controller. When a fault condition is determined to have occurred at block 805, the processing logic communicates information about the fault to the secondary-side controller across the flyback transformer (a second electrical isolation barrier) (block 806). At block 806, the processing logic can communicate the information about the fault condition by changing a first pulse width of the pulse signal to a second pulse width and applying the pulse signal having the second pulse width to the primary-side power switch, and the method 800 ends.

[0083] The above methods are directed to various embodiments of sending information from a primary-side controller to a secondary-side controller through an electrical isolation barrier, e.g., via the flyback transformer itself. Described below are methods of sending information from a secondary-side controller to a primary-side controller through an electrical isolation barrier, e.g., via a pulse transformer.

[0084] In one embodiment, the method includes sending, by a secondary-side controller in a secondary-controlled AC-DC flyback converter, a pulse signal across an electrical isolation barrier to a primary-side controller, the primary-side controller applying the pulse signal to a primary-side FET to turn on or turn off a flyback transformer in the secondary-controlled AC-DC flyback converter. The method also includes sending, by the secondary-side controller, an information signal across the electrical isolation barrier, the information signal including at least two consecutive ones or two consecutive zeros. In some cases, the method sends the information signal by changing a pulse sequence to include the at least two consecutive ones or two consecutive zeros. In another embodiment, the secondary-side controller sends the information signal via a pulse transformer. The secondary-side controller can include a programmable driver including a pull-up transistor, a pull-down transistor, a programmable resistive element (e.g., a resistor) that can be selectively added to the pull-up transistor, the pull-down transistor, or both, to generate the pulse sequence, e.g., two consecutive zeros or two consecutive ones.

[0085] In some embodiments, the information signal includes information about a fault condition. In another embodiment, the method detects, by the secondary-side controller, a fault condition and sends information about the fault condition in the information signal across the electrical isolation barrier. In some cases, two consecutive zeros represent the fault condition. In another embodiment, two consecutive zeros represent a header or a flag to the primary-side controller that the secondary-side controller will send a fault code. The fault code can be any combination of ones and zeros and can be of a predetermined size. Alternatively, two consecutive ones can be used for the fault condition or the header or flag of the fault code. The method can generate two consecutive zeros with two negative pulses without requiring any fast clock synchronization with the primary-side controller.

[0086] Figure 9 FIG. 9 is a flowchart of a method 900 of communicating information to a primary-side controller across an electrical isolation barrier according to one embodiment. The method 900 can be performed by processing logic that comprises hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. In one embodiment, a secondary-side controller in a secondary-controlled AC-DC flyback converter performs the method 900. In another embodiment, Figure 1 the secondary-side controller 116 of FIG. 1 performs the method 900. In another embodiment, Figure 3 the secondary-side controller 316 of FIG. 3 performs the method 900. In another embodiment, Figure 5 the secondary IC controller 516 of FIG. 5 performs the method 900. In another embodiment, Figure 6 the peripheral subsystem 610 of FIG. 6 performs the method 900. In some cases, the operations of the method 900 can be distributed between the primary-side controller and the secondary-side controller.

[0087] Referring to Figure 9 Method 900 begins with processing logic generating a first pulse set having alternating positive and negative pulses (block 902). The first pulse set can include a positive pulse on a positive transition (i.e., rising edge) of a square wave signal and a negative pulse on a negative transition (i.e., falling edge) of the square wave signal. The processing logic applies the first pulse set to a pulse transformer coupled to a primary-side controller (block 904). The first pulse set turns on and off a primary-side FET coupled to the primary-side controller. When the secondary-side controller needs to send information to the primary-side controller, the processing logic generates a second pulse set having at least two consecutive positive pulses or two consecutive negative pulses (block 906). The second pulse set can include a first positive pulse on a first positive transition (i.e., slow rising edge) of a sawtooth wave signal having a first negative transition that is faster than a second negative transition of a second positive transition. The processing logic applies the second pulse set to the pulse transformer (block 908), and method 900 ends. The second pulse set causes the primary-side controller to receive information from the secondary-side controller across an electrical isolation barrier. In other embodiments, the secondary-side controller can communicate information to the primary-side controller through the electrical isolation barrier between the primary-side controller and the secondary-side controller.

[0088] Figure 10 is a flowchart of a method 1000 of detecting a fault condition and communicating information about the fault condition to a primary-side controller across an electrical isolation barrier, according to one embodiment. Method 1000 can be performed by processing logic that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. In one embodiment, a secondary-side controller in a secondary controlled AC-DC flyback converter performs method 1000. In another embodiment, Figure 1 the secondary-side controller 116 of the secondary controlled AC-DC flyback converter 100 performs method 1000. In another embodiment, Figure 3 the secondary-side controller 316 of the secondary controlled AC-DC flyback converter 300 performs method 1000. In another embodiment, Figure 5 the secondary IC controller 516 of the secondary controlled AC-DC flyback converter 500 performs method 1000. In another embodiment, Figure 6 the peripheral subsystem 610 of the secondary controlled AC-DC flyback converter 600 performs method 1000. In some cases, the operations of method 1000 can be distributed between the primary-side controller and the secondary-side controller.

[0089] Referring to Figure 10Method 1000 begins with processing logic generating a first pulse set having alternating positive and negative pulses (block 1002). The first pulse set can include a positive pulse on a positive transition (i.e., rising edge) of a square wave signal and a negative pulse on a negative transition (i.e., falling edge) of the square wave signal. The processing logic applies the first pulse set to a pulse transformer coupled to a primary side controller (block 1004). The first pulse set turns on and off a primary side FET coupled to the primary side controller.

[0090] The processing logic determines whether a fault condition has occurred (block 1005). When no fault condition has occurred at block 1005, the processing logic returns to block 1002 to receive another signal from the secondary side controller. When a fault condition is determined to have occurred at block 1005, the processing logic communicates information about the fault across the pulse transformer (an electrical isolation barrier) to the primary side controller (block 1006). At block 1006, the processing logic can communicate information about the fault condition by sending a second pulse set having at least two consecutive negative pulses or two consecutive positive pulses, and the method 1000 ends.

[0091] In another embodiment, the processing logic determines that the fault condition requires the system to shut down, and sends information to the primary side controller to initiate a system shutdown, such as by firmware initiation. This can be done after the secondary side controller detects the fault condition and determines that the fault condition requires the system to shut down.

[0092] In another embodiment, the processing logic controls a programmable slow pull-up transistor at the input of the pulse transformer followed by a faster pull-down transistor to generate a first negative pulse. The processing logic controls a programmable slow pull-up transistor at the input of the pulse transformer followed by a faster pull-down transistor to generate a second negative pulse without an intervening positive pulse (e.g., two -ve edges without a +ve edge). In one embodiment, the processing logic controls the programmable slow pull-up transistor with a resistive pull-up transistor (or resistive pull-down transistor). In another embodiment, the processing logic controls the programmable slow pull-up transistor with a current source based pull-up transistor. In another embodiment, the processing logic controls a programmable slow pull-down transistor at the input of the pulse transformer followed by a faster pull-up transistor to generate a first positive pulse, and controls a programmable slow pull-down transistor at the input of the pulse transformer followed by a faster pull-up transistor to generate a second positive pulse without an intervening negative pulse (e.g., two +ve edges without a -ve edge). The pattern of two or more consecutive ones or zeros and ones can be used to communicate multiple fault conditions or other information from the secondary side controller to the primary side controller. Particular patterns can include a start pattern, a stop pattern, a soft fault requiring a soft start, a soft fault requiring a minimum delivered power, and more.

[0093] In the description above, some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, is conceived to be a self- consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0094] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "receiving", "adjusting" or the like, refer to the actions and processes of a computing system, or similar electronic computing device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system memories or registers or other such information storage, transmission or display devices.

[0095] The words "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term "an embodiment" or "one embodiment" or "an implementation" or "one implementation" throughout is not intended to mean the same embodiment or implementation unless specifically so stated.

[0096] The embodiments described herein can also relate to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a non-transitory computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, flash memories, or any type of media suitable for storing electronic instructions. The term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" should also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methodologies of the present embodiments. The term "computer-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methodologies of the present embodiments.

[0097] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description to follow. In addition, the present embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the embodiments as described herein.

[0098] The above description sets forth numerous specific details such as examples of specific systems, components, methods and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that the above-described embodiments are not limited to these specific details. The description above is intended to be illustrative, not limiting. Having thus described several aspects of at least one embodiment, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the scope of the claims.

Claims

1. A method for a secondary controlled alternating current to direct current (AC-DC) flyback converter, comprising: receiving, by a primary side controller in the secondary controlled alternating current to direct current (AC-DC) flyback converter, a control signal from a secondary side controller across an electrical isolation barrier; converting, by the primary side controller, the control signal into a first pulse signal having a first pulse width; applying, by the primary side controller, the first pulse signal to a primary side field effect transistor (FET) coupled to a flyback transformer in the secondary controlled alternating current to direct current (AC-DC) flyback converter in response to converting the control signal, the first pulse signal for turning on or off the primary side field effect transistor (FET); and communicating, by the primary side controller, information to the secondary side controller across the flyback transformer by changing the first pulse signal having the first pulse width to generate a second pulse signal having a second pulse width and applying the second pulse signal having the second pulse width to the primary side field effect transistor (FET), the second pulse signal for turning on or off the primary side field effect transistor (FET), wherein changing the first pulse signal having the first pulse width comprises converting the control signal into the second pulse signal having the second pulse width, and wherein communicating the information to the secondary side controller comprises communicating information about a fault condition across a second electrical isolation barrier of the flyback transformer by applying one or more additional pulses having the second pulse width that cause the secondary side controller to detect a decreasing voltage on a secondary side drain of a secondary side field effect transistor (FET) using negative sense (NSN).

2. The method of claim 1, further comprising: generating, by the primary side controller, one or more pulses having the first pulse width in response to the control signal, wherein changing the first pulse signal having the first pulse width comprises generating, by the primary side controller, one or more additional pulses having the second pulse width; and detecting, by the primary side controller, the fault condition.

3. The method of claim 1, wherein, Receiving the control signal from the secondary side controller comprises receiving the control signal from the secondary side controller across the electrical isolation barrier via a pulse transformer coupled between the primary side controller and the secondary side controller, wherein the control signal comprises pulse information for turning on and off the primary side field effect transistor (FET).

4. The method of claim 1, wherein, The primary side controller comprises a pulse receiver, and wherein the method further comprises: generating, by the pulse receiver, the first pulse signal having one or more pulses with the first pulse width in response to the control signal received from the secondary-side controller across the electrical isolation barrier, wherein changing the first pulse signal having the first pulse width to the second pulse signal having the second pulse width comprises generating, by the pulse receiver, the second pulse signal having one or more additional pulses with the second pulse width.

5. The method of claim 1, wherein, applying the second pulse signal having the second pulse width comprises driving, by a gate driver, a gate of the primary-side field effect transistor (FET) with the one or more additional pulses having the second pulse width, wherein the one or more pulses having the second pulse width turn on and off the primary-side field effect transistor (FET) to control the flyback transformer.

6. The method of claim 1, wherein, communicating information to the secondary-side controller across the flyback transformer comprises changing the first pulse signal having the first pulse width to generate a particular pattern in the second pulse signal, and wherein the particular pattern in the second pulse signal corresponds to the fault condition.

7. The method of claim 1, further comprising: detecting a first fault condition; and detecting a second fault condition, wherein communicating information to the secondary-side controller across the flyback transformer comprises changing the first pulse signal having the first pulse width to generate a first particular pattern in the second pulse signal in response to detecting the first fault condition, wherein the first particular pattern in the second pulse signal corresponds to the first fault condition, wherein communicating information to the secondary-side controller across the flyback transformer comprises changing the first pulse signal having the first pulse width to generate a second particular pattern in the second pulse signal in response to detecting the second fault condition, and wherein the second particular pattern in the second pulse signal corresponds to the second fault condition.

8. The method of claim 1, wherein, communicating information to the secondary-side controller across the flyback transformer comprises communicating the information from the primary-side controller to the secondary-side controller without clock synchronization between the primary-side controller and the secondary-side controller.

9. The method of claim 1, wherein, communicating information to the secondary-side controller across the flyback transformer comprises communicating the information from the primary-side controller to the secondary-side controller without input and output buffers between the primary-side controller and the secondary-side controller.

10. An alternating current to direct current (AC-DC) flyback converter comprising: a primary-side field effect transistor (FET); a flyback transformer of the alternating current to direct current (AC-DC) flyback converter, the flyback transformer coupled to the primary-side field effect transistor (FET); and a primary-side controller coupled to the flyback transformer, wherein the primary-side controller is configured to: receive a control signal from a secondary-side controller across a first electrical isolation barrier; convert the control signal to a first pulse signal having a first pulse width; apply the first pulse signal to the primary-side field effect transistor (FET) to turn on and turn off the primary-side field effect transistor (FET) in response to the control signal; and generate a second pulse signal having a second pulse width by changing the first pulse signal having the first pulse width and apply the second pulse signal having the second pulse width to the primary-side field effect transistor (FET) to communicate information across a second electrically isolated barrier of the flyback transformer to the secondary-side controller, the second pulse signal to turn on or turn off the primary-side field effect transistor (FET), wherein changing the first pulse signal having the first pulse width comprises converting the control signal to the second pulse signal having the second pulse width, and wherein the secondary-side controller communicates information about a fault condition across the second electrically isolated barrier of the flyback transformer by applying one or more additional pulses having the second pulse width that cause the secondary-side controller to detect a decreasing voltage on a secondary drain of a secondary-side field effect transistor (FET) using negative sense (NSN) in response to the primary-side controller communicating the information.

11. The alternating current to direct current (AC-DC) flyback converter of claim 10, further comprising a pulse transformer coupled between the primary side controller and the secondary side controller, wherein, the primary-side controller is configured to receive the control signal as one or more pulses from the secondary-side controller via the pulse transformer.

12. The alternating current to direct current (AC-DC) flyback converter of claim 10, wherein, the primary-side controller comprises: a pulse receiver to receive the control signal from the secondary-side controller across the electrically isolated barrier; and a gate driver coupled to the pulse receiver and a gate of the primary-side field effect transistor (FET).

13. The alternating current to direct current (AC-DC) flyback converter of claim 10, further comprising: a rectifier coupled between an alternating current (AC) input terminal and an AC line (Vin), wherein the AC line is coupled to a first end of a primary winding of the flyback transformer, wherein a second end of the primary winding is coupled to a primary drain of the primary-side field effect transistor (FET), wherein a first end of a secondary winding of the flyback transformer is coupled to a direct current (DC) output line (VBUS), and a second end of the secondary winding is coupled to the secondary drain of the secondary-side field effect transistor (FET); and a bulk capacitor coupled between the AC line and a ground node, wherein to apply the first pulse signal to the primary-side field effect transistor (FET), the primary-side controller is configured to: apply a turn-on pulse of the first pulse signal to a gate of the primary-side field effect transistor (FET), the turn-on pulse to cause a primary drain of the primary-side field effect transistor (FET) to go low and the secondary drain of the secondary-side field effect transistor (FET) to go high; applying an off pulse to the gate of the primary side field effect transistor (FET), the off pulse turning the primary side field effect transistor (FET) high and turning the secondary drain of the secondary side field effect transistor (FET) low.

14. The alternating current to direct current (AC-DC) flyback converter of claim 13, wherein, the secondary side controller is configured to: determine an amount of time between a start of the off pulse and the negative sense (NSN) turning high, wherein the amount of time corresponds to a fixed time when the first pulse signal includes the on pulse and the off pulse of the first pulse width, and wherein the amount of time corresponds to an extended time when the second pulse signal includes the on pulse and the off pulse of the second pulse width.

15. The alternating current to direct current (AC-DC) flyback converter of claim 13, wherein, the primary side controller includes a fault detection circuit to detect the fault condition, wherein the primary side controller is configured to communicate information about the fault condition across the flyback transformer to the secondary side controller by changing the first pulse signal having the first pulse width to the second pulse signal having the second pulse width and applying the second pulse signal having the second pulse width to the primary side field effect transistor (FET) in response to detecting the fault condition.

16. The alternating current to direct current (AC-DC) flyback converter of claim 13, wherein, the primary side controller includes a fault detection circuit to detect a first fault condition in a first situation and a second fault condition in a second situation, wherein the primary side controller is configured to communicate information about the first fault condition across the flyback transformer to the secondary side controller in response to detecting the first fault condition, and wherein the primary side controller is configured to communicate information about the second fault condition across the flyback transformer to the secondary side controller in response to detecting the second fault condition.

17. The alternating current to direct current (AC-DC) flyback converter of claim 13, wherein, the primary side controller configured to communicate the information across the flyback transformer to the secondary side controller is configured to change the first pulse signal having the first pulse width to generate a particular pattern in the second pulse signal, and wherein the particular pattern in the second pulse signal corresponds to the fault condition of the primary side controller.

18. An alternating current to direct current (AC-DC) power adapter device comprising: a power converter including a flyback transformer and a rectifier coupled between AC terminals and DC terminals, the rectifier to convert AC power on the AC terminals to DC power on the DC terminals and the flyback transformer to provide electrical isolation between the AC terminals and the DC terminals; a primary side controller coupled to the flyback transformer; a secondary side controller coupled to the flyback transformer; a primary side power switch; and a secondary side power switch, wherein the primary side controller is configured to: receive a first signal from the secondary side controller across an electrical isolation barrier; convert the first signal to a second signal having a first pulse width; ​ applying a second signal to the primary-side power switch in response to the first signal for turning on and off the primary-side power switch; and communicating information to the secondary-side controller across the flyback transformer by changing the second signal having the first pulse width to a third signal having a second pulse width and applying the third signal having the second pulse width to the primary-side power switch, the third signal for turning on or off the primary-side power switch, wherein changing the second signal having the first pulse width comprises converting the second signal to the third signal having the second pulse width, and wherein the secondary-side controller responds to the primary-side controller communicating the information by communicating information about a fault condition across a second electrically isolated barrier of the flyback transformer by applying one or more additional pulses having the second pulse width that cause the secondary-side controller to detect a decreasing voltage on a secondary-side power switch secondary-side drain using negative sense (NSN).

19. The alternating current to direct current (AC-DC) power adapter device of claim 18, further comprising a pulse transformer coupled between the primary side controller and the secondary side controller, wherein, the primary-side controller is configured to receive the first signal as one or more pulses from the secondary-side controller via the pulse transformer.

20. The alternating current to direct current (AC-DC) power adapter device of claim 18, wherein, the primary-side controller comprises: a pulse receiver to receive the first signal from the secondary-side controller across the electrically isolated barrier, wherein the first signal comprises a first turn-on pulse to turn on the primary-side power switch and a first turn-off pulse to turn off the primary-side power switch; a fault detection circuit to detect the fault condition; and a driver coupled to the pulse receiver and the primary-side power switch, wherein the driver is configured to apply the first turn-on pulse and the first turn-off pulse to the primary-side power switch, wherein the fault detection circuit is configured to: cause the pulse receiver to change the second signal having the first pulse width to the third signal having the second pulse width; and cause the driver to apply the third signal having the second pulse width to the primary-side power switch.

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