A method, apparatus and processor for branch prediction

Abstract

The present application provides a method and apparatus for branch prediction and a processor. The method is used for the instruction execution of a processor and includes: obtaining the result of branch feedback; generating a branch prediction feedback value according to the result of the branch feedback and the value of a global branch history register; determining that if the fetched instruction is a branch instruction, performing an exclusive OR operation on the instruction address and the branch prediction feedback value; using the result of the exclusive OR operation as an index address to obtain a decision counter for predicting a branch jump from a pattern history table; predicting whether the branch jumps according to the status value of the decision counter. The branch prediction accuracy is improved through the feedback of the branch execution situation.

Description

Technical Field

[0001] This application relates to the field of processors, and in particular, to a method, apparatus, and processor for branch prediction. Background Art

[0002] Modern high-performance processors all adopt pipeline technology. However, the use of pipeline technology inevitably generates control hazards. A control hazard refers to a situation where the pipeline cannot determine the address of the next instruction in advance when executing a branch instruction, resulting in a delay.

[0003] In a classic five-stage pipeline, it includes five stages: instruction fetch, decode, execute, memory access, and write-back. The processor needs to extract instructions through the instruction address in the instruction fetch stage, while a branch instruction can only determine the extraction address of the next instruction in the memory access stage. This causes the pipeline to wait, and at this time, the processor is in an idle stage, wasting many clock cycles and reducing performance. Summary of the Invention

[0004] This application aims to provide a method, apparatus, and processor for branch prediction. By using an additional branch prediction unit to feedback the execution situation of branches, it can maintain a high prediction accuracy rate, reduce the waste of clock cycles, reduce power consumption, and optimize the performance of the processor.

[0005] According to one aspect of this application, a method for branch prediction for instruction execution of a processor is proposed, including:

[0006] Obtaining the result of branch feedback;

[0007] Generating a branch prediction feedback value according to the result of branch feedback and the value of the global branch history register;

[0008] Judging that if the fetched instruction is a branch instruction, performing an exclusive OR operation on the instruction address and the branch prediction feedback value;

[0009] Using the result of the exclusive OR operation as an index address to obtain a decision counter for predicting branch jumps from a pattern history table;

[0010] Predicting whether the branch jumps according to the status value of the decision counter.

[0011] According to some embodiments, the foregoing method further includes that generating the branch prediction feedback value includes:

[0012] Concatenating the result of branch feedback with the high bits of the global branch history register to obtain the branch prediction feedback value.

[0013] According to some embodiments, the foregoing method further includes that obtaining the result of branch feedback includes:

[0014] Obtain a branch feedback enable signal;

[0015] According to the branch feedback enable signal, select the lower bits of the global branch history register or the branch feedback history register as the result of branch feedback, where the branch feedback history register is used to record branch feedback information.

[0016] According to some embodiments, the foregoing method further includes: according to the relationship between the branch instruction register values, select an operation mode, perform an operation on the branch instruction register values, and update the branch feedback history register with the obtained operation result.

[0017] According to some embodiments, the foregoing method further includes:

[0018] Compare the operation result with a preset value, and update the branch feedback enable signal according to the comparison result.

[0019] According to some embodiments, the foregoing method further includes, according to the relationship between the branch instruction register values, selecting an operation mode, and further includes:

[0020] If the fetched instruction is a loop branch instruction, perform a subtraction operation on the branch instruction register value and take the absolute value to obtain an operation result.

[0021] According to some embodiments, the foregoing method further includes:

[0022] Compare the operation result with a preset value. If the operation result is less than or equal to the preset value, set the branch feedback history enable signal to 1.

[0023] According to some embodiments, the foregoing method further includes that the preset value is greater than or equal to the loop step of the loop branch instruction.

[0024] According to some embodiments, the foregoing method further includes: when the branch instruction execution ends, update the global branch history register and the decision counter obtained by indexing according to the branch instruction jump result.

[0025] According to another aspect of the present application, there is provided a branch prediction device for the instruction execution of a processor, including:

[0026] A global branch history register for recording the jump situations of all branch instructions;

[0027] A branch feedback unit for obtaining the result of branch feedback;

[0028] A branch feedback value generation unit for generating a branch prediction feedback value according to the result of branch feedback and the value of the global branch history register;

[0029] An exclusive-OR calculation unit, which, if the fetched instruction is a branch instruction, performs an exclusive-OR operation on the instruction address and the branch prediction feedback value;

[0030] A pattern recognition table index unit, which uses the result of the exclusive-OR operation as an index address to obtain a decision counter for predicting a branch jump from a pattern history table;

[0031] A predicted jump unit, which predicts whether a branch jumps according to the status value of the decision counter.

[0032] According to some embodiments, the foregoing device further includes: The branch feedback unit includes a branch feedback detector, a branch feedback history register, an enable unit, and a multiplexer;

[0033] The branch feedback detector performs an operation according to the branch instruction register value;

[0034] The branch feedback history register is used to record the operation result of the branch feedback detector;

[0035] The enable unit is used to enable the multiplexer to select the branch feedback history register or the global branch history register to generate a branch prediction feedback value;

[0036] The multiplexer is used to update the branch feedback history enable signal and the branch feedback history register according to the operation result of the branch feedback detector.

[0037] According to some embodiments, the foregoing device further includes: a branch result recording unit and a pattern history table updating unit:

[0038] The branch result recording unit is used to update the global branch history register according to the branch instruction jump result;

[0039] The pattern history table updating unit is used to update the decision counter obtained by indexing according to the branch instruction jump result.

[0040] According to another aspect of the present application, there is provided a processor, which includes any one of the foregoing devices.

[0041] According to the exemplary embodiments of the present application, by providing additional information feedback on the branch execution situation, the branch prediction accuracy can be improved, the waste of clock cycles can be reduced, the power consumption can be reduced at the same time, and the performance of the processor can be optimized.

[0042] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present application. Description of the Drawings

[0043] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments.

[0044] Figure 1 Shows the schematic diagram of the implementation of G-share according to an exemplary embodiment of the present application.

[0045] Figure 2 Shows the schematic diagram of the working principle of the decision counter according to an exemplary embodiment of the present application.

[0046] Figure 3 Shows the schematic diagram of performing branch prediction according to an exemplary embodiment of the present application.

[0047] Figure 4 Shows the flowchart of the branch prediction method according to an exemplary embodiment of the present application.

[0048] Figure 5 Shows the block diagram of the branch prediction device according to an exemplary embodiment of the present application.

[0049] Figure 6 Shows the block diagram of the branch prediction device according to another exemplary embodiment of the present application. Detailed implementation manners

[0050] Now, the exemplary embodiments will be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus their repeated description will be omitted.

[0051] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0052] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0053] The flowcharts shown in the accompanying drawings are merely illustrative and not necessarily include all contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0054] It should be understood that although terms such as first, second, and third may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of the concept of the present application. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more of them.

[0055] Those skilled in the art can understand that the drawings are only schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing the present application. Therefore, they cannot be used to limit the protection scope of the present application.

[0056] In a computer architecture, a branch predictor is a digital circuit that guesses which branch will be executed before the execution of a branch instruction ends, in order to improve the performance of the instruction pipeline of the processor. The purpose of using a branch predictor is to improve the process of instruction pipelining. Branch predictors are very critical technologies for modern instruction pipeline microprocessors to achieve high performance.

[0057] Currently, the relatively common branch prediction technology is G-share. The implementation principle of G-share is as Figure 1 shown.

[0058] As Figure 1 can be seen, G-share includes the following parts:

[0059] PC refers to the fetch address of the current branch instruction stored in the program counter.

[0060] GBHSR (Global Branch History Shift Register), the global branch history shift register, refers to recording the jump situations of all branch instructions before this, and using a shift register to record.

[0061] PHT (Pattern History Table), the pattern history table, is a decision index table used to predict whether the current branch instruction will jump.

[0062] The working process of G-share is as follows:

[0063] (1) Exclusive OR the lower n bits of the PC and the lower n bits of the GBHSR to obtain the index idx.

[0064] (2) Use the idx obtained in (1) to index the PHT to obtain a 2-bit decision counter for branch prediction jumps.

[0065] (3) The working principle of the decision counter in (2) is as Figure 2 shown.

[0066] As Figure 2 known, the 2-bit decision counter has a total of four states: "strong jump", "weak jump", "strong no jump", and "weak no jump". Whenever the result of a branch instruction is "jump", the decision counter will increase the state value in the direction of "strong jump"; whenever the result of a branch instruction is "no jump", the decision counter will decrease the state value in the direction of "strong no jump".

[0067] (4) At the end of the execution of the branch instruction, update the values of the GBHSR and the decision counter according to the execution result of the branch instruction.

[0068] The global branch history shift register GBHSR used in the G-share algorithm does not maintain a dedicated history record for each conditional jump instruction. Instead, it maintains a shared history record for all conditional jump instructions. The advantage is that it can identify the correlation between different jump instructions. The disadvantage is that the history record is diluted by the execution of irrelevant different conditional jump instructions; if there are too many different branch instructions, there may not even be a single bit of the history record from the same branch instruction.

[0069] In addition, when executing a loop branch instruction, as the number of loop iterations increases, the branch jump situation recorded by the global branch history shift register GBHSR will be squeezed out. At this time, the same pattern history table PHT will be indexed. When the pipeline executes the branch instruction to jump out of the loop, the G-share algorithm always predicts incorrectly, thus reducing the accuracy of branch prediction.

[0070] According to some technical solutions, although the use of multiple groups of GBHR and a multi-level indexing mechanism improves the branch prediction accuracy to a certain extent, there are still the following deficiencies:

[0071] The solution using multiple groups of GBHR will increase the hardware area of the branch prediction unit and inevitably increase the power consumption.

[0072] The solution implementing the branch prediction algorithm using a two-level indexing mechanism will increase the latency, reduce the performance of the instruction fetch module, and increase the implementation difficulty of the instruction fetch module.

[0073] In the solution, since the PC is used to index the GBHR, as the number of loops increases, the branch jump information recorded in the GBHR will be overwritten. At this time, the same PHT will be indexed. When the pipeline executes the branch instruction to jump out of the loop, this solution always predicts incorrectly, reducing the accuracy of branch prediction.

[0074] For most loop structures, they can be described in C language using the following template:

[0075] (1) Increasing loop

[0076]

[0077]

[0078] (A) Before the loop starts, first assign the initial value S of the loop variable to the loop variable i, and then assign the loop step P and the loop end flag E to the registers.

[0079] (B) When the loop starts, first check whether the loop variable i is equal to the loop end flag. This instruction is a branch instruction.

[0080] (a) If they are not equal, it means the loop has not ended.

[0081] When the loop has not ended, the structural code of the loop body should be executed sequentially.

[0082] After the execution of the structural code of the loop body, the loop variable i should be incremented by the step P for the next branch instruction to judge.

[0083] After the execution of the structural code of the loop body and the increment of the loop variable i, it should jump to the branch instruction at the start of the loop to judge whether the next loop will be executed.

[0084] (b) If they are equal, it means the loop has ended, and it should jump to the code position ExitLoop at the end of the loop to execute the next instruction.

[0085] (2) Decreasing loop

[0086]

[0087] (3) Nested loop

[0088]

[0089]

[0090] (A) Before the loop starts, first assign the initial value S of the loop variable to the loop variable i, and then assign the loop step P and the loop end flag E to the registers.

[0091] (B) When the loop starts, first check whether the loop variable i is equal to the loop end flag. This instruction is a branch instruction.

[0092] (a) If they are not equal, it means the loop has not ended.

[0093] When the loop has not ended, the structural code of the loop body should be executed sequentially.

[0094] After the execution of the structural code of the loop body, the loop variable i should be decremented by the step size P for the next branch instruction to judge.

[0095] After the execution of the structural code of the loop body and the decrement of the loop variable i, it should jump to the branch instruction at the start of the loop to determine whether the next loop will be executed.

[0096] (b) If they are equal, it means the loop has ended, and it should jump to the code position ExitLoop at the end of the loop to execute the next instruction.

[0097] For the above type of loop structure, if the existing branch prediction technology is adopted, the historical execution situation of each jump instruction beq will be recorded in the GBHR. However, as the number of loop iterations increases, the value of the GBHR will be squeezed out by the latest jump situation. This will cause the current branch prediction technology to be unable to accurately determine when the loop exits.

[0098] Therefore, this application proposes a branch prediction method and device, which can greatly improve the branch prediction accuracy by providing additional information feedback on the branch execution situation.

[0099] Next, taking the loop branch instruction as an example, the technical solution according to the embodiment of this application will be described. Those skilled in the art can easily understand that the technical solution according to the embodiment of this application can be applied to branch instruction prediction scenarios other than loop branch instructions.

[0100] The following will illustrate the exemplary embodiments of this application with reference to the accompanying drawings.

[0101] Figure 3 A schematic diagram showing the execution of branch prediction according to the exemplary embodiment of this application. Figure 4 A flowchart showing the branch prediction method according to the exemplary embodiment of this application. Figure 4 The method shown can be implemented through Figure 3 the execution process shown.

[0102] The following will Figure 3 、 Figure 4 be used to describe in detail the branch prediction method proposed in this application.

[0103] A processor based on the classic five-stage pipeline of the RISC-V instruction set divides the pipeline functional modules into five functional modules: instruction fetch, decode, execute, memory access, and write-back.

[0104] The first stage in the five-stage pipeline, instruction fetch, refers to the process of reading instructions from the memory.

[0105] Decode refers to the process of translating the instructions fetched from the memory. After decoding, the register indices of the operands required by the instructions can be obtained, and these indices can be used to read the operands from the general-purpose register file. The decode stage decodes the fetched instructions. Except for branch instructions, other instructions also require registers.

[0106] Execute: After the instruction is decoded and the types of calculations required are known, and the required operands have been read from the general-purpose register file, the instruction execution follows. Instruction execution refers to the process of performing the actual operation on the instruction. For example, if the instruction is an addition operation instruction, an addition operation is performed on the operands; if it is a subtraction operation instruction, a subtraction operation is performed.

[0107] Memory access: Memory access instructions are often one of the most important instruction types in the instruction set. Memory access (MemoryAccess) refers to the process of reading data from the memory or writing data to the memory by memory access instructions.

[0108] Write-back (Write-Back) refers to the process of writing the result of the instruction execution back to the general-purpose register file. If it is an ordinary arithmetic instruction, the result value comes from the result calculated in the "execute" stage; if it is a memory read instruction, the result comes from the data read from the memory in the "memory access" stage.

[0109] See Figure 4 , in S401, obtain the feedback result of branch execution.

[0110] According to some embodiments, read the values in the branch feedback history register and the global branch history register. See Figure 3 , the global branch history register GBHR refers to recording the jump situations of all branch instructions before this. The branch feedback history register FBHR records branch feedback information. The number of bits of F here can be determined according to the arithmetic relationship of the branch instruction register value.

[0111] In S403, generate a branch prediction feedback value according to the feedback result of branch execution and the value in the global branch history register.

[0112] According to the branch feedback history enable signal FB_EN, select the lower bits of the branch feedback history register or the global branch history register, and splice them with the higher bits of the global branch history register to generate a branch prediction feedback value.

[0113] FB_EN is the branch feedback history enable signal, which is used by the multiplexer to select the data source. For example, the multiplexer is enabled by the FB_EN signal to select either the branch feedback history register (such as the branch feedback history register of the F bit, hereinafter referred to as FBHR) or the low F bits of the global branch history register GBHR, and splice them with the high M bits of GBHR to generate a new number, called the branch prediction feedback value.

[0114] In S405, if it is determined that the fetched instruction is a branch instruction, then the exclusive OR operation is performed on the instruction address and the branch prediction feedback value.

[0115] According to some embodiments, in the instruction fetch stage, if the fetched instruction is a branch instruction, then the exclusive OR operation is performed on the instruction address PC and the branch prediction feedback value as the index address of the pattern history table PHT.

[0116] See Figure 3 , PC refers to the fetch address of the current branch instruction stored in the program counter. The pattern history table PHT is a decision index table used to predict whether the current branch instruction will jump.

[0117] In S407, the result of the exclusive OR operation is used as the index address to index the pattern history table to obtain the decision counter for predicting the branch jump.

[0118] According to some embodiments, the PHT indexes the corresponding 2-bit decision counter according to the index address obtained in S405, and predicts whether to jump according to the situation of the 2-bit decision counter.

[0119] In S409, it is predicted whether the branch jumps according to the status value of the decision counter.

[0120] Predict a jump when the status in the 2-bit decision maker is "strong jump" or "weak jump";

[0121] Predict no jump when the status in the 2-bit decision maker is "strong no jump" or "weak no jump".

[0122] When a branch instruction is executed to completion, the branch feedback detector performs an operation according to the execution situation of this instruction.

[0123] The operation update process of the branch feedback detector: By operating on the values of the two registers mem_rs1 and mem_rs2 stored in the memory access stage, and comparing with a preset value (for example, the feedback accuracy x), FBHR and FB_EN are updated. The operation result of the branch feedback detector is saved in FBHR. The FB_EN signal indicates whether the loop is about to end.

[0124] SeeFigure 3 mem_rs1 and mem_rs2 are the two register values of the previous branch instruction. Except for branch instructions, other instructions also require registers. As the branch instructions are updated, mem_rs1 and mem_rs2 will also be updated.

[0125] For example, in the case of an incrementing loop, mem_rs1 is incremented continuously. When mem_rs1 and mem_rs2 are equal, the loop exits. In this case, only the subtraction operation of mem_rs1 and mem_rs2 needs to be performed, and the absolute value of the subtraction is compared with a feedback accuracy x, where the feedback accuracy x needs to be greater than or equal to the step size P, otherwise this comparison is meaningless.

[0126] If the value in FBHR is less than or equal to x, it means that the loop instruction is about to end. At this time, the FB_EN signal is set to 1 to make the multiplexer select the FBHR signal. Specifically as follows:

[0127] mem-rs1 mem-rs2 FBHR P x FB_EN 0 10 10 2 3 0 2 10 8 2 3 0 4 10 6 2 3 0 6 10 4 2 3 0 8 10 2 2 3 1 10 10 0 2 3 1

[0128] For other loop types, the feedback detector can select the most suitable operation method by itself. The suitable method means that the feedback detector can have other operation methods. Specifically, in one case, for the most common incrementing loop, the feedback detector can select the method of taking the absolute value of the subtraction.

[0129] The feedback detector of the present application can take the two register values mem_rs1 and mem_rs2 of the branch instruction as feedback through a certain operation, predict the relationship between the two register values mem_rs1 and mem_rs2 in advance, and then predict whether the branch instruction jumps.

[0130] It is also applicable to non-loop instructions and can also improve the accuracy. Because for branch instructions, the relationship between the two registers rs1 and rs2 represents whether to jump. This relationship includes: rs1 = rs2, rs1 ≠ rs2, rs1 > rs2, etc.

[0131] Taking the most common incrementing loop as an example, the absolute value of the subtraction operation of rs1 and rs2 is taken as feedback in the feedback detector.

[0132] When a branch instruction is executed and completed, the branch result recording unit and the PHT update unit will be updated according to the jump situation of the branch instruction. When the branch result recording unit and the PHT update unit are updated, GBHR and the indexed 2-bit decision maker will be updated.

[0133] GBHR uses "0" to represent that the branch does not jump and "1" to represent that the branch jumps. When the branch instruction is executed and completed, its execution situation will be recorded in this register through shifting.

[0134] The 2-bit decision counter includes four states: "strong jump", "weak jump", "strong no-jump", and "weak no-jump". If the result of the branch instruction is "jump", the decision counter will increase the status value in the direction of "strong jump"; if the result of the branch instruction is "no-jump", the decision counter will decrease the status value in the direction of "strong no-jump". When the branch instruction is executed, its execution situation will cause the indexed 2-bit decision counter to jump to the next state.

[0135] Figure 5 The block diagram of a branch prediction method and apparatus according to an exemplary embodiment of the present application is shown. Figure 6 The block diagram of a branch prediction apparatus according to another exemplary embodiment of the present application is shown.

[0136] See Figure 5 , the branch prediction apparatus includes a global branch history register 501 for recording the jump situations of all branch instructions.

[0137] A branch feedback unit 502 for obtaining the result of branch feedback.

[0138] A branch feedback value generation unit 503 for generating a branch prediction feedback value according to the result of branch feedback and the value of the global branch history register.

[0139] An exclusive-OR calculation unit 504, which, if the fetched instruction is a branch instruction, performs an exclusive-OR operation on the instruction address and the branch prediction feedback value.

[0140] A pattern history table index unit 505 uses the result of the exclusive-OR operation as an index address to obtain a decision counter for predicting branch jumps from the pattern history table.

[0141] A predicted jump unit 506 predicts whether a branch jumps according to the status value of the decision counter.

[0142] See Figure 6 , the branch feedback unit 502 in the branch prediction apparatus further includes a branch feedback detector 601, a branch feedback history register 602, an enable unit 603, and a multiplexer 604.

[0143] The branch feedback detector 601 performs operations according to the branch instruction register value and updates the branch feedback history enable signal and the branch feedback history register according to the operation result.

[0144] The branch feedback history register 602 is used to record the operation result of the branch feedback detector.

[0145] The enable unit 603 is used to receive the branch feedback history enable signal to enable the multiplexer.

[0146] A multiplexer 604 for selecting a branch feedback history register or a global branch history register to generate a branch prediction feedback value.

[0147] According to some embodiments, the apparatus for branch prediction further includes a branch result recording unit and a pattern history table updating unit (not shown in the figure).

[0148] The branch result recording unit is configured to update the global branch history register according to the jump result of the branch instruction.

[0149] The pattern history table updating unit is configured to update the decision counter obtained by indexing according to the jump result of the branch instruction.

[0150] According to some embodiments, the branch feedback unit 502 reads the branch feedback history register 602 and the global branch history register 501.

[0151] When the execution of a branch instruction ends, the branch feedback detector 601 performs an operation according to the execution status of this instruction.

[0152] According to some embodiments, the operation update process of the branch feedback detector 601: by performing an operation on the values of two registers, mem_rs1 and mem_rs2, stored in the memory access stage, and comparing with a preset value (for example, the feedback accuracy x), so as to update the branch feedback history register 602 and the branch feedback history enable signal FB_EN.

[0153] The branch feedback value generation unit 503 selects the lower bits of the branch feedback history register 602 or the global branch history register 501 according to the branch feedback history enable signal FB_EN, and splices them with the higher bits of the global branch history register to generate a branch prediction feedback value.

[0154] FB_EN is the branch feedback history enable signal for the multiplexer 604 to select the data source. For example, the multiplexer 604 is enabled by the FB_EN signal enabling unit 603 to select the branch feedback history register 602 or the global branch history register 501.

[0155] According to some embodiments, if the fetched instruction is a branch instruction, the exclusive OR calculation unit 504 performs an exclusive OR operation on the instruction address and the branch prediction feedback value.

[0156] According to some embodiments, in the instruction fetch stage, if the fetched instruction is a branch instruction, then the instruction address PC and the branch prediction feedback value are subjected to an exclusive OR operation as the index address of the pattern history table PHT.

[0157] The mode history table index unit 505 uses the result of the exclusive OR operation as an index address to index the mode history table, and obtains a decision counter for predicting branch jumps.

[0158] According to some embodiments, the prediction jump unit 506 predicts whether to jump according to the situation of the decision counter.

[0159] Some designs of the present application may use methods such as forwarding modified feedback data, logical circuits, and modifying arithmetic methods to achieve the same implementation method as the present application for feedback of branch instruction information.

[0160] It should be clearly understood that the present application describes how to form and use specific examples, but the present application is not limited to any details of these examples. Instead, based on the teachings of the content disclosed in the present application, these principles can be applied to many other embodiments.

[0161] Those skilled in the art can understand that all or part of the steps for implementing the above embodiments are implemented as a computer program executed by a CPU. When the computer program is executed by the CPU, the program for implementing the above functions defined by the above method provided by the present application can be stored in a computer-readable storage medium, and the storage medium can be a read-only memory, a magnetic disk, an optical disk, etc.

[0162] In addition, it should be noted that the above drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, rather than for limiting purposes. It is easy to understand that the processes shown in the above drawings do not indicate or limit the time sequence of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously in, for example, multiple modules.

[0163] Through the description of the exemplary embodiments, those skilled in the art can easily understand that the branch prediction method according to the embodiments of the present application has at least one or more of the following advantages.

[0164] According to the exemplary embodiments, compared with using multiple groups of global branch history registers GBHR, the present application only uses the global branch history register GBHR and the branch feedback history register FBHR, greatly reducing the hardware area of the branch prediction unit, while improving the prediction speed and reducing the power consumption.

[0165] According to the exemplary embodiments, compared with the G-share algorithm that only uses one group of GBHSR, the present application uses a prediction algorithm that combines GBHR and FBHR, improving the accuracy of branch prediction.

[0166] According to an exemplary embodiment, the present application provides feedback through a branch prediction unit, which can adopt additional information on the execution status of branches according to different branch instructions, thereby improving the accuracy of branch prediction. At the same time, it can also accurately predict the jump situation of loop branch instructions, thus solving the problem that the prediction result of the loop end situation in the prior art always fails.

[0167] According to an exemplary embodiment, the implementation of the present application will not cause a reduction in prediction due to loop nesting.

[0168] Those skilled in the art can understand that the above-mentioned modules can be distributed in the device according to the description of the embodiment, or can be correspondingly changed and distributed in one or more devices that are different from this embodiment. The modules of the above embodiment can be combined into one module, or can be further split into multiple sub-modules.

[0169] The above specifically shows and describes the exemplary embodiments of the present application. It should be understood that the present application is not limited to the detailed structure, setting method or implementation method described here; on the contrary, the present application is intended to cover various modifications and equivalent settings included in the spirit and scope of the appended claims.

Claims

1. A method for branch prediction, used for the instruction execution of a processor, characterized in that, it includes: Obtaining the result of branch feedback; Generating a branch prediction feedback value according to the result of branch feedback and the value of the global branch history register; Judging that if the fetched instruction is a branch instruction, performing an exclusive OR operation on the instruction address and the branch prediction feedback value; Using the result of the exclusive OR operation as an index address to obtain a decision counter for predicting branch jumps from the pattern history table; Predicting whether the branch jumps according to the status value of the decision counter; wherein, the generating of the branch prediction feedback value includes: Concatenating the result of branch feedback with the high bits of the global branch history register to obtain the branch prediction feedback value; wherein, the obtaining of the result of branch feedback includes: Obtaining a branch feedback enable signal; According to the branch feedback enable signal, selecting the low bits of the global branch history register or the branch feedback history register as the result of branch feedback, and the branch feedback history register is used to record branch feedback information.

2. The method according to claim 1, characterized in that, it further includes: Selecting an operation method according to the relationship between the branch instruction register values, performing an operation on the branch instruction register values, and updating the branch feedback history register with the obtained operation result.

3. The method according to claim 2, characterized in that, it further includes: Comparing the operation result with a preset value, and updating the branch feedback enable signal according to the comparison result.

4. The method according to claim 2, characterized in that, selecting an operation method according to the relationship between the branch instruction register values further includes: If the fetched instruction is a loop branch instruction, subtracting the branch instruction register values and taking the absolute value to obtain an operation result.

5. The method according to claim 4, characterized in that, it further includes: Comparing the operation result with a preset value, and if the operation result is less than or equal to the preset value, setting the branch feedback history enable signal to 1.

6. The method according to claim 5, characterized in that, the preset value is greater than or equal to the loop step of the loop branch instruction.

7. The method according to claim 1, characterized in that, When the branch instruction execution ends, updating the global branch history register and the decision counter obtained by indexing according to the branch instruction jump result.

8. A branch prediction device, used for the instruction execution of a processor, characterized in that, it includes: A global branch history register, used to record the jump situations of all branch instructions; A branch feedback unit, used to obtain the result of branch feedback; A branch feedback value generation unit, used to generate a branch prediction feedback value according to the result of branch feedback and the value of the global branch history register; An exclusive OR calculation unit, judging that if the fetched instruction is a branch instruction, performing an exclusive OR operation on the instruction address and the branch prediction feedback value; A pattern history table indexing unit, using the result of the exclusive OR operation as an index address to obtain a decision counter for predicting branch jumps from the pattern history table; A prediction jump unit that predicts whether a branch jumps according to the status value of the decision counter; Among them, the branch feedback value generation unit is further configured to splice the result of the branch feedback with the high bits of the global branch history register to obtain the branch prediction feedback value; Among them, the branch feedback unit is further configured to obtain a branch feedback enable signal; according to the branch feedback enable signal, select the low bits of the global branch history register or the branch feedback history register as the result of the branch feedback.

9. The apparatus according to claim 8, characterized in that, The branch feedback unit includes a branch feedback detector, a branch feedback history register, an enable unit, and a multiplexer; The branch feedback detector performs operations according to the branch instruction register value, and updates the branch feedback history enable signal and the branch feedback history register according to the operation result; The branch feedback history register is used to record the operation result of the branch feedback detector; The enable unit is used to receive the branch feedback history enable signal and enable the multiplexer; The multiplexer is used to select the branch feedback history register or the global branch history register to generate the branch prediction feedback value.

10. The apparatus according to claim 9, characterized in that, It further includes a branch result recording unit and a pattern history table updating unit; The branch result recording unit is used to update the global branch history register according to the branch instruction jump result; The pattern history table updating unit is used to update the decision counter obtained by indexing according to the branch instruction jump result.

11. A processor, characterized in that, The processor includes the apparatus according to any one of claims 8-10.

Images