Design of a low-noise, high-bandwidth current sensor chip

Abstract

The present invention proposes a low-noise, high-bandwidth current sensing chip, which is characterized by comprising a low-noise Class AB operational amplifier A1 and a high-performance pseudo-resistor R composed of an inverting amplifier B and a current attenuator C. F . Its significant advantage is that the current sensing chip design proposed in the present invention can realize the equivalent of a large-resistance feedback resistor in a small area within the chip, providing a transimpedance gain of up to 1GΩ. At the same time, compared with off-chip resistors, it has the advantages of low noise, small area, good linearity and a wide adjustment range. It can achieve a signal bandwidth of 16kHz and an equivalent noise current effective amplitude of 0.7pA under the bandwidth, which is suitable for realizing high transimpedance gain, high bandwidth and low noise current detection within the chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal processing, and relates to a micro-current amplifier, in particular to a micro-current amplifier with high gain, high precision, low noise and adjustable input bias voltage. Background Art

[0002] Many sensors in analog circuits output current signals, which are often processed by converting them into voltage signals. Therefore, designing a transimpedance amplifier (TIA) to convert current into voltage is indispensable. The performance of TIAs, especially the implementation of high-performance front-end amplifiers within integrated circuits, is an ongoing process of exploration.

[0003] Conventional weak current detection systems typically use an op amp plus feedback resistor. This structure requires high-value, high-precision resistors, typically exceeding hundreds of megohms, which are typically not integrated on-chip. Furthermore, their parasitic capacitance limits the bandwidth of the detection signal. A 1GΩ resistor can have parasitic capacitance of up to 0.1pF. Furthermore, multi-stage amplification often introduces increased noise, hindering the acquisition of weak current signals.

[0004] Currently, the overall structure of commercial devices is relatively complex and has a limited scope of application. Therefore, we propose a low-noise, high-bandwidth current sensor chip that combines the advantages of a wide input range, high resolution, high bandwidth, low noise and highly integrated design within the chip. Summary of the Invention

[0005] In order to improve the practicality of a transimpedance amplifier and realize on-chip integration and multi-channel detection, the present invention proposes a low-noise and high-bandwidth current sensing chip design.

[0006] The technical solution adopted in the present invention is as follows:

[0007] A low-noise, high-bandwidth current sensor chip design, characterized by including low-noise Class AB operational amplifiers A1, A2, and A3, resistors R1, R2, and R3, NMOS transistors M0 and M2, PMOS transistors M1 and M3, and feedback capacitor C F , provides 3 signal ports, input current terminal I in , you can connect a larger input capacitor C S Current signal source, bias voltage terminal V CMD , used to adjust the bias voltage at the input and the output voltage V OResistors R1 and R2 and low-noise Class AB operational amplifier A2 form a first-stage inverting amplifier B, resistor R3, NMOS tubes M0 and M2, PMOS tubes M1 and M3 and low-noise Class AB operational amplifier A3 form a first-stage current attenuator C; the first-stage inverting amplifier B and the first-stage current attenuator C together form a high-performance pseudo resistor R F The low-noise Class AB operational amplifiers A1, A2 and A3 are composed of a first-stage folded cascode amplifier and a first-stage push-pull amplifier, with the inverting input terminal of A1 connected to the input current terminal I in , its non-inverting input terminal is connected to the bias voltage terminal V CMD , the output terminal is connected to the output voltage terminal V O The output terminal V of the first-stage inverting amplifier B X Connect the input end of the primary current attenuator C, and the output end of the primary current attenuator C is connected to the input current end I in The non-inverting input of the first-stage inverting amplifier B and the non-inverting input of the first-stage current attenuator C are both connected to the bias voltage V CMD .

[0008] Furthermore, the low-noise, high-bandwidth current sensor chip design is characterized by low-noise Class AB operational amplifiers A1, A2, and A3, as shown in the attached diagram. Figure 2As shown, it includes MOS transistors M0 to M22, capacitors C1 and C2; the sources of PMOS transistors M0, M9, M10, M15, M18, and M21 are connected to the power supply voltage VDD; the drain of PMOS transistor M0 is connected to the sources of M1 and M2; the source of PMOS transistor M7 is connected to the drain of M9; the source of PMOS transistor M8 is connected to the drain of M10; the gate and drain of PMOS transistor M18 are connected to the source of M19; the sources of NMOS transistors M5, M6, M17, M20, and M22 are connected to GND; the gate and drain of NMOS transistor M17 are connected to the source of M16; the drain of NMOS transistor M5 and the source of M3 are connected to the drain of PMOS transistor M1; the drain of NMOS transistor M6 and the source of M4 are connected to the drain of PMOS transistor M2; the drain of NMOS transistor M3 is connected to the drain of , the source of M11 is connected to the drain of PMOS tube M13; the drain of NMOS tube M4, the source of M12, the gate of M22 and the drain of PMOS tube M14 are connected to each other; the drain of NMOS tube M11 is connected to the drain of PMOS tube M7, the source of M13, and the gates of M9 and M10; the drain of NMOS tube M12 is connected to the source of PMOS tube 14, the drain of M8, and the gate of M21; the gate and drain of NMOS tube M16, the gates of M11 and M12 are connected to the drain of PMOS tube 15; the drain of NMOS tube 20 is connected to the gate and drain of PMOS tube M19, and the gates of M13 and M14; the two ends of C1 are connected to the gate and drain of PMOS tube M21 respectively; the two ends of C2 are connected to the gate and drain of NMOS tube M22 respectively; the gates of M0 and M15 are connected to the bias voltage V B1 , M5, M6, M20 gate connection bias voltage V B2 , M3, M4 gate connection bias voltage V B3 , M7, M8 gate connection bias voltage V B4 ; The gate of M2 serves as the inverting input terminal V of the low-noise Class AB operational amplifiers A1, A2, and A3 - , M1 gate serves as the non-inverting input terminal V of low noise Class AB operational amplifiers A1, A2 and A3 respectively + , the drains of M21 and M22 are connected to each other as the output terminal V O .

[0009] Furthermore, the low-noise and high-bandwidth current sensor chip design is as shown in the attached Figure 2As shown, it is characterized by a folded cascode amplifier composed of MOS transistors M0 to M10 of low-noise Class AB operational amplifiers A1, A2, and A3, which provides a wide input range and noise suppression capability; MOS transistors M11 to M14 generate an additional voltage difference, so that MOS transistors M21 and M22 work in Class AB; M15 to M20 generate a bias voltage for M11 to M14.

[0010] Furthermore, the low-noise and high-bandwidth current sensor chip design is as shown in the attached Figure 1 As shown, it is characterized by the fact that the resistance values ​​of R1 and R2 of the inverting amplifier B are equal, and the output voltage V X satisfy

[0011] V X =2V CMD -V O (1)

[0012] Furthermore, the low-noise, high-bandwidth current sensor chip design is characterized in that the source electrodes of the first-stage current attenuator C, the NMOS tubes M0, M2 and the PMOS tubes M1, M3 are connected together and connected to the output end of the low-noise class AB operational amplifier A3; the gate and drain electrodes of the NMOS tube M0 and the PMOS tube M1 are connected together and connected together with one end of the resistor R3 to the inverting input end of the low-noise class AB operational amplifier A3; the other end of the resistor R3 is connected to the output end V of the first-stage inverting amplifier B. X The gate and drain of NMOS tube M2 and PMOS tube M3 are connected together and connected to the inverting input terminal and input current terminal of low noise class AB operational amplifier A3. in connected.

[0013] Furthermore, in the current attenuator C, the width-to-length ratio of the NMOS transistors M0 and M2 is equal to the width-to-length ratio of the PMOS transistors M1 and M3.

[0014] Assume that the width-to-length ratio of NMOS tubes MO, M2 and PMOS tubes M1, M3 satisfies

[0015]

[0016] Due to the negative feedback of the low-noise Class AB operational amplifier A3, the drain voltage of the NMOS transistor MO and the drain voltage of the PMOS transistor M1 are clamped to V CMD Due to the negative feedback of the low-noise Class AB operational amplifier A1, the drain voltage of the NMOS tube M2 and the drain voltage of the PMOS tube M3 are also clamped to V CMDSince the source terminals of NMOS transistors M0 and M2 and PMOS transistors M1 and M3 are connected together and have the same voltage, the ratio of the total current of NMOS transistors M0 and M1 to the total current of NMOS transistors M2 and M3 is equal to K. The current passing through R3 is precisely reduced in the reverse direction to 1 / K times. Therefore, the input current I in satisfy

[0017]

[0018] In summary, the low-noise and high-bandwidth current sensor chip design has an input current I in and the output voltage V O satisfy

[0019]

[0020] That is, high-performance pseudo-resistance R F The resistance is K×R3.

[0021] Due to the negative feedback of the low-noise Class AB operational amplifier A1, the voltage at the input current terminal Iin is fixed at V CMD , so the present invention can achieve a transimpedance gain A R for

[0022] A R =R F =K×R3 (5)

[0023] The DC output characteristics of the low-noise, high-bandwidth current sensor chip are:

[0024] V O =V CMD -I in ×A R (6)

[0025] Capacitor C F It is connected in parallel between the output and inverting input of the low-noise Class AB operational amplifier A1 to provide compensation, improve circuit stability, and also limit the bandwidth of the system.

[0026] The maximum transimpedance gain bandwidth of the present invention is

[0027]

[0028] High performance pseudo resistor R F Compared with the fixed resistance feedback resistor, it also has its own advantages in terms of noise. F The middle MOS transistors M0 to M3 are in the subthreshold region and have extremely low transconductance, so they can generate smaller input noise current.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] 1. The present invention realizes high-performance pseudo-resistance R in the chip through current scaling F , saving a lot of layout area and suitable for integration in integrated circuits.

[0031] 2. The design of the present invention has a wide input current and voltage output range.

[0032] 3. The present invention has extremely low input noise current and can achieve a higher signal-to-noise ratio compared to off-chip resistors.

[0033] 4. The present invention realizes high-performance pseudo-resistance R in the chip F , with smaller parasitic capacitance, can achieve higher signal bandwidth compared to off-chip resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the present invention.

[0035] Figure 2 Schematic diagram of the operational amplifiers A1 to A3.

[0036] Figure 3 is the DC relationship between input and output in a specific implementation.

[0037] Figure 4 1 is a Bode diagram of transimpedance gain bandwidth in a specific implementation manner.

[0038] Figure 5 is the power spectrum of the equivalent input current noise in a specific embodiment

[0039] Figure 6 The transient response of 50pA / 100pA input current in a specific embodiment is shown in FIG. DETAILED DESCRIPTION

[0040] In order to better illustrate the performance and advantages of the present invention, the following embodiments are proposed, which, combined with the accompanying drawings, are more conducive to explaining the advantages of the present invention.

[0041] The technical solution adopted in the present invention is as follows:

[0042] A low-noise, high-bandwidth current sensor chip design, characterized by including low-noise Class AB operational amplifiers A1, A2, and A3, resistors R1, R2, and R3, NMOS transistors M0 and M2, PMOS transistors M1 and M3, and feedback capacitor C F , provides 3 signal ports, input current terminal I in , you can connect a larger input capacitor C S Current signal source, bias voltage terminal VCMD , used to adjust the bias voltage at the input and the output voltage V O Resistors R1 and R2 and low-noise Class AB operational amplifier A2 form a first-stage inverting amplifier B, resistor R3, NMOS tubes M0 and M2, PMOS tubes M1 and M3 and low-noise Class AB operational amplifier A3 form a first-stage current attenuator C; the first-stage inverting amplifier B and the first-stage current attenuator C together form a high-performance pseudo resistor R F The low-noise Class AB operational amplifiers A1, A2 and A3 are composed of a first-stage folded cascode amplifier and a first-stage push-pull amplifier, with the inverting input terminal of A1 connected to the input current terminal I in , its non-inverting input terminal is connected to the bias voltage terminal V CMD , the output terminal is connected to the output voltage terminal V O The output terminal V of the first-stage inverting amplifier B X Connect the input end of the primary current attenuator C, and the output end of the primary current attenuator C is connected to the input current end I in The non-inverting input of the first-stage inverting amplifier B and the non-inverting input of the first-stage current attenuator C are both connected to the bias voltage V CMD .

[0043] Furthermore, the low-noise, high-bandwidth current sensor chip design is characterized by low-noise Class AB operational amplifiers A1, A2, and A3, as shown in the attached diagram. Figure 2As shown, it includes MOS transistors M0 to M22, capacitors C1 and C2; the sources of PMOS transistors M0, M9, M10, M15, M18, and M21 are connected to the power supply voltage VDD; the drain of PMOS transistor M0 is connected to the sources of M1 and M2; the source of PMOS transistor M7 is connected to the drain of M9; the source of PMOS transistor M8 is connected to the drain of M10; the gate and drain of PMOS transistor M18 are connected to the source of M19; the sources of NMOS transistors M5, M6, M17, M20, and M22 are connected to GND; the gate and drain of NMOS transistor M17 are connected to the source of M16; the drain of NMOS transistor M5 and the source of M3 are connected to the drain of PMOS transistor M1; the drain of NMOS transistor M6 and the source of M4 are connected to the drain of PMOS transistor M2; the drain of NMOS transistor M3 is connected to the drain of , the source of M11 is connected to the drain of PMOS tube M13; the drain of NMOS tube M4, the source of M12, the gate of M22 and the drain of PMOS tube M14 are connected to each other; the drain of NMOS tube M11 is connected to the drain of PMOS tube M7, the source of M13, and the gates of M9 and M10; the drain of NMOS tube M12 is connected to the source of PMOS tube 14, the drain of M8, and the gate of M21; the gate and drain of NMOS tube M16, the gates of M11 and M12 are connected to the drain of PMOS tube 15; the drain of NMOS tube 20 is connected to the gate and drain of PMOS tube M19, and the gates of M13 and M14; the two ends of C1 are connected to the gate and drain of PMOS tube M21 respectively; the two ends of C2 are connected to the gate and drain of NMOS tube M22 respectively; the gates of M0 and M15 are connected to the bias voltage V B1 , M5, M6, M20 gate connection bias voltage V B2 , M3, M4 gate connection bias voltage V B3 , M7, M8 gate connection bias voltage V B4 ; The gate of M2 serves as the inverting input terminal V of the low-noise Class AB operational amplifiers A1, A2, and A3 - , M1 gate serves as the non-inverting input terminal V of low noise Class AB operational amplifiers A1, A2 and A3 respectively + , the drains of M21 and M22 are connected to each other as the output terminal V O .

[0044] Furthermore, the low-noise and high-bandwidth current sensor chip design is as shown in the attached Figure 2As shown, it is characterized by a folded cascode amplifier composed of MOS transistors M0 to M10 of low-noise Class AB operational amplifiers A1, A2, and A3, which provides a wide input range and noise suppression capability; MOS transistors M11 to M14 generate an additional voltage difference, so that MOS transistors M21 and M22 work in Class AB; M15 to M20 generate a bias voltage for M11 to M14.

[0045] Furthermore, the low-noise and high-bandwidth current sensor chip design is as shown in the attached Figure 1 As shown, it is characterized by the fact that the resistance values ​​of R1 and R2 of the inverting amplifier B are equal, and the output voltage V X satisfy

[0046] V X =2V CMD -V O (1)

[0047] Furthermore, the low-noise, high-bandwidth current sensor chip design is characterized in that the source electrodes of the first-stage current attenuator C, the NMOS tubes M0, M2 and the PMOS tubes M1, M3 are connected together and connected to the output end of the low-noise class AB operational amplifier A3; the gate and drain electrodes of the NMOS tube M0 and the PMOS tube M1 are connected together and connected together with one end of the resistor R3 to the inverting input end of the low-noise class AB operational amplifier A3; the other end of the resistor R3 is connected to the output end V of the first-stage inverting amplifier B. X The gate and drain of NMOS tube M2 and PMOS tube M3 are connected together and connected to the inverting input terminal and input current terminal of low noise class AB operational amplifier A3. in connected.

[0048] Furthermore, in the current attenuator C, the width-to-length ratio of the NMOS transistors M0 and M2 is equal to the width-to-length ratio of the PMOS transistors M1 and M3.

[0049] Assume that the width-to-length ratio of NMOS tubes MO, M2 and PMOS tubes M1, M3 satisfies

[0050]

[0051] Due to the negative feedback of the low-noise Class AB operational amplifier A3, the drain voltage of the NMOS transistor MO and the drain voltage of the PMOS transistor M1 are clamped to V CMD Due to the negative feedback of the low-noise Class AB operational amplifier A1, the drain voltage of the NMOS tube M2 and the drain voltage of the PMOS tube M3 are also clamped to V CMDSince the source terminals of NMOS transistors M0 and M2 and PMOS transistors M1 and M3 are connected together and have the same voltage, the ratio of the total current of NMOS transistors M0 and M1 to the total current of NMOS transistors M2 and M3 is equal to K. The current passing through R3 is precisely reduced in the reverse direction to 1 / K times. Therefore, the input current I in satisfy

[0052]

[0053] In summary, the low-noise and high-bandwidth current sensor chip design has an input current I in and the output voltage V O satisfy

[0054]

[0055] That is, high-performance pseudo-resistance R F The resistance is K×R3.

[0056] Due to the negative feedback of the low-noise Class AB operational amplifier A1, the voltage at the input current terminal Iin is fixed at V CMD , so the present invention can achieve a transimpedance gain A R for

[0057] A R =R F =K×R3 (5)

[0058] The DC output characteristics of the low-noise, high-bandwidth current sensor chip are:

[0059] V O =V CMD -I in ×A R (6)

[0060] Capacitor C F It is connected in parallel between the output and inverting input of the low-noise Class AB operational amplifier A1 to provide compensation, improve circuit stability, and also limit the bandwidth of the system.

[0061] The maximum transimpedance gain bandwidth of the present invention is

[0062]

[0063] High performance pseudo resistor R F Compared with the fixed resistance feedback resistor, it also has its own advantages in terms of noise. F The middle MOS transistors M0 to M3 are in the subthreshold region and have extremely low transconductance, so they can generate smaller input noise current.

[0064] This case study is based on the SMIC 55nm process. The following are the relevant parameters for this patent. The gate width W, gate length L, and capacitance values ​​for each MOS transistor A1-A3 are as follows:

[0065]

[0066]

[0067]

[0068]

[0069]

[0070]

[0071]

[0072]

[0073]

[0074]

[0075]

[0076]

[0077] The capacitance values ​​of capacitors C1 and C2 satisfy

[0078] C1=C2=720fF

[0079] Constitute a high-performance pseudo resistor R F In the structure, the parameters of R1~R3 ​​and M0 to M0~M3 are as follows:

[0080] R1=R2=500kΩ

[0081] R3=2MΩ

[0082]

[0083]

[0084]

[0085] The overall compensation capacitor C F The parameters are as follows:

[0086] C F =10fF

[0087] In Example VCMD The voltage is set to 100mV.

[0088] Based on the above parameters, this embodiment theoretically has the following performance.

[0089] Feedback resistor R F The parameters are as follows:

[0090] A R =K×R3=500×2MΩ=1GΩ

[0091] When the signal input is DC current, the DC response is as shown in the following figure. Figure 3 As shown, satisfied

[0092] V O =100mV-1GΩ×Iin

[0093] When the input current changes from -500pA to 500pA, the output voltage changes from 600mV to -400mV, which meets the preset DC characteristics.

[0094] In summary, the low-frequency gain in this embodiment satisfies

[0095] 20log 10 A R =180dBΩ

[0096] Bandwidth Satisfaction

[0097]

[0098] The amplitude-frequency response of the gain is shown in the attached Figure 4 As shown, the theory and Figure 4 The results are consistent with those shown, indicating that controllable high gain is achieved on the chip.

[0099] The output noise power spectrum of the circuit in this embodiment is shown in the attached figure. Figure 5 , the effective noise amplitude within 16kHz is V n，rms =0.7mV, the equivalent input noise current is 0.7pA, which shows that the present invention has excellent low noise characteristics.

[0100] The transient response when the input current is switched between 50pA and 100pA is shown in the attached figure. Figure 6 , the clock period is 1ms, where the pulse width of 50pA is 200μs, and the amplitude switches well between 100mV and 50mV without obvious overshoot.

Claims

1. A low-noise, high-bandwidth current sensor chip, characterized in that: It includes low-noise Class AB operational amplifiers A1, A2, and A3, resistors R1, R2, and R3, NMOS tubes M0 and M2, PMOS tubes M1 and M3, and feedback capacitor C F , provides 3 signal ports, input current terminal I in , connect the input capacitor C s Current signal source, bias voltage terminal V CMD , used to adjust the bias voltage at the input and the output voltage V O Resistors R1 and R2 and low-noise Class AB operational amplifier A2 form a first-stage inverting amplifier B, resistor R3, NMOS tubes M0 and M2, PMOS tubes M1 and M3 and low-noise Class AB operational amplifier A3 form a first-stage current attenuator C; the first-stage inverting amplifier B and the first-stage current attenuator C together form a high-performance pseudo resistor R F The low-noise Class AB operational amplifiers A1, A2 and A3 are composed of a first-stage folded cascode amplifier and a first-stage push-pull amplifier, with the inverting input terminal of A1 connected to the input current terminal I in , its non-inverting input terminal is connected to the bias voltage terminal V CMD , the output terminal is connected to the output voltage terminal V O The output terminal V of the first-stage inverting amplifier B X Connect the input end of the primary current attenuator C, and the output end of the primary current attenuator C is connected to the input current end I in The non-inverting input of the first-stage inverting amplifier B and the non-inverting input of the first-stage current attenuator C are both connected to the bias voltage V CMD .

2. The low-noise, high-bandwidth current sensor chip according to claim 1, characterized in that: Low-noise Class AB operational amplifiers A1, A2, and A3 include MOS transistors M0 to M22 and capacitors C1 and C2. The sources of PMOS transistors M0, M9, M10, M15, M18, and M21 are connected to the power supply voltage VDD. The drain of PMOS transistor M0 is connected to the sources of M1 and M2. The source of PMOS transistor M7 is connected to the drain of M9. The source of PMOS transistor M8 is connected to the drain of M10. The gate and drain of PMOS transistor M18 are connected to the source of M19. The sources of NMOS transistors M5, M6, M17, M20, and M22 are connected to GND. The gate and drain of NMOS transistor M17 are connected to the source of M16. The drain of NMOS transistor M5 and the source of M3 are connected to the drain of PMOS transistor M1. The drain of NMOS transistor M6 and the source of M4 are connected to the drain of PMOS transistor M2. The drain of OS transistor M3 and the source of M11 are connected to the drain of PMOS transistor M13; the drain of NMOS transistor M4, the source of M12, and the gate of M22 are connected to the drain of PMOS transistor M14; the drain of NMOS transistor M11 is connected to the drain of PMOS transistor M7, the source of M13, and the gates of M9 and M10; the drain of NMOS transistor M12 is connected to the source of PMOS transistor 14, the drain of M8, and the gate of M21; the gate and drain of NMOS transistor M16, the gates of M11 and M12 are connected to the drain of PMOS transistor 15; the drain of NMOS transistor 20 is connected to the gate and drain of PMOS transistor M19, and the gates of M13 and M14; the two ends of C1 are connected to the gate and drain of PMOS transistor M21 respectively; the two ends of C2 are connected to the gate and drain of NMOS transistor M22 respectively; the gates of M0 and M15 are connected to the bias voltage V B1 , M5, M6, M20 gate connection bias voltage V B2 , M3, M4 gate connection bias voltage V B3 , M7, M8 gate connection bias voltage V B4 The gate of M2 serves as the non-inverting input terminal V of the low-noise Class AB operational amplifiers A1, A2, and A3. + The gate of M1 serves as the inverting input terminal V of the low-noise Class AB operational amplifiers A1, A2, and A3 respectively. The drains of M21 and M22 are connected to each other as the output terminal V O .

3. The low-noise, high-bandwidth current sensor chip according to claim 2, characterized in that: The folded cascode amplifier formed by MOS transistors M0-M10 of low-noise Class AB operational amplifiers A1, A2, and A3 provides a wide input range and noise suppression capabilities. MOS transistors M11-M14 generate an additional voltage difference, which enables MOS transistors M21 and M22 to operate in Class AB mode. M15-M20 generate bias voltage for M11-M14.

4. The low-noise, high-bandwidth current sensor chip according to claim 1, characterized in that: The resistors R1 and R2 of the inverting amplifier B have equal resistance values.

5. The low-noise, high-bandwidth current sensor chip according to claim 1, characterized in that: The first-stage current attenuator C has the source electrodes of the NMOS tubes M0 and M2 connected together with the source electrodes of the PMOS tubes M1 and M3, and connected to the output terminal of the low-noise Class AB operational amplifier A3; the gate and drain of the NMOS tube M0 are connected together with the gate and drain of the PMOS tube M1, and connected together with one end of the resistor R3 to the inverting input terminal of the low-noise Class AB operational amplifier A3; the other end of the resistor R3 is connected to the output terminal V of the first-stage inverting amplifier B. X The gate and drain of the NMOS tube M2 are connected to the gate and drain of the PMOS tube M3, and are connected to the inverting input terminal and input current terminal of the low-noise class AB operational amplifier A3. in connected.

6. A low-noise, high-bandwidth current sensor chip according to claim 1 or 5, characterized in that: In the first-stage current attenuator C, the width-to-length ratio of the NMOS tubes M0 and M2 is equal to the width-to-length ratio of the PMOS tubes M1 and M3.

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