Delay Estimation Method, Device, Electronic Device and Storage Medium for Programmable Devices

Abstract

The present invention discloses a method, device, electronic device and storage medium for delay estimation of a programmable device, belonging to the field of integrated circuit design. It includes entering a plurality of routed units that have completed routing into a planar coordinate system; obtaining a relative coordinate vector between any two routed units; dividing all the routed units into a plurality of routing modules, where a routing module includes at least one routing group formed by two routed units; obtaining the actual delay and estimated delay between the two routed units in each routing group, and calculating a delay correction coefficient for each said routing group; obtaining an average delay coefficient for each said routing module; and obtaining a corrected delay for the two routed units in each routing group according to the obtained estimated delay, relative coordinate vector and the average delay coefficient of the routing module. The present invention can more accurately estimate the delay between two routed units that are far apart in a very large-scale programmable device.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and relates to the design technology of integrated circuit software tools for field programmable logic devices (hereinafter referred to as programmable devices), and particularly relates to a method, device, electronic device and storage medium for estimating the delay of programmable devices. Background Art

[0002] As Figure 2 As shown in the schematic diagram of the delay cost model of the routing algorithm for programmable devices based on the A* algorithm, in the existing routing expansion algorithm process of programmable devices based on the A* algorithm, the delay cost model of f = g + h is often used to estimate the cost value from the current expansion node to the target node. g represents the delay cost value that has been traveled from the source node to the current expansion node, plus the congestion factor value; h represents the estimated delay cost value from the current expansion node to the target node.

[0003] In the above-mentioned routing expansion based on the A* algorithm, the accuracy of the h-value estimation will greatly affect the performance of the routing algorithm. The more accurate the h-value estimation is, the better the routing expansion directivity is, the fewer intermediate nodes are expanded, and the better the algorithm performance is.

[0004] The prior art usually uses the distance estimation method or the lookup delay table estimation method to obtain the h-value. The inventor finds that when estimating the delay of two relatively distant routing units (Switch Box) in a very large-scale programmable device in the above-mentioned prior art solutions, the estimation accuracy of the above h-value is relatively low, and the actual delay and the estimated delay of the two relatively distant routing units differ greatly, thus having a greater impact on the performance and efficiency of the routing algorithm. Therefore, it is necessary to make improvements. Summary of the Invention

[0005] The embodiments of the present invention provide a method, device, electronic device and storage medium for estimating the delay of programmable devices, with relatively high estimation accuracy of the h-value, which can more accurately estimate the delay of two relatively distant routing units in a very large-scale programmable device, thereby improving the performance of the routing expansion algorithm.

[0006] The technical solution of the present invention is as follows: Provide a method for estimating the delay of a programmable device, including: Entering multiple routed units that have been routed into a planar coordinate system; Obtaining the relative coordinate vector between any two routed units according to the coordinates of the routed units in the planar coordinate system; Dividing all the routed units into multiple routing modules according to the relative coordinate vector, where the routing module includes at least one routing group formed by two routed units, and the relative coordinate vectors corresponding to each routing group in each routing module are equal; Obtaining the actual delay and the estimated delay between two routed units in each routing group, and calculating the delay correction coefficient of each routing group according to the actual delay and the estimated delay; Obtaining the average delay coefficient of each routing module according to the delay correction coefficients in each routing module; Obtaining the corrected delay of two routed units in each routing group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the routing module.

[0007] Preferably, the obtaining the actual delay and the estimated delay between two routed units in each routing group, and calculating the delay correction coefficient of each routing group according to the actual delay and the estimated delay includes: Obtaining the actual delay between two routed units in each routing group according to the actual working conditions; Looking up a preset delay estimation table to obtain the estimated delay between two routed units in each routing group, where the delay estimation table is used to record the estimated delay between two routed units in the routing group; Dividing the actual delay of each routing group by the estimated delay corresponding to each routing group to obtain the delay correction coefficient of each routing group.

[0008] Preferably, the obtaining the average delay coefficient of each routing module according to the delay correction coefficients in each routing module includes: Respectively obtaining the average value of the delay correction coefficients corresponding to each routing group in each routing module to obtain the average delay coefficient of each routing module.

[0009] Preferably, the obtaining the relative coordinate vector between any two routed units according to the coordinates of the routed units in the planar coordinate system includes: Obtaining the horizontal coordinate and the vertical coordinate of each routed unit; Determining the starting routed unit and the target routed unit among the any two routed units; Subtracting the horizontal coordinate of the starting routed unit from the horizontal coordinate of the target routed unit to obtain the horizontal coordinate difference of the relative coordinate vector, and subtracting the vertical coordinate of the starting routed unit from the vertical coordinate of the target routed unit to obtain the vertical coordinate difference of the relative coordinate vector; Pointing from the starting routed unit to the target routed unit, and obtaining the relative coordinate vector between the two routed units according to the horizontal coordinate difference and the vertical coordinate difference of the relative coordinate vector.

[0010] Preferably, obtaining the corrected delay of two routing units in each routing group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the routing module includes: obtaining the relative coordinate vector of any two routing units; determining the routing group formed by the any two routing units according to the relative coordinate vector; determining the routing module where the any two routing units are located according to the routing group; obtaining the average delay coefficient of the any two routing units according to the routing module; querying the preset delay estimation table to obtain the estimated delay of the any two routing units; multiplying the average delay coefficient of the any two routing units by their respective corresponding estimated delays to obtain the corrected delay of the any two routing units.

[0011] Preferably, after obtaining the corrected delay of any two routing units, it further includes: constructing a delay correction table according to the corrected delay of the any two routing units and the relative coordinate vector between the any two routing units.

[0012] Preferably, after obtaining the average delay coefficient of each routing module and before obtaining the corrected delay of any two routing units according to the preset delay estimation table, the relative coordinate vector, and the average delay coefficient of the routing module, it further includes: establishing a delay correction coefficient matrix according to the relative coordinate vector, the average delay coefficient of each routing module, and the corrected delay of any two routing units; wherein, the first column of the first delay correction coefficient matrix is the horizontal coordinate difference of the relative coordinate vector corresponding to the routing module, the second column is the vertical coordinate difference of the relative coordinate vector corresponding to the routing module, the third column is the average delay coefficient corresponding to the routing module, and the fourth column is the corrected delay corresponding to the routing module.

[0013] Another technical solution of the present invention is as follows: Provide a delay estimation device for a programmable device, including: a wiring input module for inputting a plurality of wired units that have completed wiring into a plane coordinate system; a vector generation module for obtaining a relative coordinate vector between any two wired units according to the coordinates of the wired units in the plane coordinate system; a wiring division module for dividing all the wired units into a plurality of wiring modules according to the relative coordinate vector, where the wiring module includes at least one wiring group formed by two wired units, and the relative coordinate vectors corresponding to the wiring groups in each wiring module are equal; a correction coefficient generation module for obtaining the actual delay and the estimated delay between two wired units in each wiring group, and calculating the delay correction coefficient of each wiring group according to the actual delay and the estimated delay; an average delay calculation module for obtaining the average delay coefficient of each wiring module according to the delay correction coefficients in the wiring module; a corrected delay generation module for obtaining the corrected delay between two wired units in each wiring group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the wiring module.

[0014] Another technical solution of the present invention is as follows: Provide an electronic device, including a processor and a memory coupled to the processor, where the memory stores program instructions executable by the processor; when the processor executes the program instructions stored in the memory, the steps of the above-mentioned delay estimation method for a programmable device are implemented.

[0015] Another technical solution of the present invention is as follows: Provide a storage medium, where program instructions are stored in the storage medium, and when the program instructions are executed by a processor, the steps of the above-mentioned delay estimation method for a programmable device can be implemented.

[0016] Compared with the prior art, the beneficial effects of the present application are as follows:

[0017] 1. The present application can make up for the deficiencies of the existing wiring delay estimation method, effectively improve the accuracy of delay estimation, thereby improving the wiring expansion guidance during integrated circuit design, further improving the performance of the wiring expansion algorithm, and improving the efficiency of the wiring algorithm. When the inventor uses the method described in the present application for delay estimation (i.e., determining the h value) and uses the corrected delay obtained from the present application to run the subsequent wiring process during integrated circuit design, the efficiency of the wiring algorithm is significantly improved, saving about 5% of the wiring time (the wiring time of a single thread can be reduced by about 200 seconds).

[0018] 2. This application utilizes statistical thinking, calculates based on a large amount of experimental data, and further proposes a new delay estimation method on the basis of the existing lookup delay table estimation algorithm. By dividing several wiring groups (i.e., multiple pairs of wiring units) with the same relative coordinate vector into the same wiring module, it calculates the average delay coefficient of all wiring groups in the same wiring module, and then calculates the corrected delay of all wiring groups. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 is a schematic flowchart of the delay estimation method for the programmable device in an embodiment of the present invention;

[0021] Figure 2 is a schematic diagram of the delay cost model of the programmable device routing algorithm based on the A* algorithm;

[0022] Figure 3 is a schematic structural diagram of the delay estimation device for the programmable device in the second embodiment of the present invention;

[0023] Figure 4 is a schematic structural diagram of the electronic device in the third embodiment of the present invention;

[0024] Figure 5 is a schematic structural diagram of the storage medium in the fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0026] The terms "first", "second", and "third" in the present invention are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0027] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0028] When existing delay estimation methods (such as distance estimation method and lookup delay table estimation method) are used to estimate the delay of a long-distance node (that is, the distance between two routing units is relatively long), the accuracy of the delay estimation of the h value is relatively low, which will lead to the loss of guidance for the routing expansion of the long-distance node, thus seriously affecting the performance of the routing algorithm and further reducing the routing expansion efficiency.

[0029] Figure 1 It is a schematic flowchart of the delay estimation method of the programmable device according to the first embodiment of the present invention. It should be noted that if there are substantially the same results, the method of the present invention is not limited to Figure 1 the shown flow sequence. As Figure 1 shown, the delay estimation method of the programmable device includes the steps:

[0030] S1: Enter a plurality of routed routing units into the plane coordinate system;

[0031] In this step, multiple wiring units that have completed the wiring process will automatically form an array layout as a whole. Therefore, when the present application enters the above-mentioned multiple wiring units into a plane coordinate system, each wiring unit can automatically obtain its own coordinate values (including horizontal coordinates and vertical coordinates). During actual work, people can set the coordinate difference between two adjacent wiring units according to their own needs, such as setting the coordinate difference between two wiring units to 1.

[0032] S2: Obtain the relative coordinate vector between any two wiring units according to the coordinates of the wiring units in the plane coordinate system;

[0033] In this step, the method for obtaining the relative coordinate vector between any two wiring units includes:

[0034] S21: Obtain the horizontal coordinate and vertical coordinate of each wiring unit;

[0035] S22: Determine the starting wiring unit and the target wiring unit among the any two wiring units;

[0036] S23: Subtract the horizontal coordinate of the starting wiring unit from the horizontal coordinate of the target wiring unit to obtain the horizontal coordinate difference of the relative coordinate vector, and subtract the vertical coordinate of the starting wiring unit from the vertical coordinate of the target wiring unit to obtain the vertical coordinate difference of the relative coordinate vector;

[0037] S24: Pointing from the starting wiring unit to the target wiring unit, obtain the relative coordinate vector between the two wiring units according to the horizontal coordinate difference and the vertical coordinate difference of the relative coordinate vector.

[0038] During the actual working process, the inventor found that there are relatively small differences in the layout of the input interfaces and the output interfaces on different wiring units among any two wiring units. Even on some wiring units, there are relatively small differences in the layout of their own input interfaces and their own output interfaces (such as the actual wiring methods of the input interfaces and the output interfaces are different). Therefore, the inventor found that there are often some relatively small differences in the delay from wiring unit A to wiring unit B and the delay from wiring unit B to wiring unit A (including actual delay and estimated delay). Therefore, the inventor believes that it is necessary to determine the starting wiring unit among the two wiring units to distinguish the above two different delays.

[0039] During actual operation, for multiple routed units that have completed routing, record the position coordinates of the routed unit (Switch Box) corresponding to the driver (starting node) in two routed units on a programmable device (such as an FPGA chip) as (drv_x, drv_y), and the position coordinates of the routed unit (Switch Box) corresponding to the load (target node) in the two routed units as (load_x, load_y). Denote the relative coordinate vector as (dist_x, dist_y), then: dist_x = load_x - drv_x, dist_y = load_y - drv_y.

[0040] S3: Divide all routed units into multiple routing modules according to the relative coordinate vector. Each routing module includes at least one routing group formed by two routed units, and the relative coordinate vectors corresponding to each routing group in each routing module are equal;

[0041] In this application, in order to better distinguish and address the situation where there are often some relatively small differences between the delay from routed unit A to routed unit B and the delay from routed unit B to routed unit A, based on the fact that vectors in different directions in mathematics are not the same vector, the inventors of this application divide the above two routed units into two routing groups according to the different starting routed units (for example, the routing from routed unit A to routed unit B is divided into the first routing group, and the routing from routed unit B to routed unit A is divided into the second routing group), and distinguish the above two routing groups by using the relative coordinate vector (the directions of the relative coordinate vectors of the two routing groups are different), so as to divide the above two routing groups into different routing modules respectively, and then obtain different delay correction coefficients and average delay coefficients.

[0042] S4: Obtain the actual delay and estimated delay between the two routed units in each routing group, and calculate the delay correction coefficient of each routing group according to the actual delay and the estimated delay;

[0043] During actual operation, due to different starting routed units, two relative coordinate vectors can be determined between any two routed units in this application, thus determining two routing groups. The delay correction coefficients (including actual delay and estimated delay) between the two routed units in each routing group are different.

[0044] In this step, the steps of calculating the delay correction coefficient of each routing group include:

[0045] S41: Obtain the actual delay between the two routed units in each routing group according to the actual working conditions;

[0046] S42: Search for a preset delay estimation table to obtain the estimated delay between two routing units in each routing group, where the delay estimation table is used to record the estimated delay between two routing units in the routing group;

[0047] S43: Divide the actual delay of each routing group by the corresponding estimated delay of each routing group to obtain the delay correction coefficient of each routing group.

[0048] During actual operation, the steps for this application to obtain the delay correction coefficient in combination with actual operation are as follows: This application runs the FPGA EDA tool software to execute the design use case. For multiple routed units that have been routed, obtain the actual delay from the driver (starting routed unit) to the load (target routed unit) in each routing group, denoted as sn_delay. At the same time, obtain the corresponding estimated delay by looking up the delay table, denoted as table_delay. Denote the delay correction coefficient as delay_coef, then: delay_coef = sn_delay / table_delay.

[0049] S5: Obtain the average delay coefficient of each routing module according to the delay correction coefficients in each routing module;

[0050] In this step, the steps to obtain the average delay coefficient of each routing module include: separately obtain the average value of the delay correction coefficients corresponding to each routing group in each routing module to obtain the average delay coefficient of each routing module.

[0051] During actual operation, for multiple routed units that meet the conditions in the previous text and have been routed in the design use case, sum and average the delay correction coefficients delay_coef of each routing group according to different relative coordinate vectors (dist_x, dist_y), and then the average delay coefficient of each routing module of the entire chip is obtained.

[0052] During actual operation, in order to make each data parameter (including the horizontal coordinate difference, vertical coordinate difference, and average delay coefficient) in this application more intuitive for the computer to search, this application can also construct a delay correction coefficient matrix. The specific method is as follows: establish a delay correction coefficient matrix according to the relative coordinate vector, the average delay coefficient of each routing module, and the corrected delay between any two routed units; where the first column of the first delay correction coefficient matrix is the horizontal coordinate difference of the relative coordinate vector corresponding to the routing module, the second column is the vertical coordinate difference of the relative coordinate vector corresponding to the routing module, the third column is the average delay coefficient corresponding to the routing module, and the fourth column is the corrected delay corresponding to the routing module.

[0053] During actual operation, for all the routed resources with completed wiring, the present application records the coordinate offset vector of the starting routing unit (driver) and the target routing unit (load) as (δx, δy), the number of driver / load combinations (i.e., the number of routing groups in each routing module) as T, and the delay correction coefficient calculated for the t-th driver / load combination as (delay_coef[δx][δy])t, where t = 0, 1,..., T - 1. Then, the delay correction coefficient for the coordinate offset vector (δx, δy) of the driver and load on the chip at this time is:

[0054]

[0055] After counting all the routed resources with completed wiring in the design cases, record the value range of δx as {δx0, δx1,..., δxm}, the value range of δy as {δy0, δy1,..., δyn}, where m and n are integers, and record the delay correction coefficient matrix of the entire chip as delay_coef_array. Then, there is:

[0056]

[0057] S6: Obtain the corrected delay of the two routing units in each routing group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the routing module.

[0058] During actual operation, when using the corrected delay obtained by the present application for delay estimation,

[0059] In this step, the steps of obtaining the corrected delay of the two routing units in each routing group include:

[0060] S61: Obtain the relative coordinate vector of any two routing units;

[0061] S62: Determine the routing group formed by the any two routing units according to the relative coordinate vector;

[0062] S63: Determine the routing module where the any two routing units are located according to the routing group;

[0063] S64: Obtain the average delay coefficient of the any two routing units according to the routing module;

[0064] S65: Query the preset delay estimation table to obtain the estimated delay of the any two routing units;

[0065] S66: Multiply the average delay coefficient of the any two routing units by their respective corresponding estimated delays to obtain the corrected delay of the any two routing units.

[0066] During actual operation, even if the delay difference between different wiring groups in the same two wiring groups is very small, when it is necessary to estimate the delay of a very large-scale programmable device, due to the large number of wiring units in the very large-scale programmable device, compared with the prior art, when the method described in this application is used for delay estimation, the accuracy of the delay estimation result of this application will be greatly improved, and the wiring duration can be significantly reduced (reduced by about 5%).

[0067] In this application, after obtaining the corrected delays of any two wiring units, it further includes: constructing a delay correction table based on the corrected delays of the any two wiring units and the relative coordinate vector between the any two wiring units; replacing the delay estimation table with the delay correction table. During actual operation, the above delay correction table can enable the wiring units of the programmable device to more conveniently and quickly determine the delay between any two wiring units, thereby further accelerating the wiring algorithm process.

[0068] Figure 3 It is a schematic structural diagram of a delay estimation device for a programmable device according to the second embodiment of the present invention. As Figure 3 shown, the delay estimation device of the programmable device includes:

[0069] A wiring entry module 21, configured to enter multiple wiring units that have completed wiring into a plane coordinate system;

[0070] A vector generation module 22, configured to obtain a relative coordinate vector between any two wiring units according to the coordinates of the wiring units in the plane coordinate system;

[0071] A wiring division module 23, configured to divide all wiring units into multiple wiring modules according to the relative coordinate vector, where the wiring module includes at least one wiring group formed by two wiring units, and the relative coordinate vectors corresponding to the wiring groups in each wiring module are equal;

[0072] A correction coefficient generation module 24, configured to obtain the actual delay and the estimated delay between two wiring units in each wiring group, and calculate a delay correction coefficient for each wiring group according to the actual delay and the estimated delay;

[0073] An average delay calculation module 25, configured to obtain an average delay coefficient for each wiring module according to the delay correction coefficients in the wiring module;

[0074] A corrected delay generation module 26, configured to obtain the corrected delay between two wiring units in each wiring group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the wiring module.

[0075] During actual operation, the specific limitations of the delay estimation device for programmable devices can be referred to the limitations of the delay estimation method for programmable devices in the above text, and will not be elaborated here. Each module in the above delay estimation device for programmable devices can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or independent of it, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0076] Figure 4 is a schematic structural diagram of the electronic device according to the third embodiment of the present invention. As Figure 4 shown, the electronic device 30 includes a processor 31 and a memory 32 coupled to the processor 31.

[0077] The memory 32 stores program instructions for implementing the delay estimation method of the programmable device in any of the above embodiments.

[0078] The processor 31 is configured to execute the program instructions stored in the memory 32 to process sewage monitoring data.

[0079] Among them, the processor 31 can also be referred to as a CPU (Central Processing Unit). The processor 31 may be an integrated circuit chip with signal processing capabilities. The processor 31 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0080] Refer to Figure 5 , Figure 5 is a schematic structural diagram of the storage medium according to the fourth embodiment of the present invention. The storage medium 40 according to the fourth embodiment of the present invention stores program instructions 41 that can implement all of the above methods. Among them, the program instructions 41 can be stored in the above storage medium in the form of a software product, including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present invention. And the foregoing storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, or terminal devices such as computers, servers, mobile phones, and tablets.

[0081] In several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0082] In addition, each functional unit in various embodiments of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units. The above is only the implementation manner of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied to other related technical fields, is equally included in the patent protection scope of the present invention.

[0083] Those of ordinary skill in the art can understand that all or part of the processes of implementing the above-mentioned embodiment methods can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile and / or volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned method embodiments. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided by the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0084] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the present application only takes the above division of each functional unit and module as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. For those of ordinary skill in the art, without departing from the inventive concept of the present invention, improvements can still be made, but these all fall within the protection scope of the present invention.

Claims

1. A method for estimating the delay of a programmable device, characterized in that, Including: Entering multiple wired units with completed wiring into a planar coordinate system; Obtaining a relative coordinate vector between any two wired units according to the coordinates of the wired units in the planar coordinate system; Dividing all wired units into multiple wiring modules according to the relative coordinate vector, where each wiring module includes at least one wiring group formed by two wired units, and the relative coordinate vectors corresponding to each wiring group in each wiring module are equal; Obtaining the actual delay and estimated delay between two wired units in each wiring group, and calculating the delay correction coefficient of each wiring group according to the actual delay and the estimated delay; Obtaining the average delay coefficient of each wiring module according to the delay correction coefficients in each wiring module; Obtaining the corrected delay between two wired units in each wiring group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the wiring module.

2. The delay estimation method of the programmable device according to claim 1, characterized in that The step of obtaining the actual delay and estimated delay between two wired units in each wiring group, and calculating the delay correction coefficient of each wiring group according to the actual delay and the estimated delay includes: Obtaining the actual delay between two wired units in each wiring group according to the actual working conditions; Searching a preset delay estimation table to obtain the estimated delay between two wired units in each wiring group, where the delay estimation table is used to record the estimated delay between two wired units in the wiring group; Dividing the actual delay of each wiring group by the estimated delay corresponding to each wiring group to obtain the delay correction coefficient of each wiring group.

3. The delay estimation method of the programmable device according to claim 2, wherein Including: The step of obtaining the average delay coefficient of each wiring module according to the delay correction coefficients in each wiring module includes: Respectively obtaining the average value of the delay correction coefficients corresponding to each wiring group in each wiring module to obtain the average delay coefficient of each wiring module.

4. The method for estimating the delay of a programmable device according to claim 1 or 2 or 3, characterized in that The step of obtaining a relative coordinate vector between any two wired units according to the coordinates of the wired units in the planar coordinate system includes: Obtaining the horizontal coordinate and vertical coordinate of each wired unit; Determining the starting wired unit and the target wired unit among the any two wired units; Subtracting the horizontal coordinate of the starting wired unit from the horizontal coordinate of the target wired unit to obtain the horizontal coordinate difference of the relative coordinate vector, and subtracting the vertical coordinate of the starting wired unit from the vertical coordinate of the target wired unit to obtain the vertical coordinate difference of the relative coordinate vector; Pointing from the starting wired unit to the target wired unit, and obtaining the relative coordinate vector between the two wired units according to the horizontal coordinate difference and vertical coordinate difference of the relative coordinate vector.

5. The method for estimating the delay of a programmable device according to claim 4, wherein Including: The step of obtaining the corrected delay between two wired units in each wiring group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the wiring module includes: Obtaining the relative coordinate vector of any two wired units; Determining the wiring group formed by the any two wired units according to the relative coordinate vector; Determining the wiring module where the any two wired units are located according to the wiring group; Obtain the average delay coefficient of any two wiring units according to the wiring module; Query the preset delay estimation table to obtain the estimated delay of any two wiring units; Multiply the average delay coefficient of any two wiring units by their respective corresponding estimated delays to obtain the corrected delay of any two wiring units.

6. The method for estimating the delay of a programmable device according to claim 5, wherein After obtaining the corrected delay of any two wiring units, it further includes: Construct a delay correction table according to the corrected delay of any two wiring units and the relative coordinate vector between any two wiring units.

7. The method for estimating the delay of a programmable device according to claim 6, wherein After obtaining the average delay coefficient of each wiring module, before obtaining the corrected delay of any two wiring units according to the preset delay estimation table, the relative coordinate vector, and the average delay coefficient of the wiring module, it further includes: Establish a delay correction coefficient matrix according to the relative coordinate vector, the average delay coefficient of each wiring module, and the corrected delay of any two wiring units; Wherein, the first column of the first delay correction coefficient matrix is the horizontal coordinate difference of the relative coordinate vector corresponding to the wiring module, the second column is the vertical coordinate difference of the relative coordinate vector corresponding to the wiring module, the third column is the average delay coefficient corresponding to the wiring module, and the fourth column is the corrected delay corresponding to the wiring module.

8. A delay estimation device for a programmable device, characterized in that It includes: A wiring entry module for entering multiple completed wiring units into a plane coordinate system; A vector generation module for obtaining the relative coordinate vector between any two wiring units according to the coordinates of the wiring units in the plane coordinate system; A wiring division module for dividing all wiring units into multiple wiring modules according to the relative coordinate vector, where the wiring module includes at least one wiring group formed by two wiring units, and the relative coordinate vectors corresponding to each wiring group in each wiring module are equal; A correction coefficient generation module for obtaining the actual delay and the estimated delay between two wiring units in each wiring group, and calculating the delay correction coefficient of each wiring group according to the actual delay and the estimated delay; An average delay calculation module for obtaining the average delay coefficient of each wiring module according to the delay correction coefficients in each wiring module; A corrected delay generation module for obtaining the corrected delay of two wiring units in each wiring group according to the obtained estimated delay, the relative coordinate vector, and the average delay coefficient of the wiring module.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the delay estimation method of the programmable device as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the delay estimation method of the programmable device as described in any one of claims 1 to 7.

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