A method for reducing the risk of short circuit between contact hole and polysilicon

Abstract

The present invention provides a method for reducing the risk of short circuit between a contact hole and polysilicon. The method comprises providing a standard CD of the contact hole, etching according to a size larger than the standard CD to form a contact hole; forming an oxide layer in the contact hole; forming a SiOCN layer on the oxide layer in the contact hole; and etching to remove the oxide layer and the SiOCN layer at the bottom of the contact hole. The present invention deposits oxide and SiOCN in the contact hole to reduce the CD of the contact hole. SiOCN also serves as a sidewall protection layer. The oxide layer maintains capacitance, and SiOCN has a smaller k value than SIN, and the capacitance increases less. When etching the SiOCN and the oxide layer at the bottom of the contact hole, the sidewall SiOCN is resistant to etching, which is used to protect the sidewall and reduce the risk of short circuit between the contact hole and polysilicon.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for reducing the risk of short-circuiting between a contact hole and polysilicon. Background Art

[0002] In the existing contact hole technology, silicon oxide is used as the interlayer dielectric layer (ILD), and metal is directly deposited after the contact hole etching (CT Etch) is completed to form the contact hole.

[0003] However, as the device size decreases, the risk of shorting between the contact hole CT and polysilicon (Poly) increases, and the overlay shift (Overlay Shift) needs to be strictly controlled. There are two ideas for this. One is to reduce the critical dimension CD of the contact hole CT through photolithography (Photo) and etching (Etch), but it will lead to a reduction in the photolithography window (Photo Window) and an increase in the risk of etching open (EtchOpen). The other is to increase the polysilicon spacing (Poly Space), such as reducing the polysilicon (Poly CD), but the device leakage increases; or relax the design rules (Design Rule), but it increases the cost.

[0004] Therefore, a new method needs to be proposed to solve the above problems. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for reducing the risk of short circuit between contact holes and polysilicon, so as to solve the problems in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for reducing the risk of short circuit between contact holes and polysilicon, which at least comprises:

[0007] Step 1, providing a standard CD of the contact hole, and etching according to a size larger than the standard CD to form the contact hole;

[0008] Step 2: forming an oxide layer in the contact hole;

[0009] Step 3, forming a SiOCN layer on the oxide layer in the contact hole;

[0010] Step 4: etching and removing the oxide layer and the SiOCN layer at the bottom of the contact hole.

[0011] Preferably, in step 2, a deposition method is used to form the oxide layer in the contact hole.

[0012] Preferably, in step 2, the oxide layer is formed in the contact hole by using an atomic layer deposition method.

[0013] Preferably, the oxide layer formed in step 2 is silicon oxide.

[0014] Preferably, in step 2, the oxide layer is formed on both the sidewall and the bottom of the contact hole.

[0015] Preferably, in step three, the method of forming the SiOCN layer in the contact hole is an atomic layer deposition method.

[0016] Preferably, while the oxide layer and the SiOCN layer at the bottom of the contact hole are removed by etching in step 4, the oxide layer and the SiOCN layer at both sides outside the contact hole are also removed.

[0017] Preferably, after the oxide layer and the SiOCN layer at the bottom of the contact hole are removed by etching in step 4, the CD of the contact hole is the standard CD.

[0018] As described above, the method of reducing the risk of short circuit between contact hole and polysilicon of the present invention has the following beneficial effects: the present invention deposits oxide and SiOCN in the contact hole to reduce the CD of the contact hole, and SiOCN also serves as a sidewall protection layer, the oxide layer maintains capacitance, and SiOCN has a smaller k value than SIN, and the capacitance increase is less. When etching SiOCN and the oxide layer at the bottom of the contact hole, the sidewall SiOCN is etch-resistant to protect the sidewall, while reducing the risk of short circuit between the contact hole and polysilicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram showing the structure of etching a contact hole larger than a standard CD in the present invention;

[0020] Figure 2 It is a schematic diagram of the structure after an oxide layer is formed in the contact hole in the present invention;

[0021] Figure 3 It is a schematic diagram showing the structure of forming a SiOCN layer in a contact hole in the present invention;

[0022] Figure 4 It is a schematic diagram of the structure after the oxide layer and SiOCN layer at the bottom of the contact hole are etched away in the present invention;

[0023] Figure 5 It is a flow chart of the method for reducing the risk of short circuit between contact hole and polysilicon according to the present invention. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0026] The present invention provides a method for reducing the risk of short circuit between contact holes and polysilicon. Figure 5 As shown, Figure 5 The flowchart of the method for reducing the risk of short circuit between contact hole and polysilicon according to the present invention is shown, and the method at least comprises the following steps:

[0027] Step 1: provide a standard CD of the contact hole, and etch according to a size larger than the standard CD to form the contact hole; Figure 1 As shown, Figure 1 The structure schematic diagram of the contact hole 01 formed by etching in the present invention is shown. The standard CD in step 1 refers to the CD (critical dimension) of the contact hole after forming according to the actual process. The critical dimension of the contact hole 01 formed by etching in step 1 is larger than the standard CD.

[0028] Step 2: forming an oxide layer in the contact hole; Figure 2 As shown, Figure 2 The structure diagram after forming an oxide layer in the contact hole in the present invention is shown. In step 2, the oxide layer 02 is formed in the contact hole 01.

[0029] According to the present invention, in step 2 of this embodiment, a deposition method is used to form the oxide layer in the contact hole.

[0030] In step 2, the oxide layer is formed in the contact hole by using atomic layer deposition (ALD).

[0031] According to the present invention, the oxide layer formed in step 2 of this embodiment is silicon oxide.

[0032] According to the present invention, in step 2 of this embodiment, the oxide layer is formed on both the sidewall and the bottom of the contact hole.

[0033] Step 3: forming a SiOCN layer on the oxide layer in the contact hole; Figure 3 As shown, Figure 3 It is a schematic diagram of the structure of forming a SiOCN layer in a contact hole in the present invention. In step 3, a SiOCN layer 03 is formed on the oxide layer 02 in the contact hole 01. The SiOCN layer covers the oxide layer on the sidewall and bottom of the contact hole.

[0034] Furthermore, in the present invention, in step three of this embodiment, the method for forming the SiOCN layer in the contact hole is atomic layer deposition (ALD).

[0035] Step 4: Etch and remove the oxide layer and the SiOCN layer at the bottom of the contact hole. Figure 4 As shown, Figure 4 It is a schematic diagram of the structure after the oxide layer and the SiOCN layer at the bottom of the contact hole are etched away in the present invention.

[0036] Furthermore, in the present invention, while the oxide layer and the SiOCN layer at the bottom of the contact hole are etched away in step 4 of this embodiment, the oxide layer and the SiOCN layer at both sides outside the contact hole are also removed.

[0037] In the present invention, after the oxide layer and the SiOCN layer at the bottom of the contact hole are removed by etching in step 4 of this embodiment, the CD of the contact hole is the standard CD. That is, the CD of the contact hole after being covered with the oxide layer and the SiOCN layer is smaller than the CD of the contact hole formed in step 1, and the CD of the contact hole after being covered with the oxide layer and the SiOCN layer is the standard CD.

[0038] In summary, the present invention deposits oxide and SiOCN in the contact hole to reduce the CD of the contact hole. SiOCN also serves as a sidewall protection layer. The oxide layer maintains capacitance, and SiOCN has a smaller k value than SIN, so the capacitance increase is less. When etching the SiOCN and the oxide layer at the bottom of the contact hole, the sidewall SiOCN is resistant to etching, which is used to protect the sidewall and reduce the risk of short circuit between the contact hole and polysilicon. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0039] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for reducing the risk of short circuit between contact holes and polysilicon, characterized in that: At least: Step 1, providing a standard CD of the contact hole, and etching according to a size larger than the standard CD to form the contact hole; Step 2: forming an oxide layer in the contact hole; Step 3, forming a SiOCN layer on the oxide layer in the contact hole; Step 4: etching and removing the oxide layer and the SiOCN layer at the bottom of the contact hole, and at the same time, the oxide layer and the SiOCN layer on both sides outside the contact hole are also removed, and the oxide layer and the SiOCN layer on the side wall of the contact hole are retained to form a target contact hole; the CD of the target contact hole is the standard CD.

2. The method for reducing the risk of short circuit between contact hole and polysilicon according to claim 1, characterized in that: In step 2, the oxide layer is formed in the contact hole by a deposition method.

3. The method for reducing the risk of short circuit between contact hole and polysilicon according to claim 2, characterized in that: In step 2, the oxide layer is formed in the contact hole by using an atomic layer deposition method.

4. The method for reducing the risk of short circuit between contact holes and polysilicon according to claim 3, characterized in that: The oxide layer formed in step 2 is silicon oxide.

5. The method for reducing the risk of short circuit between contact holes and polysilicon according to claim 1, characterized in that: In step 2, the oxide layer is formed on the sidewall and the bottom of the contact hole.

6. The method for reducing the risk of short circuit between contact holes and polysilicon according to claim 1, characterized in that: In step three, the method for forming the SiOCN layer in the contact hole is atomic layer deposition.

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