Dynamic random access memory and method of manufacturing the same

Abstract

A dynamic random access memory and a manufacturing method thereof are disclosed. The dynamic random access memory includes a substrate, an isolation structure disposed in the substrate, a plurality of bit lines disposed on the substrate, a plurality of storage node contact plugs disposed between the bit lines and directly contacting an active region, and a plurality of storage node contact pads disposed on the storage node contact plugs and partially overlapping the bit lines, respectively. The storage node contact pads include a first sidewall located directly above the bit lines and a second sidewall located directly above the storage node contact plugs. The dynamic random access memory further includes a metal nitride layer covering at least the first sidewall and the second sidewall of the storage node contact pads.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of fabricating the same, and more particularly to a dynamic random access memory (DRAM) and a method of fabricating the same. BACKGROUND

[0002] A dynamic random access memory (DRAM) is a volatile memory device including an array area composed of a plurality of memory cells and a peripheral area composed of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor, and the transistor controls storage or release of electric charges in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control access to data of each memory cell through a word line (WL) and a bit line (BL) which cross the array area and are electrically connected to each memory cell.

[0003] To reduce the size of the memory cell and fabricate a chip with higher integration, the structure of the memory cell has been developed in three dimensions, such as using a buried word line and a stacked capacitor. The stacked capacitor is vertically arranged above the substrate, which can save the substrate area occupied by the capacitor and also can easily obtain a larger capacitance by increasing the height of the electrode plate of the capacitor. Currently, the stacked capacitor is electrically connected to the transistor fabricated in the substrate through a storage node contact structure. There is still a need for a storage node contact structure which can provide good electrical connection quality to ensure the performance of the DRAM. SUMMARY

[0004] The present application provides a DRAM and a method of fabricating the same, which includes forming a metal nitride layer on the surface of the metal material exposed by the storage node contact plug and the storage node contact pad after forming the storage node contact plug and the storage node contact pad, using a nitriding process. The metal nitride layer can reduce the problem of deterioration of the metal material due to reaction with air and / or gases used in subsequent processes, thereby improving the electrical connection quality of the storage node contact pad.

[0005] A dynamic random access memory according to an embodiment of the present application includes a substrate, isolation structures disposed within the substrate, a plurality of bit lines disposed on the substrate, a plurality of storage node contact plugs disposed between the bit lines and directly contacting the active regions, and a plurality of storage node contact pads disposed on the storage node contact plugs and overlapping with top surface portions of the bit lines. The storage node contact pads include first sidewalls located directly above the bit lines and second sidewalls located directly above the storage node contact plugs. A metal nitride layer is formed on at least the first sidewalls and the second sidewalls of the storage node contact pads.

[0006] A method of fabricating a dynamic random access memory according to an embodiment of the present application includes the following steps. First, a substrate is provided and a plurality of bit lines are formed on the substrate. Next, a plurality of storage node contact plugs are formed between the bit lines and a plurality of storage node contact pads are disposed on the storage node contact plugs, respectively, wherein the storage node contact pads overlap with top surface portions of the bit lines and include first sidewalls located directly above the bit lines and second sidewalls located directly above the storage node contact plugs. Subsequently, a nitridation fabrication process is performed to form a metal nitride layer on at least the first sidewalls and the second sidewalls of the storage node contact pads. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of some embodiments. It will be appreciated that all drawings are schematic and for illustrative purposes only. Relative dimensions and proportions of parts in the drawings have been shown exaggerated or reduced in size for the convenience of explanation. Identical symbols often appear in different drawings to indicate like or similar features.

[0008] Figures 1 to 10 A schematic diagram of a method of fabricating a dynamic random access memory according to an embodiment of the present application is shown in FIG. 1. Figure 1 and Figure 2 is a plan view, Figures 3 to 10 is a cross-sectional view taken along line A-A' in Figure 2 .

[0009] Figure 11 A cross-sectional schematic diagram of a dynamic random access memory according to another embodiment of the present application is shown in FIG. 2.

[0010] In the drawings, like reference numerals refer to like elements throughout.

[0011] 10 substrate

[0012] 12 active region

[0013] 14 isolation structure

[0014] 16 buried word line

[0015] 18 recess

[0016] 20 bit line

[0017] 20a semiconductor layer

[0018] 20b metal layer

[0019] 20c mask layer

[0020] 32 first sidewall sub

[0021] 34 second sidewall sub

[0022] 36 third sidewall sub

[0023] 38 dielectric layer

[0024] 42 semiconductor layer

[0025] 44 barrier layer

[0026] 50 metal layer

[0027] 51 trench

[0028] 52 storage node contact plug

[0029] 52c top surface

[0030] 54 storage node contact pad

[0031] 54a first sidewall

[0032] 54b second sidewall

[0033] 54c top surface

[0034] 62 metal nitride layer

[0035] 70 dielectric layer

[0036] 72 etch stop layer

[0037] 74 first support layer

[0038] 76 second support layer

[0039] 80 capacitor structure

[0040] 82 bottom electrode layer

[0041] 84 capacitor dielectric layer

[0042] 86 top electrode layer

[0043] A-A' tangent line

[0044] P1 Depression Manufacturing Process

[0045] P2 Cleaning process

[0046] P3 Nitriding Process

[0047] P4 planarization process

[0048] T1 thickness

[0049] T2 thickness Detailed Implementation

[0050] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0051] Figures 1 to 10 This is a schematic diagram of a method for manufacturing a dynamic random access memory according to an embodiment of the present invention, wherein... Figure 1 and Figure 2 This is a floor plan. Figures 3 to 10 For along Figure 2 A cross-sectional view of the tangent line A-A'. Please refer to the diagram. Figure 1 First, a substrate 10 is provided, such as a silicon substrate, epitaxial silicon substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator (SOI) substrate, but not limited thereto. An isolation structure 14 is provided within the substrate 10 to define a plurality of active regions 12 within the substrate 10. The isolation structure 14 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations thereof, but not limited thereto. A plurality of embedded word lines 16 are disposed in the substrate 10 and cut through each active region 12 to divide each active region 12 into two ends and a middle portion.

[0052] Please refer to Figure 2 and Figure 3Next, an etching process can be performed on the substrate 10 to form a recess 18 in the middle of the active region 12 and the nearby isolation structure 14. Then, multiple bit lines 20 are formed on the substrate 10, and the bit lines 20 pass through the recess 18 and overlap with the middle of the active region 12. Figure 3 As shown, bit line 20 may include a multilayer structure, such as a semiconductor layer 20a, a metal layer 20b, and a masking layer 20c. The semiconductor layer 20a may be made of polycrystalline silicon, amorphous silicon, or other silicon-containing or silicon-free semiconductor materials. The metal layer 20b may be made of aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum (TiAl) alloy, or other suitable low-resistance metal materials. The masking layer 20c may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but is not limited thereto. In some embodiments, an interface layer (not shown) may be included between the semiconductor layer 20a and the metal layer 20b, such as a single-layer or multi-layer structure composed of titanium (Ti), tungsten silicide (WSi), tungsten nitride (WN), and / or other metal silicides or metal nitrides, but is not limited thereto.

[0053] Please refer to Figure 4 Next, deposition and etching processes can be performed to form sidewall substructures on the sidewalls of bit line 20, and to fill the recesses 18 with the sidewall substructures. According to one embodiment of the present invention, the sidewall substructure may include a multilayer structure, for example, it may include a first sidewall 32, a second sidewall 34, and a third sidewall 36, wherein the first sidewall 32 covers the sidewalls of bit line 20 and the surface of the recesses 18, the second sidewall 34 is located on the first sidewall 32 at the bottom of bit line 20 and fills the recesses 18 on both sides of bit line 20, and the third sidewall 36 is located on the first sidewall 32 on the sidewalls of bit line 20. The first sidewall 32, the second sidewall 34, and the third sidewall 36 may each include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations of the above materials, but are not limited thereto.

[0054] Please refer to Figure 5A deposition fabrication process can then be performed to form a dielectric layer 38 over the substrate 10 and fill the gaps between the bit lines 20, and then etch to remove portions of the dielectric layer 38 to form a plurality of contact holes (not shown) in the dielectric layer 38 between the bit lines 20, exposing portions of the substrate 10 (e.g., the ends of the active regions 12). Subsequently, an epitaxial growth can be performed to form a semiconductor layer 42 at the bottom of the contact holes, and then a deposition fabrication process can be performed to form a barrier layer 44 and a metal layer 50 over the semiconductor layer 42 and the bit lines 20. After the metal layer 50 is formed, a planarization fabrication process (e.g., a chemical mechanical polishing fabrication process) can be performed to remove portions of the metal layer 50 until the metal layer 50 over the bit lines 20 reaches a predetermined thickness, and to provide the metal layer 50 with a planar surface.

[0055] The semiconductor layer 42 is in direct contact with the substrate 10, and the material can include single crystal silicon, polysilicon, silicon phosphide (SiP), but is not limited thereto. In some embodiments, the substrate 10 (e.g., the ends of the active regions 12) exposed from the contact holes can also be etched to be recessed during the fabrication of the contact holes to increase the contact area of the semiconductor layer 42 with the substrate (the ends of the active regions 12). The barrier layer 44 conformally covers along the top surface of the semiconductor layer 42 and the sidewalls and top surface of the bit lines 20, and the material can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten (Ti / W), or a combination thereof, but is not limited thereto. The metal layer 50 includes a metal material, such as aluminum (Al), tungsten (W), copper (Cu), titanium aluminum (TiAl) alloy, or other suitable metal material. According to an embodiment of the present application, the barrier layer 44 includes titanium nitride (TiN), and the metal layer 50 includes tungsten (W).

[0056] The material of the dielectric layer 38 can include silicon oxide, but is not limited thereto. In some embodiments, a portion of the dielectric layer 38 can remain on the sidewalls of the bit lines 20, between the third sidewall sub 36 and the barrier layer 44. In some embodiments, a metal silicide layer (not shown) can be included between the barrier layer 44 and the semiconductor layer 42, and the material can include titanium silicide (TiSix), tungsten silicide (Wsix), tantalum silicide (TaSix), molybdenum silicide (MoSix), cobalt silicide (CoSix), or nickel silicide (NiSix), or a combination thereof, but is not limited thereto.

[0057] Reference is made to Figure 6Then, a recessing process P1 can be performed to etch and remove unwanted portions of the metal layer 50 and the barrier layer 44 to pattern the metal layer 50 and the barrier layer 44, resulting in the storage node contact plug 52 located within the contact hole and the storage node contact pad 54 located above the storage node contact plug 52 and separated by the trench 51. That is, the storage node contact plug 52 and the storage node contact pad 54 are integrally formed and comprise the same material (i.e., the metal material of the metal layer 50). As shown in Figure 6 the storage node contact pad 54 can be offset to one side of the bit line 20 and partially overlap the top surface of the bit line 20, and comprise a first sidewall 54a located directly above the bit line 20 and a second sidewall 54b located directly above the storage node contact plug 52.

[0058] In some embodiments, to ensure that there is no residual metal layer 50 and / or barrier layer 44 between the storage node contact pads 54, the etching step to form the trench 51 can be etched down until the bottom surface of the trench 51 is lower than the top surface of the bit line 20 (the top surface of the masking layer 20c). Thus, the storage node contact pad 54 can have a cross-sectional shape similar to an inverted L shape, and the bottom end of the second sidewall 54b can be lower than the bottom end of the first sidewall 54a, and the length of the second sidewall 54b in the vertical direction can be greater than the length of the first sidewall 54a in the vertical direction.

[0059] In some embodiments, a cleaning process P2 can be performed after the recessing process P1 to remove etching byproducts (e.g., polymers) attached to the surface and particles of the metal layer 50 material redeposited or fallen onto the surface. The cleaning process P2 can comprise any suitable dry or wet cleaning method, such as plasma cleaning, solvent cleaning, spray cleaning, etc., but is not limited thereto.

[0060] Please refer to Figure 7 After the cleaning process P2 is completed, a nitridation process P3, such as a decoupled plasma nitridation (DPN) process, can be performed to nitride any exposed metal material of the metal layer 50 to form a metal nitride layer 62 on the exposed surface of the metal layer 50. As shown in Figure 7 the metal nitride layer 62 can continuously cover the first sidewall 54a, the second sidewall 54b and the top surface 54c of the storage node contact pad 54 and the top surface 52c of the storage node contact plug 52. The metal nitride layer 62 can have a uniform thickness T1. According to an embodiment of the present application, the thickness T1 can be between about 10-40 angstroms.

[0061] The metal nitride layer 62 is a nitride of the metal material of the metal layer 50, that is, when the metal layer 50 comprises tungsten (W), the metal nitride layer 62 can comprise tungsten nitride (WN). The metal nitride layer 62 can block the metal material of the storage node contact plug 52 and the storage node contact pad 54 from air, can reduce abnormality caused by reaction between the metal material and gas (e.g. oxygen or moisture) in air during Q-time, and can improve quality of the storage node contact plug 52 and the storage node contact pad 54, especially can improve electrical connection quality between the storage node contact pad 54 and a stacked capacitor (not shown) subsequently fabricated thereon.

[0062] Please refer to Figure 8 and Figure 9 . Then, a deposition fabrication process can be performed to form a dielectric layer 70 on the substrate 10, and the dielectric layer 70 completely covers the storage node contact pad 54 and fills the trench 51, and a planarization fabrication process P4 (e.g. a chemical mechanical polishing fabrication process) is performed to remove part of the dielectric layer 70 until the metal nitride layer 62 on the top surface 54c of the storage node contact pad 54 is exposed. The dielectric layer 70 is separated from the storage node contact plug 52 and the storage node contact pad 54 by the metal nitride layer 62 without direct contact. The material of the dielectric layer 70 can comprise silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric material such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or a combination thereof, but is not limited thereto. The metal nitride layer 62 can block the storage node contact plug 52 and the storage node contact pad 54 from process gas used in the deposition fabrication process for fabricating the dielectric layer 70, and can reduce the chance of reaction between the storage node contact plug 52 and the storage node contact pad 54 and the process gas.

[0063] The metal nitride layer 62 on the top surface 54c of the storage node contact pad 54 is also removed by part in the planarization fabrication process P4, and thus the thickness T2 of the metal nitride layer 62 covering the top surface 54c is smaller than the thickness T1 of the metal nitride layer 62 covering the first sidewall 54a and the second sidewall 54b after the planarization fabrication process P4. According to an embodiment of the present application, the thickness T2 can be between about 10-20 angstroms. As shown in FIG. 4B, the dielectric layer 70 is formed on the substrate 10, and the dielectric layer 70 completely covers the storage node contact pad 54 and fills the trench 51. The dielectric layer 70 is separated from the storage node contact plug 52 and the storage node contact pad 54 by the metal nitride layer 62 without direct contact. The material of the dielectric layer 70 can comprise silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric material such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or a combination thereof, but is not limited thereto. The metal nitride layer 62 can block the storage node contact plug 52 and the storage node contact pad 54 from process gas used in the deposition fabrication process for fabricating the dielectric layer 70, and can reduce the chance of reaction between the storage node contact plug 52 and the storage node contact pad 54 and the process gas. Figure 9As shown, the metal nitride layer 62 covering the storage node contact pad 54 can have an inverted U-shaped cross-sectional shape, in which the metal nitride layer 62 on the first sidewall 54a is in direct contact with the top surface of the barrier layer 44 on the bit line 20, and can be trimmed flush with the sidewall of the barrier layer 44 in the vertical direction. Since the length of the second sidewall 54b is greater than that of the first sidewall 54a, the length of the portion of the metal nitride layer 62 on the second sidewall 54b is also greater than that of the portion on the first sidewall 54a. The metal nitride layer 62 covering the top surface 52c of the storage node contact plug 52 is in direct contact with the sidewall of the barrier layer 44 on the bit line 20 sidewall, and can be trimmed flush with the top surface of the barrier layer 44 in the horizontal direction.

[0064] Referring to Figure 10 After the planarization process P4 is completed, a capacitor structure 80 can be formed over the substrate 10. According to an embodiment of the present application, the capacitor structure 80 can be formed by the following steps. First, a deposition process is performed to sequentially form an etch stop layer 72, a first sacrificial layer (not shown), a first support layer 74, a second sacrificial layer (not shown), and a second support layer 76 over the substrate 10. The materials of the etch stop layer 72, the first support layer 74, and the second support layer 76 are different from those of the first sacrificial layer (not shown) and the second sacrificial layer (not shown) so that the first sacrificial layer and the second sacrificial layer can be removed by a selective etching process in a subsequent step. According to an embodiment of the present application, the first sacrificial layer and the second sacrificial layer can include silicon oxide, and the etch stop layer 72, the first support layer 74, and the second support layer 76 can include silicon nitride (SiN), silicon carbon nitride (SiCN), boron-doped silicon nitride (SiBN), silicon oxynitride (SiON), etc., but are not limited thereto.

[0065] Next, an etching fabrication process is performed to form a plurality of bottom electrode openings (not shown) that penetrate the second support layer 76, the second sacrificial layer, the first support layer 74, the first sacrificial layer, and the etching stop layer 72, and are aligned to the respective storage node contact pads 54, and the bottom portions of the bottom electrode openings penetrate the metal nitride layer 62 directly above the storage node contact pads 54. Then, a deposition fabrication process is performed to form a bottom electrode layer 82 along the sidewalls and the bottom surface of the bottom electrode openings, and then the bottom electrode layer 82 is used to provide structural support, and the second sacrificial layer and the first sacrificial layer are selectively etched away through the openings of the second support layer 76 and the openings of the first support layer 74 to form cavities (not shown) between the second support layer 76, the first support layer 74, and the etching stop layer 72, exposing the sidewalls of the bottom electrode layer 82 and the surface of the etching stop layer 72. Next, a deposition fabrication process is performed to form a capacitor dielectric layer 84 conformally along the sidewalls of the bottom electrode layer 82, the surface of the first support layer 74, the surface of the second support layer 76, and the surface of the etching stop layer 72, and then a top electrode layer 86 is formed to fill the cavities between the second support layer 76, the first support layer 74, and the etching stop layer 72 and the gaps between the bottom electrode layer 82, obtaining a capacitor structure 80. As shown in Figure 10 FIG. 2, the bottom electrode layer 82 of the capacitor structure 80 is disposed directly above the respective storage node contact pads 54 and in direct contact with the storage node contact pads 54 and the metal nitride layer 62. The etching stop layer 72 is separated from the storage node contact pads 54 by the metal nitride layer 62 and is not in direct contact with the storage node contact pads 54.

[0066] The bottom electrode layer 82 and the top electrode layer 86 of the capacitor structure 80 can comprise conductive materials, such as low-resistance metal materials including aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), but are not limited thereto. The capacitor dielectric layer 84 can comprise dielectric materials and can comprise a single layer or a multi-layer structure. According to an embodiment of the present application, the capacitor dielectric layer 84 can comprise high-k dielectric materials, such as hafnium oxide (Hf02), hafnium silicon oxide (HfSi04), hafnium silicon oxynitride (HfSiON), zirconium oxide (Zr02), titanium oxide (Ti02), aluminum oxide (Al203), tantalum oxide (Ta205), zirconium-aluminum-zirconium oxide (ZAZ), or metal oxides thereof, but are not limited thereto. According to an embodiment of the present application, the capacitor dielectric layer 84 can comprise an ONO stack comprising silicon oxide, silicon nitride, and silicon oxide.

[0067] Please refer to Figure 11 , which is a cross-sectional view of a dynamic random access memory according to another embodiment of the present application, which is similar to Figure 9The structures of the dynamic random access memory shown are largely the same, including a substrate 10, bit lines 20, memory node contact plugs 52, memory node contact pads 54, and a metal nitride layer 62, etc., which will not be described in detail here. This embodiment mainly illustrates that the metal nitride layer 62 on the top surface 54c of the memory node contact pad 54 can be completely removed in the planarization process P4, exposing the top surface 54c of the memory node contact pad 54. Subsequently, an etch stop layer (e.g., etch stop layer) can be formed on the substrate 10. Figure 10 Etching stop layer 72) and capacitor structure (e.g. Figure 10 (Capacitor structure 80). In this embodiment, since the metal nitride layer 62 on the top surface 54c of the storage node contact pad 54 has been completely removed during the planarization process P4, the etch stop layer can directly contact the storage node contact pad 54.

[0068] In summary, the dynamic random access memory of the present invention utilizes a nitridation process to form a metal nitride layer along the surface of the metal materials of the storage node contact plug 52 and the storage node contact pad 54. This metal nitride layer isolates the metal materials of the storage node contact plug 52 and the storage node contact pad 54 from air or process gases used in subsequent manufacturing processes, reducing the problem of deterioration caused by the reaction of the metal materials of the storage node contact plug 52 and the storage node contact pad 54 with air and / or process gases, and improving the quality of electrical connections.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic random access memory, characterized by, The semiconductor layer is below the storage node contact plug and directly contacts the substrate, a bottom surface of the semiconductor layer is lower than a top surface of the substrate; a barrier layer is disposed between the semiconductor layer, the bit line, and the storage node contact plug. The metal nitride layer is directly in contact with a top surface of the barrier layer on the portion of the metal nitride layer on the second sidewall and is cut flush with a sidewall of the barrier layer in a vertical direction. The metal nitride layer is directly in contact with a sidewall of the barrier layer on the portion of the metal nitride layer on the first sidewall and is cut flush with a top surface of the barrier layer in a horizontal direction. The metal nitride layer also covers a top surface of the storage node contact plug. The metal nitride layer also covers a top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape. The metal nitride layer on the portion of the top surface of the storage node contact pad has a thickness that is less than a thickness of the metal nitride layer on the portions of the first sidewall and the second sidewall. The semiconductor layer is below the storage node contact plug and directly contacts the substrate, a bottom surface of the semiconductor layer is lower than a top surface of the substrate; a barrier layer is disposed between the semiconductor layer, the bit line, and the storage node contact plug. The metal nitride layer is directly in contact with a top surface of the barrier layer on the portion of the metal nitride layer on the second sidewall and is cut flush with a sidewall of the barrier layer in a vertical direction. The metal nitride layer is directly in contact with a sidewall of the barrier layer on the portion of the metal nitride layer on the first sidewall and is cut flush with a top surface of the barrier layer in a horizontal direction.

2. The dynamic random access memory of claim 1, wherein, The metal nitride layer also covers a top surface of the storage node contact plug.

3. The dynamic random access memory of claim 1, wherein, The metal nitride layer also covers a top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape.

4. The dynamic random access memory of claim 3, wherein, The metal nitride layer on the portion of the top surface of the storage node contact pad has a thickness that is less than a thickness of the metal nitride layer on the portions of the first sidewall and the second sidewall.

5. The dynamic random access memory of claim 1, wherein, The semiconductor layer is below the storage node contact plug and directly contacts the substrate, a bottom surface of the semiconductor layer is lower than a top surface of the substrate; a barrier layer is disposed between the semiconductor layer, the bit line, and the storage node contact plug.

6. The dynamic random access memory of claim 1, wherein, The metal nitride layer is directly in contact with a top surface of the barrier layer on the portion of the metal nitride layer on the second sidewall and is cut flush with a sidewall of the barrier layer in a vertical direction.

7. The dynamic random access memory of claim 1, wherein, The metal nitride layer is directly in contact with a sidewall of the barrier layer on the portion of the metal nitride layer on the first sidewall and is cut flush with a top surface of the barrier layer in a horizontal direction.

8. The dynamic random access memory of claim 1, wherein, The metal nitride layer also covers a top surface of the storage node contact plug.

9. The dynamic random access memory of claim 8, wherein, The metal nitride layer also covers a top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape.

10. A method for fabricating a dynamic random access memory, the method comprising: The metal nitride layer on the portion of the top surface of the storage node contact pad has a thickness that is less than a thickness of the metal nitride layer on the portions of the first sidewall and the second sidewall. The semiconductor layer is below the storage node contact plug and directly contacts the substrate, a bottom surface of the semiconductor layer is lower than a top surface of the substrate; a barrier layer is disposed between the semiconductor layer, the bit line, and the storage node contact plug. The metal nitride layer is directly in contact with a top surface of the barrier layer on the portion of the metal nitride layer on the second sidewall and is cut flush with a sidewall of the barrier layer in a vertical direction. The metal nitride layer is directly in contact with a sidewall of the barrier layer on the portion of the metal nitride layer on the first sidewall and is cut flush with a top surface of the barrier layer in a horizontal direction. The metal nitride layer also covers a top surface of the storage node contact plug. The metal nitride layer also covers a top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape. The metal nitride layer on the portion of the top surface of the storage node contact pad has a thickness that is less than a thickness of the metal nitride layer on the portions of the first sidewall and the second sidewall. The semiconductor layer is below the storage node contact plug and directly contacts the substrate, a bottom surface of the semiconductor layer is lower than a top surface of the substrate; a barrier layer is disposed between the semiconductor layer, the bit line, and the storage node contact plug. The metal nitride layer is directly in contact with a top surface of the barrier layer on the portion of the metal nitride layer on the second sidewall and is cut flush with a sidewall of the barrier layer in a vertical direction. The metal nitride layer is directly in contact with a sidewall of the barrier layer on the portion of the metal nitride layer on the first sidewall and is cut flush with a top surface of the barrier layer in a horizontal direction. The metal nitride layer also covers a top surface of the storage node contact plug. The metal nitride layer also covers a top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape. The metal nitride layer on the portion of the top surface of the storage node contact pad has a thickness that is less than a thickness of the metal nitride layer on the portions of the first sidewall and the second sidewall. forming a semiconductor layer at the bottom of the contact hole, the bottom surface of the semiconductor layer being lower than the top surface of the substrate; forming a barrier layer along the top surface of the semiconductor layer and the sidewall of the bit line; forming a metal layer to fill the contact hole and cover the bit line; and performing a recessing process to pattern the metal layer; wherein the portion of the metal nitride layer on the first sidewall is in direct contact with the top surface of the barrier layer and is cut flush with the sidewall of the barrier layer in the vertical direction; and the metal nitride layer further covers the top surface of the storage node contact plug and is in direct contact with the sidewall of the barrier layer on the bit line sidewall and is cut flush with the top surface of the barrier layer in the horizontal direction.

11. The method of claim 10, wherein further comprising forming a dielectric layer between the storage node contact pads, wherein the dielectric layer and the storage node contact pads are separated by the metal nitride layer without being in direct contact.

12. The method of claim 10, wherein the method further comprises: the metal nitride layer comprises a nitride of the metal material of the storage node contact pad.

13. The method of claim 10, wherein the method further comprises: the storage node contact pad comprises tungsten and the metal nitride layer comprises tungsten nitride.

14. The method of claim 10, wherein the portion of the metal nitride layer on the second sidewall has a length greater than the portion of the metal nitride layer on the first sidewall.

15. The method of claim 10, wherein the metal nitride layer further covers the top surface of the storage node contact pad and has an inverted U-shaped cross-sectional shape.

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