A Schottky diode and a manufacturing method thereof

Abstract

This invention discloses a Schottky diode and its fabrication method. The Schottky diode includes an N-type epitaxial layer and a barrier metal layer stacked sequentially from bottom to top. A trench extending in the front-back direction is formed on the upper side of the N-type epitaxial layer. The trench is filled with a channel structure, which includes a gate oxide layer, two polysilicon layers located on both sides of the gate oxide layer, and two lightly doped P-type layers located on both sides of the two polysilicon layers. A heavily doped P-type layer connected to the lightly doped P-type layer is provided on the upper side of the N-type epitaxial layer, and the heavily doped P-type layer is in contact with the barrier metal layer. The Schottky diode provided by this invention utilizes the ohmic contact formed by the heavily doped P-type layer and the barrier metal layer, and the lightly doped P-type layer as a conductivity modulation layer, which greatly improves the surge resistance of the device without affecting the switching characteristics of the Schottky diode.

Description

Technical Field

[0001] This invention relates to the field of diode technology, and in particular to a Schottky diode and its manufacturing method. Background Technology

[0002] Schottky diodes are widely used in fast charging power supplies, but their surge protection is poor. To improve the surge protection of Schottky diodes, the current approach is to integrate the PN junction and the Schottky junction together. However, this approach reduces the switching frequency of the device. Therefore, it is extremely important to create a Schottky diode that can improve surge protection without reducing the switching frequency of the device. Summary of the Invention

[0003] The main objective of this invention is to provide a Schottky diode and its fabrication method, aiming to provide a Schottky diode that can improve surge resistance without reducing the device's switching frequency.

[0004] To achieve the above objectives, the present invention proposes a Schottky diode, comprising an N-type epitaxial layer and a barrier metal layer stacked sequentially from bottom to top. A trench extending in the front-back direction is formed on the upper side of the N-type epitaxial layer, and the trench is filled with a channel structure. The channel structure includes a gate oxide layer, two polysilicon layers located on both sides of the gate oxide layer, and two P-type lightly doped layers located on both sides of the two polysilicon layers. A P-type heavily doped layer connected to the P-type lightly doped layer is provided on the upper side of the N-type epitaxial layer, and the P-type heavily doped layer is in contact with the barrier metal layer.

[0005] Optionally, the heavily doped P-type layer is disposed corresponding to the channel structure, and both ends of the heavily doped P-type layer are respectively connected to the two lightly doped P-type layers of the channel structure.

[0006] Optionally, multiple channel structures are provided, and the multiple channel structures are spaced apart along their width direction;

[0007] In any two adjacent channel structures, a P-type heavily doped layer is provided between two adjacent lightly doped P-type layers, and the two ends of the heavily doped P-type layer are respectively connected to the two lightly doped P-type layers.

[0008] Optionally, multiple P-type heavily doped layers are provided, and the multiple P-type heavily doped layers are spaced apart along the length direction of the channel structure.

[0009] Optionally, multiple P-type heavily doped layers are provided, and the multiple P-type heavily doped layers are spaced apart along the width direction of the channel structure.

[0010] Optionally, the distance between two adjacent heavily doped P-type layers and the front side of the N-type epitaxial layer is equal; and / or,

[0011] In two adjacent P-type heavily doped layers, the distance between one and the front side of the N-type epitaxial layer is greater than the distance between the other and the front side of the N-type epitaxial layer.

[0012] Optionally, the doping concentration of the heavily doped p-type layer is 10. 11 ~10 13 cm -2 .

[0013] Optionally, the junction depth of the heavily doped P-type layer is smaller than the junction depth of the lightly doped P-type layer.

[0014] This invention also proposes a method for manufacturing a Schottky diode as described above, comprising the following steps:

[0015] A P-type ring region is prepared on the upper side of the N-type epitaxial layer;

[0016] Trenches are etched into the P-type ring region, and the remaining portion of the P-type ring region after etching forms a lightly doped P-type layer.

[0017] A gate oxide layer is prepared in the trench, and then a polycrystalline silicon layer is prepared.

[0018] A P-type heavily doped layer is prepared on the upper side of the N-type epitaxial layer corresponding to the P-type lightly doped layer;

[0019] A barrier metal layer is prepared on the upper side of the heavily doped P-type layer.

[0020] Optionally, the step of fabricating a heavily doped P-type layer on the upper side of the N-type epitaxial layer includes:

[0021] Photoresist is applied to the upper side of the N-type epitaxial layer, exposed and developed, and then ion implantation is performed. After implantation, the photoresist is removed to form a heavily doped P-type layer.

[0022] In the technical solution of this invention, a P+PN type device structure is formed by connecting the barrier metal layer and the lightly doped P-type layer through a heavily doped P-type layer. Here, P+ refers to heavily doped P-type, P- refers to lightly doped P-type, and N refers to the N-type epitaxial layer. When the device is forward-biased, under small and medium current conditions, the Schottky diode current dominates because the PN junction barrier is high, resulting in very few minority carriers injected through the PN junction, thus having a weak impact on the device's switching characteristics. Under high current conditions, especially surge conditions (typically more than 20 times the device's nominal current), the PN junction conducts, and the P+PN type region injects minority carriers into the epitaxial layer, resulting in a conductivity modulation effect, reducing the epitaxial layer resistance, and consequently reducing the device's on-state voltage drop and transient power consumption, thereby improving the device's surge resistance. Compared to the case where there is no heavily doped P-type layer and the lightly doped P-type layer is in direct contact with the barrier metal layer, the Schottky diode provided by this invention has a smaller impact on switching characteristics and stronger surge resistance. This invention utilizes a heavily doped P-type layer to form an ohmic contact with a barrier metal layer, and a lightly doped P-type layer to act as a conductivity modulation layer, thereby greatly improving the surge protection capability of the device without affecting the switching characteristics of the Schottky diode. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of an embodiment of the Schottky diode of the present invention;

[0025] Figure 2 for Figure 1 Top view;

[0026] Figure 3 This is a schematic diagram of another embodiment of the Schottky diode of the present invention;

[0027] Figure 4 This is a schematic diagram illustrating the manufacturing process of one embodiment of the Schottky diode manufacturing method of the present invention.

[0028] Explanation of icon numbers:

[0029] label name label name 1 N-type substrate 6 P-type lightly doped layer 2 N-type epitaxial layer 7 P-type heavily doped layer 3 trench 8 silicon nitride layer 4 gate oxide layer 9 P-type ring region 5 polycrystalline silicon layer

[0030] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0033] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include multiple such features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0034] Schottky diodes are widely used in fast charging power supplies, but their surge protection is poor. To improve the surge protection of Schottky diodes, the current approach is to integrate the PN junction and the Schottky junction together. However, this approach reduces the switching frequency of the device. Therefore, it is extremely important to create a Schottky diode that can improve surge protection without reducing the switching frequency of the device.

[0035] Therefore, the present invention provides a Schottky diode. Figures 1 to 3 An embodiment of the Schottky diode provided by the present invention includes an N-type substrate 1 and an N-type epitaxial layer 2 formed on the upper side of the N-type substrate 1. The optimization and improvement of the present invention lies in the N-type epitaxial layer 2. Therefore, the following will be combined with Figures 1 to 3 The structure of the N-type epitaxial layer 2 is described in detail.

[0036] like Figures 1 to 3As shown, a Schottky diode includes an N-type epitaxial layer 2 and a barrier metal layer (not shown) stacked sequentially from bottom to top. A trench 3 extending in the front-back direction is formed on the upper side of the N-type epitaxial layer 2. The trench 3 is filled with a channel structure. The channel structure includes a gate oxide layer 4, two polysilicon layers 5 located on both sides of the gate oxide layer 4, and two P-type lightly doped layers 6 located on both sides of the two polysilicon layers 5. A P-type heavily doped layer 7 connected to the P-type lightly doped layer 6 is provided on the upper side of the N-type epitaxial layer 2, and the P-type heavily doped layer 7 is in contact with the barrier metal layer.

[0037] It should be noted that the lower ends of the two polysilicon layers 5 are connected to each other, and the two polysilicon layers 5 fill the space between the inner sidewall of the trench 3 and the gate oxide layer 4.

[0038] In the technical solution of this invention, a P+PN type device structure is formed by connecting the barrier metal layer and the lightly doped P-type layer 6 through a heavily doped P-type layer 7. Here, P+ refers to heavily doped P-type, P- refers to lightly doped P-type, and N refers to the N-type epitaxial layer 2. When the device is forward-biased, under small and medium current conditions, the Schottky diode current dominates because the PN junction barrier is high, resulting in very few minority carriers injected through the PN junction, thus having a weak impact on the device's switching characteristics. Under high current conditions, especially surge conditions (typically more than 20 times the device's nominal current), the PN junction conducts, and the P+PN type region injects minority carriers into the epitaxial layer, resulting in a conductivity modulation effect, reducing the epitaxial layer resistance, and consequently reducing the device's on-state voltage drop and transient power consumption, thereby improving the device's surge resistance. Compared to the case where the heavily doped P-type layer 7 is not present, and the lightly doped P-type layer 6 is in direct contact with the barrier metal layer, the Schottky diode provided by this invention has a smaller impact on switching characteristics and stronger surge resistance. This invention utilizes the P-type heavily doped layer 7 to form an ohmic contact with the barrier metal layer, and the P-type lightly doped layer 6 to act as a conductivity modulation layer, thereby greatly improving the surge resistance of the device without affecting the switching characteristics of the Schottky diode.

[0039] Furthermore, the heavily doped P-type layer 7 is disposed corresponding to the channel structure, and both ends of the heavily doped P-type layer 7 are respectively connected to the two lightly doped P-type layers 6 of the channel structure. It should be noted that, since multiple channel structures are generally provided, there are two possibilities for the connection between the two ends of the heavily doped P-type layer 7 and the two lightly doped P-type layers 6 of the channel structure: first, the two ends of the heavily doped P-type layer 7 are connected to the two lightly doped P-type layers 6 of one channel structure; second, the two ends of the heavily doped P-type layer 7 are connected to the two lightly doped P-type layers 6, where the two lightly doped P-type layers 6 belong to two different channel structures. This invention does not impose any limitations on this.

[0040] Specifically, regarding the configuration where "the two ends of the heavily doped P-type layer 7 are connected to two lightly doped P-type layers 6, and the two lightly doped P-type layers 6 belong to two different channel structures," multiple channel structures are provided, spaced apart along their width. In any two adjacent channel structures, a heavily doped P-type layer 7 is positioned between two adjacent lightly doped P-type layers 6, and the two ends of the heavily doped P-type layer 7 are connected to two lightly doped P-type layers 6 respectively. In this case, ion implantation into the N-type epitaxial layer 2 corresponding to the lightly doped P-type layer 6 forms the heavily doped P-type layer 7, facilitating its fabrication and improving fabrication efficiency. It should be noted that two adjacent lightly doped P-type layers 6 belong to two adjacent channel structures.

[0041] Furthermore, multiple heavily doped P-type layers 7 are provided, and these layers are spaced apart along the length of the channel structure. Thus, the heavily doped P-type layers 7 and the lightly doped P-type layers 6, spaced apart along the length of the channel structure, form a trapezoidal structure. During operation of the P+PN structure, minority carriers flow through the heavily doped P-type layers 7 into the lightly doped P-type layers 6, and finally into the N-type epitaxial layer 2. Therefore, the region of the lightly doped P-type layers 6 closer to the heavily doped P-type layers 7 has a higher voltage, resulting in stronger conductance modulation during surges, while the region of the lightly doped P-type layers 6 farther from the heavily doped P-type layers 7 has a lower voltage, resulting in weaker conductance modulation during surges. Therefore, the conductance modulation mechanism of the device can be controlled by adjusting the spacing of the heavily doped P-type layers 7, thereby coordinating the relationship between the device's switching frequency and surge capability. In addition, this invention does not limit the width and spacing of the heavily doped P-type layers 7, as these are related to specific device design requirements, such as static parameters and dynamic characteristics.

[0042] The device has multiple heavily doped P-type layers 7, which are spaced apart along the width direction of the channel structure. By providing multiple heavily doped P-type layers 7, the surge immunity of the device is further optimized. Preferably, the phrase "multiple heavily doped P-type layers 7 are spaced apart along the width direction of the channel structure" can be combined with "multiple heavily doped P-type layers 7 are spaced apart along the length direction of the channel structure," that is, a trapezoidal structure composed of multiple heavily doped P-type layers 7 and lightly doped P-type layers 6 is formed on the upper side of the N-type epitaxial layer 2. (See reference [reference needed] for details.) Figure 2 and Figure 3 .

[0043] In addition, such as Figure 2 As shown, the distance between two adjacent P-type heavily doped layers 7 and the front side of the N-type epitaxial layer 2 is equal, that is, the P-type heavily doped layers 7 in the two adjacent trapezoidal structures are aligned one by one.

[0044] Of course, the P-type heavily doped layers 7 in two adjacent trapezoidal structures can also be staggered, such as... Figure 3 As shown, in two adjacent P-type heavily doped layers 7, the distance between one and the front side of the N-type epitaxial layer 2 is greater than the distance between the other and the front side of the N-type epitaxial layer 2.

[0045] Furthermore, the doping concentration of the p-type heavily doped layer 7 is 10. 11 ~10 13 cm -2 This ensures that the amount of impurities incorporated into the heavily doped P-type layer 7 is sufficient, thus guaranteeing ohmic contact between the heavily doped P-type layer 7 and the barrier metal layer.

[0046] The junction depth of the heavily doped P-type layer 7 is smaller than that of the lightly doped P-type layer 6, which makes the Schottky diode more surge resistant.

[0047] Furthermore, this invention also proposes a method for fabricating the Schottky diode as described above; please refer to [reference needed]. Figure 4 This includes the following steps:

[0048] Step S10: Prepare a P-type ring region 9 on the upper side of the N-type epitaxial layer 2.

[0049] Specifically, firstly, a layer is deposited on the N-type epitaxial layer 2. The left and right silicon nitride layers 8 serve as barrier layers for silicon etching of trench 3, such as... Figure 4 As shown in (a). The preferred thickness of the silicon nitride layer 8 is... Left and right, of which, unit For Egypt, At the aforementioned thickness, the blocking effect is good.

[0050] Then, a first photolithography is performed on the upper side of silicon nitride layer 8 to etch out the ion implantation window, as shown below. Figure 4 As shown in (b). Further ion implantation is then performed. For N-type Schottky diodes, the ion source can be BF3, BCL3, etc., with an ion implantation energy between 30 kEV and 120 kEV, and an ion implantation dose of 10. 11 ~10 13 cm -2 between.

[0051] Finally, a rapid thermal annealing process is performed to form a P-type ring region 9 on the upper side of the N-type epitaxial layer 2, such as... Figure 4 As shown in (c). The rapid thermal annealing process is conducted at temperatures between 900℃ and 1150℃, ensuring low lateral diffusion in the P-ring region 9.

[0052] Step S20: Trench 3 is etched on the P-type ring region 9, and the remaining part of the P-type ring region 9 after etching forms a lightly doped P-type layer 6.

[0053] Specifically, trench 3 is etched on the P-type ring region 9, with silicon nitride layer 8 as an etching barrier layer. The etched trench 3 structure and the formed P-type lightly doped layer 6 are as follows: Figure 4 As shown in (d), the ion implantation window and the etching window are both formed by silicon nitride layer 8 as the ion implantation shielding layer and the etching barrier layer, respectively. Only the portion of the P-type ring region 9 remaining after being etched into the trench 3 is retained as the lightly doped P-type layer 6, which has a low doping concentration. In addition, to ensure the successful formation of the lightly doped P-type layer 6, the width of the P-type ring region 9 must be greater than the width of the trench 3.

[0054] Step S30: Prepare a gate oxide layer 4 in the trench 3, and then prepare a polycrystalline silicon layer 5.

[0055] Specifically, a gate oxide layer 4 is prepared within the trench 3. The thickness of the gate oxide layer 4 is determined by the device's breakdown voltage. Then, polysilicon deposition is performed, followed by reverse etching to remove the silicon nitride layer 8, forming a structure as shown in the image. Figure 4 As shown in (e), the top view is as follows: Figure 4 As shown in (f), the trench 3 contains a polysilicon layer 5 remaining after reverse etching.

[0056] Step S40: Prepare a P-type heavily doped layer 7 on the upper side of the N-type epitaxial layer 2, corresponding to the P-type lightly doped layer 6.

[0057] Specifically, step S40 includes: step S41, applying photoresist to the upper side of the N-type epitaxial layer 2, exposing and developing it, then performing ion implantation, removing the photoresist after implantation, and forming a P-type heavily doped layer 7.

[0058] More specifically, photoresist is applied to the upper side of the N-type epitaxial layer 2, exposed, and developed. P-type impurities are then ion-implanted using the photoresist as a barrier layer. The ion source can be BF3, BCL3, etc., with an ion implantation energy between 30 kEV and 60 kEV and an ion implantation dose of 10. 15 ~10 17 cm -2 Between these steps, the photoresist is removed, and finally ion implantation annealing is performed to form a heavily doped P-type layer 7. A top view is shown below. Figure 4 As shown in (g), the newly formed heavily doped P-type layer 7 and lightly doped P-type layer 6 are in... Figure 4 (g) is distributed in a trapezoidal shape, forming a trapezoidal structure.

[0059] Step S50: Prepare a barrier metal layer on the upper side of the p-type heavily doped layer 7.

[0060] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the patent protection scope of the present invention.

Claims

1. A Schottky diode, characterized by, The N-type epitaxial layer and the barrier metal layer are sequentially stacked from bottom to top, a trench extending along the front-back direction is formed on the upper side of the N-type epitaxial layer, a channel structure is filled in the trench, the channel structure comprises a gate oxide layer, two polysilicon layers located on both sides of the gate oxide layer, and two P-type lightly doped layers located on both sides of the two polysilicon layers, a P-type heavily doped layer connected with the P-type lightly doped layer is arranged on the upper side of the N-type epitaxial layer, and the P-type heavily doped layer is in contact with the barrier metal layer, the P-type heavily doped layer corresponds to the channel structure, and the two ends of the P-type heavily doped layer are respectively connected with the two P-type lightly doped layers of the channel structure, the channel structure is provided in plurality, the plurality of channel structures are arranged at intervals along the width direction of the channel structure, in any two adjacent channel structures, the P-type heavily doped layer is arranged between the two adjacent P-type lightly doped layers, and the two ends of the P-type heavily doped layer are respectively connected with the two P-type lightly doped layers, the P-type heavily doped layer is provided in plurality, the plurality of P-type heavily doped layers are arranged at intervals along the length direction of the channel structure, the plurality of P-type heavily doped layers are arranged at intervals along the width direction of the channel structure, and the P-type heavily doped layer and the P-type lightly doped layer are arranged in a trapezoidal structure along the length direction of the channel structure; The distance between the two adjacent P-type heavily doped layers and the front side of the N-type epitaxial layer is equal, or the distance between one of the two adjacent P-type heavily doped layers and the front side of the N-type epitaxial layer is greater than the distance between the other and the front side of the N-type epitaxial layer; The P-type heavily doped layer has a doping concentration of 10 11 ~10 13 cm -2 ; The junction depth of the P-type heavily doped layer is smaller than the junction depth of the P-type lightly doped layer.

2. A method of fabricating a Schottky diode as claimed in claim 1, characterized in that, The method comprises the following steps: Preparing a P-type ring region on the upper side of the N-type epitaxial layer; Etching a trench on the P-type ring region, and the P-type lightly doped layer is formed by the part of the P-type ring region left after etching; Preparing a gate oxide layer in the trench, and then preparing a polysilicon layer; Preparing a P-type heavily doped layer on the upper side of the N-type epitaxial layer corresponding to the P-type lightly doped layer; Preparing a barrier metal layer on the upper side of the P-type heavily doped layer.

3. The method of claim 2, wherein the metal layer is formed by a process selected from the group consisting of sputtering, evaporation, and plating. The step of preparing a P-type heavily doped layer on the upper side of the N-type epitaxial layer comprises: Smearing photoresist on the upper side of the N-type epitaxial layer, exposing and developing, then performing ion implantation, removing the photoresist after implantation, and forming a P-type heavily doped layer.

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