Method for converting binary digital signals into ternary analog signals and conversion circuit therefor

Abstract

The application provides a binary digital signal to balanced ternary analog signal conversion method and conversion circuit, a binary digital signal to balanced ternary analog signal conversion method, which comprises the following steps: detecting the bit number of a binary number corresponding to a binary digital signal, and recording the bit number as M; dividing the binary number from a low bit to a high bit into several conversion units with equal bit number, and recording the bit number of each conversion unit as N; reading the binary number of each conversion unit from a low bit to a high bit in sequence, and recording the reading number as K; converting the binary number of each conversion unit into a ternary number, and multiplying the ternary number by a decimal number 2 (N(K‑1)) corresponding to the ternary number; performing addition operation on the ternary number obtained in the step to obtain a ternary number corresponding to the original binary number; and converting the ternary number into an analog signal. The application has the beneficial effect that the binary digital signal is converted into a corresponding ternary analog signal, so that the binary digital signal drives a ternary chip.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing, and in particular to a method and circuit for converting binary digital signals to ternary analog signals. Background Technology

[0002] Programmable Josephson quantum voltage systems use Josephson chips as their core components. Their internal drive system, controlled by software, regulates the microwave frequency and current to generate the required voltage from the Josephson sub-junction array. A Josephson chip consists of an array of tens of thousands of Josephson junctions connected in series. Due to differences in manufacturing processes, Josephson chips are classified into two main types based on the number of sub-junctions: binary and ternary. Correspondingly, their drive systems are divided into binary chip drive systems and ternary chip drive systems. Currently developed binary chip drive systems transmit the binary signal of the Josephson junction array bias combination calculated by software to the binary chip drive module, which then outputs the generated drive current to the binary chip. Ternary chip drive systems transmit the ternary signal of the Josephson junction array bias combination calculated by software to the ternary chip drive module, which then outputs the generated drive current to the ternary chip. However, binary chip drive systems can only drive binary chips; the two different chip system modules are not interchangeable, lacking portability and flexibility.

[0003] Therefore, it is essential to provide a conversion method and circuit that can convert the binary signal of the Josephson array bias combination calculated by the software in the binary chip driver system into a ternary signal.

[0004] Balanced ternary, also known as symmetric ternary, is a ternary counting system with base 3 and bases -1 (hereinafter referred to as T), 0, and 1. Due to the introduction of -1, this system can directly represent negative numbers without additional signs. This makes balanced ternary more efficient than binary in addition, subtraction, and multiplication. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, the present invention aims to provide a conversion method and circuit for converting binary digital signals into ternary analog signals, which can convert multi-bit binary digital signals into ternary analog signals, thereby enabling the use of binary digital signals to drive ternary chip driver modules.

[0006] In view of this, the present invention provides a method for converting binary digital signals to balanced ternary analog signals, comprising the following steps:

[0007] The number of bits in the binary number corresponding to the binary digital signal is denoted as M;

[0008] Divide the binary number into several conversion units of equal number of bits from the least significant bit to the most significant bit. The number of bits in each conversion unit is denoted as N. If M is not an integer multiple of N, add 0s before the most significant bit to make M an integer multiple of N.

[0009] Read the binary number of each conversion unit sequentially from the least significant bit to the most significant bit, and record the number of reads as K;

[0010] Convert the binary number of each conversion unit to a ternary number and multiply it by the decimal number 2. (N(K-1)) The corresponding ternary number is used to obtain a ternary number containing the digit information of the binary number converted by each conversion unit in the complete binary number;

[0011] Add the ternary numbers containing digit information in all conversion units to obtain the ternary number corresponding to the binary digital signal;

[0012] The obtained ternary number is converted into an analog signal.

[0013] Furthermore, the ternary signal is represented by a two-bit binary number corresponding to a one-bit ternary number.

[0014] Furthermore, the correspondence between the two binary numbers and the one ternary number is as follows: the binary number "00" represents the ternary number "0"; the binary number "01" represents the ternary number "1"; and the binary number "11" represents the ternary number "T".

[0015] Furthermore, the method for converting the ternary number into the analog signal is as follows:

[0016] If the ternary number is "1", the analog signal output is a positive level signal;

[0017] If the ternary number is "0", the analog signal output is a zero-level signal;

[0018] If the ternary number is "T", then the analog signal output is a negative level signal.

[0019] Based on the above-mentioned objectives, the present invention also provides a conversion circuit for binary digital signals to balanced ternary analog signals, comprising:

[0020] The signal input terminal is used to input multi-bit binary digital signals.

[0021] A conversion module is used to convert binary digital signals into ternary signals. It includes several conversion units. The signal input terminal is electrically connected to the conversion module. The conversion unit is used to convert several bits in the binary digital signal into ternary signals. The ternary signals are represented in a way that two binary digital signals correspond to one ternary signal.

[0022] The multiplier generation module includes several multiplier units that are configured in a corresponding manner to the conversion unit. The multiplier units are configured based on the bit information of the binary digital signal processed by the corresponding conversion unit in the complete binary digital signal.

[0023] The multiplication module includes several multiplication units, which are used to perform ternary multiplication operations on the ternary signals output by the conversion unit and the corresponding ternary signals output by the multiplier unit.

[0024] The addition module includes several cascaded addition units, which are used to perform ternary addition on the ternary signals output by the multiplication unit and output the result in the form of a ternary signal.

[0025] The analog signal output module outputs the corresponding analog signal based on the ternary signal output from the addition module.

[0026] Furthermore, the conversion unit is used to convert a two-bit binary digital signal into a two-bit ternary signal.

[0027] Furthermore, the conversion unit used to process the lowest two bits of the binary digital signal is set as a basic conversion unit, and the output terminal of the basic unit is directly electrically connected to the input terminal of the addition module and the input terminal of the analog signal output module.

[0028] Furthermore, the multiplication unit includes a multiplier and a carry adder.

[0029] Furthermore, the addition unit includes an adder and a carry adder.

[0030] Furthermore, the analog signal output module includes a plurality of analog signal output units, each configured to convert a one-bit ternary signal represented by a two-bit binary signal into a ternary analog signal. The analog signal output unit includes:

[0031] The input terminal includes a first input terminal for inputting the lower bit of a two-bit binary signal and a second input terminal for inputting the higher bit of a two-bit binary signal;

[0032] The first transistor is an NPN type transistor;

[0033] The second transistor is a PNP type transistor;

[0034] The resistor includes: a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4;

[0035] The power supply includes a positive power supply VCC and a negative power supply VEE;

[0036] The output terminal is used to output a ternary analog signal;

[0037] In this configuration, the base of the first transistor is electrically connected to the second input terminal, the collector of the first transistor is electrically connected to the positive power supply VCC through the first resistor R1, the emitter of the first transistor is grounded through the second resistor R2, the base of the second transistor is electrically connected to the first input terminal through the third resistor R3, the emitter of the second transistor is electrically connected to the collector of the first transistor, the collector of the second transistor is electrically connected to the negative power supply VEE through the first resistor R4, and the collector of the second transistor is electrically connected to the output terminal.

[0038] Compared with the prior art, the beneficial effects of the present invention are as follows: The binary digital signal to ternary analog signal conversion method and its conversion circuit provided by the present invention can convert binary digital signals into corresponding ternary analog signals. The ternary analog signals include three level states, namely positive level, zero level and negative level. The ternary analog signals are used to drive ternary chips, thereby realizing the binary digital signals driving ternary chips. Attached Figure Description

[0039] Figure 1 This is a flowchart of the conversion method according to an embodiment of the present invention.

[0040] Figure 2 This is a block diagram of the conversion circuit according to an embodiment of the present invention.

[0041] Figure 3 This is a circuit diagram of the conversion unit according to an embodiment of the present invention.

[0042] Figure 4 This is a circuit diagram of a multiplier for two one-bit ternary signals according to an embodiment of the present invention.

[0043] Figure 5 This is a circuit diagram of an adder for two one-bit ternary signals according to an embodiment of the present invention.

[0044] Figure 6 This is a circuit diagram of the analog signal output unit according to an embodiment of the present invention.

[0045] Figure 7 This is a schematic diagram illustrating an application scenario of an embodiment of the present invention. Detailed Implementation

[0046] To enable readers to better understand the design intent of this invention, the following specific embodiments are provided to allow readers to vividly understand the structure, structural composition, working principle, and technical effects involved in this invention. However, it should be noted that the following embodiments are not intended to limit the technical solutions of this invention. Those skilled in the art, while analyzing and understanding the embodiments, can make a series of modifications and equivalent substitutions to the technical solutions provided by this invention in conjunction with existing knowledge. New technical solutions obtained through such modifications and equivalent substitutions are also included in this invention.

[0047] like Figure 1 As shown, a method for converting a binary digital signal to a balanced ternary analog signal includes the following steps:

[0048] The number of bits in the binary number corresponding to the binary digital signal is denoted as M;

[0049] Divide the binary number into several conversion units of equal number of bits from the least significant bit to the most significant bit. The number of bits in each conversion unit is denoted as N. If M is not an integer multiple of N, add 0s before the most significant bit to make M an integer multiple of N.

[0050] Read the binary number of each conversion unit sequentially from the least significant bit to the most significant bit, and record the number of reads as K;

[0051] Convert the binary number of each conversion unit to a ternary number and multiply it by the decimal number 2. (N(K-1)) The corresponding ternary number is used to obtain a ternary number containing the digit information of the binary number converted by each conversion unit in the complete binary number;

[0052] Add the ternary numbers containing digit information in all conversion units to obtain the ternary number corresponding to the original binary digital signal;

[0053] The obtained ternary number is converted into an analog signal.

[0054] In one implementation, the ternary signal is represented by a two-bit binary number corresponding to a one-bit ternary number. The correspondence between the two binary numbers and the one ternary number is as follows: the binary number "00" represents the ternary number "0"; the binary number "01" represents the ternary number "1"; and the binary number "11" represents the ternary number "T" (T represents the decimal number -1).

[0055] As one implementation method, using two binary digits as a conversion unit, the input-output correspondence of the conversion unit is shown in the table below:

[0056]

[0057] The output of four binary numbers corresponds to two ternary numbers. Specifically, the binary number "0000" corresponds to the ternary number "00", the binary number "0001" corresponds to the ternary number "01", the binary number "0111" corresponds to the ternary number "1T", and the binary number "0100" corresponds to the ternary number "10".

[0058] As one implementation, the conversion method for the ternary number to the analog signal is as follows: if the ternary number is "1", the analog signal output is a positive level signal; if the ternary number is "0", the analog signal output is a zero level signal; if the ternary number is "T", the analog signal output is a negative level signal. Because the ternary signal is represented by two binary digits in this method, if the two binary digits are "01", the analog signal output is a positive level signal; if the two binary digits are "00", the analog signal output is a zero level signal; and if the two binary digits are "11", the analog signal output is a negative level signal.

[0059] As one implementation method, the multiplication rule for ternary numbers in the above method is: "0*0=0", "0*1=0", "0*T=0", "1*1=1", "1*T=T", "T*T=1"; the addition rule for ternary numbers is: "0+0=0", "0+1=1", "0+T=T", "1+1=1T", "1+T=0", "T+T=T1", where "1T" represents a carry of 1 and "T1" represents a carry of T.

[0060] like Figure 2 As shown, a binary digital signal to balanced ternary analog signal conversion circuit includes: a signal input terminal, a conversion module, a multiplier generation module, a multiplication operation module, an addition operation module, and an analog signal output module.

[0061] The signal input terminal is used to input multi-bit binary digital signals.

[0062] The conversion module is used to convert binary digital signals into ternary signals. It includes several conversion units, and the circuit diagram of the conversion unit is shown below. Figure 3 As shown, the signal input terminal is electrically connected to the conversion module. The conversion unit is used to convert several bits in the binary digital signal into a ternary signal. The ternary signal is represented by a two-bit binary digital signal corresponding to a one-bit ternary signal.

[0063] The multiplier generation module includes several multiplier units corresponding to the conversion unit. The multiplier units are set based on the bit information of the binary digital signal processed by the corresponding conversion unit in the complete binary digital signal. Since the binary digital signal processed by each conversion unit is a portion of the value extracted from the complete binary digital signal, in order to make the sum of the extracted binary digital signals equal to the value of the complete binary digital signal, it is necessary to set the multiplier units according to the bit information of the binary digital signal processed by the conversion unit in the complete binary digital signal. The value represented by the binary number processed by the conversion unit in the original binary number can only be obtained by multiplying the binary number processed by the conversion unit with the value of the corresponding multiplier unit.

[0064] The multiplication module includes several multiplication units, which are used to perform ternary multiplication operations on the ternary signals output by the conversion unit and the corresponding ternary signals output by the multiplier unit. Each multiplication unit includes a multiplier and a carry-adder. The rules for ternary multiplication are: "0*0=0", "0*1=0", "0*T=0", "1*1=1", "1*T=T", and "T*T=1".

[0065] The addition module includes several cascaded addition units. Each addition unit performs ternary addition on the ternary signals output by the multiplication unit and outputs the result in ternary form. The rules for ternary addition are: "0+0=0", "0+1=1", "0+T=T", "1+1=1T", "1+T=0", and "T+T=T1", where "1T" indicates a carry of 1 and "T1" indicates a carry of T.

[0066] As one implementation method, the multiplier circuit is as follows: Figure 4 As shown in the table below, the input-output relationship of the multiplier circuit is as follows:

[0067]

[0068] As one implementation method, the adder circuit is as follows: Figure 5 As shown in the table below, the input-output relationship of the adder circuit is as follows:

[0069]

[0070]

[0071] The analog signal output module outputs the corresponding analog signal based on the ternary signal output from the addition module. The input-output relationship of the analog signal output module is as follows:

[0072] G-IN11 G-IN12 G-OUT 0 0 Zero level 0 1 Positive level 1 1 negative level

[0073] G-IN11 and G-IN12 correspond to the high and low bits of a single binary number using two binary digits.

[0074] In one implementation, the conversion unit converts a two-bit binary digital signal into a two-bit ternary signal. The conversion unit that processes the least significant two bits of the binary digital signal is designated as a basic conversion unit. The output of the basic unit is directly electrically connected to the input of the addition module and the input of the analog signal output module. Because the value of the multiplier unit corresponding to the least significant bit is 1, the multiplier unit and multiplication unit can be omitted.

[0075] like Figure 6 As shown, the analog signal output module includes several analog signal output units, each configured to convert a one-bit ternary signal represented by a two-bit binary signal into a ternary analog signal. The analog signal output unit includes:

[0076] The input terminal includes a first input terminal for inputting the lower bit of a two-bit binary signal and a second input terminal for inputting the higher bit of a two-bit binary signal;

[0077] The first transistor is an NPN type transistor;

[0078] The second transistor is a PNP type transistor;

[0079] The resistor includes: a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4;

[0080] The power supply includes a positive power supply VCC and a negative power supply VEE;

[0081] The output terminal is used to output a ternary analog signal;

[0082] In this configuration, the base of the first transistor is electrically connected to the second input terminal, the collector of the first transistor is electrically connected to the positive power supply VCC through the first resistor R1, the emitter of the first transistor is grounded through the second resistor R2, the base of the second transistor is electrically connected to the first input terminal through the third resistor R3, the emitter of the second transistor is electrically connected to the collector of the first transistor, the collector of the second transistor is electrically connected to the negative power supply VEE through the first resistor R4, and the collector of the second transistor is electrically connected to the output terminal.

[0083] The invention will be further illustrated below using the binary number "011001" corresponding to a 6-bit binary digital signal at a certain moment as an example:

[0084] The binary number 011001 is divided into three conversion units with two bits as each conversion unit. From the least significant bit to the most significant bit, the conversion units are "01", "10", and "01". The two least significant bits of the binary number "01" are directly converted into the corresponding ternary number "01" by the conversion unit.

[0085] The third and fourth digits of the binary number, "10", are converted to the corresponding ternary number "1T" by the conversion unit. The first multiplier unit is the ternary number corresponding to the decimal number 4, which is the ternary number "11". The ternary number "1T" obtained from the conversion unit and the ternary number "11" output by the first multiplier unit are multiplied by the multiplication unit to obtain the ternary number "010T" (1T + 1T0 = 10T). That is, the output of the multiplication unit is the ternary number "010T". After passing through the two carry adders of the addition unit (adding the lowest two digits "01" obtained from the conversion unit to the ternary number "010T" output by the multiplication unit), the ternary number "0100" is obtained.

[0086] The fifth and sixth bits of the binary number, "01", are converted to their corresponding ternary "01" by the conversion unit. The second multiplier unit is set to the ternary number corresponding to the decimal number 16, i.e., the ternary number "1TT1". The ternary "01" obtained from the conversion unit and the ternary number "1TT1" output by the second multiplier unit are then multiplied by the multiplication unit to obtain the ternary number "1TT1". After being added by the addition unit (adding the lower four bits "0100" obtained from the conversion unit to the ternary number "1TT1" output by the multiplication unit), the ternary number "10T1" is obtained.

[0087] The ternary number "10T1" is converted into a corresponding analog signal through a signal conversion circuit. The analog signal is in the following order from high to low: positive level, zero level, negative level, and positive level.

[0088] In summary, the binary digital signal to ternary analog signal conversion method and its conversion circuit provided by this invention can convert binary digital signals into corresponding ternary analog signals. The ternary analog signals include three level states: positive level, zero level, and negative level. The ternary analog signals are used to drive ternary chips, thereby realizing the driving of ternary chips by binary digital signals.

[0089] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. The accompanying drawings corresponding to the specific embodiments are provided as an aid to understanding, enabling the reader to fully grasp the abstract higher-level concepts involved in this method by understanding the concrete and visual lower-level concepts. When understanding this method as a whole and comparing it with other technical solutions besides those provided by this method, the appearance of the drawings should not be taken as the sole reference. Furthermore, after understanding the concept of this method, all modifications, equivalent substitutions, merging of feature elements, deletion and recombination of unnecessary technical feature elements, and reasonable addition and recombination of common unnecessary technical feature elements in the prior art, made according to or without reference to the drawings, should be understood as being encompassed within the spirit of this method.

Claims

1. A circuit for converting binary digital signals to balanced ternary analog signals, characterized in that, include: The signal input terminal is used to input a multi-bit binary digital signal, wherein the number of bits of the multi-bit binary digital signal is denoted as M; A conversion module is used to convert binary digital signals into ternary signals. It includes several conversion units. The signal input terminal is electrically connected to the conversion module. The conversion unit is used to convert several bits in the binary digital signal into ternary signals. The ternary signals are represented by two binary digital signals corresponding to one ternary signal. The conversion unit is obtained by dividing the binary number into equal parts from the least significant bit to the most significant bit. The number of bits in each conversion unit is denoted as N. If M is not equal to an integer multiple of N, zeros are padded before the most significant bit to make M equal to an integer multiple of N. The multiplier generation module includes several multiplier units corresponding to the conversion unit. Each multiplier unit is configured based on the bit information of the binary digital signal processed by the corresponding conversion unit within the complete binary digital signal. The multiplier unit is configured as a decimal number 2. (N(K-1)) The corresponding ternary number, K is the number of times the binary number of each conversion unit is read sequentially from the least significant bit to the most significant bit; The multiplication module includes several multiplication units, which are used to perform ternary multiplication on the ternary signal output by the conversion unit and the ternary signal output by the corresponding multiplier unit to obtain a ternary number containing the digit information of the binary number converted by each conversion unit in the complete binary number. The addition module includes several cascaded addition units, which are used to perform ternary addition on the ternary signals output by the multiplication unit and output the result in the form of a ternary signal. The analog signal output module outputs the corresponding analog signal based on the ternary signal output from the addition module.

2. The binary digital signal to balanced ternary analog signal conversion circuit according to claim 1, characterized in that, The conversion unit is used to convert a two-bit binary digital signal into a two-bit ternary signal.

3. The binary digital signal to balanced ternary analog signal conversion circuit according to claim 2, characterized in that, The conversion unit used to process the lowest two bits of the binary digital signal is designated as the basic conversion unit. The output of the basic unit is directly electrically connected to the input of the addition module and the input of the analog signal output module.

4. The binary digital signal to balanced ternary analog signal conversion circuit according to claim 1, characterized in that, The multiplication unit includes a multiplier and a carry adder.

5. The binary digital signal to balanced ternary analog signal conversion circuit according to claim 1, characterized in that, The addition unit includes an adder and a carry adder.

6. The binary digital signal to balanced ternary analog signal conversion circuit according to claim 1, characterized in that, The analog signal output module includes several analog signal output units, each configured to convert a one-bit ternary signal represented by a two-bit binary signal into a ternary analog signal. The analog signal output unit includes: The input terminal includes a first input terminal for inputting the lower bit of a two-bit binary signal and a second input terminal for inputting the higher bit of a two-bit binary signal; The first transistor is an NPN type transistor; The second transistor is a PNP type transistor; The resistor includes: a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; The power supply includes a positive power supply VCC and a negative power supply VEE; The output terminal is used to output a ternary analog signal; In this configuration, the base of the first transistor is electrically connected to the second input terminal, the collector of the first transistor is electrically connected to the positive power supply VCC through the first resistor R1, the emitter of the first transistor is grounded through the second resistor R2, the base of the second transistor is electrically connected to the first input terminal through the third resistor R3, the emitter of the second transistor is electrically connected to the collector of the first transistor, the collector of the second transistor is electrically connected to the negative power supply VEE through the first resistor R4, and the collector of the second transistor is electrically connected to the output terminal.

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