Signal processing method, device, system and storage medium for display device

Abstract

The present invention discloses a signal processing method, device, system and storage medium for a display device, wherein the method comprises: a mainboard chip acquires a control signal, performs a first encoding on the control signal, and obtains multiple groups of first parallel signals; a signal output chip performs a second encoding on multiple groups of the first parallel signals, and obtains compressed signals; a signal receiving chip decodes the compressed signal, and obtains multiple groups of second parallel signals; a logic board chip performs a third encoding on multiple groups of the second parallel signals, and obtains display signals, and transmits the display signals to a display screen. The present application simplifies the wiring process during the transmission process by compressing and then decompressing the parallel signal during the signal transmission process.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to a signal processing method, device, system and storage medium for a display device. Background Art

[0002] At present, display technology is constantly developing and innovating, and high-definition displays have entered the lives of more and more people. In order to cater to people's visual experience, high-end display screens continue to pursue high resolution and high refresh rate. According to the current industry standards, from a technical point of view, as long as the screen resolution can reach 720P or above, it can be called a high-definition display. With the continuous upgrading of technology, the resolution of the display can reach 2K, 4K, and even 8K. The so-called 4K ultra-high-definition TV refers to a TV with a resolution of 3840×2160, while 8K ultra-high-definition TV refers to a TV with a resolution of 7680×4320. It can be seen that the resolution of 8K ultra-high-definition TV is 4 times that of 4K ultra-high-definition TV, that is, it is doubled in both horizontal and vertical directions. The data volume of 8K display is four times that of 4K display. At the same time, the refresh rate of 8K display screens is generally configured at 120 Hz, which is twice as high as the 60 Hz refresh rate of traditional display screens. Therefore, the main signal format used by the display screen motherboard connected to the display screen logic driver board is the mainstream V-by-One HS signal format, and its maximum signal transmission speed can reach 3.75 switching bandwidths (Gbps).

[0003] However, even with this signal transmission, an 8K 120HZ display screen still requires at least 128 signal lines for transmission. These display differential pair wiring and sockets greatly occupy the area on the display screen's motherboard, increasing the material cost of the wiring and the workload of signal testing, resulting in a very complicated wiring process for the display device.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a signal processing method, device, system and storage medium for a display device, aiming to solve the problem that too many wires are required for data transmission in a display device, resulting in a complicated wiring process.

[0006] The technical solution of the present invention is as follows:

[0007] A signal processing method for a display device, comprising: a mainboard chip acquires a control signal, performs a first encoding on the control signal, and obtains multiple groups of first parallel signals; a signal output chip performs a second encoding on the multiple groups of the first parallel signals, and obtains compressed signals; a signal receiving chip decodes the compressed signal, and obtains multiple groups of second parallel signals; a logic board chip performs a third encoding on the multiple groups of the second parallel signals, and obtains display signals, and transmits the display signals to a display screen.

[0008] In the signal processing method of the display device, the decoding method of the second parallel signal is the reverse encoding method of the second encoding.

[0009] The signal processing method for the display device, wherein the signal output chip performs a second encoding on the plurality of groups of the first parallel signals to obtain a compressed signal, specifically comprises:

[0010] The signal output chip divides the first parallel signal into blocks according to a first preset time interval to obtain a plurality of first parallel signal sub-blocks;

[0011] Merging all of the first parallel signal sub-blocks in the same time period to obtain a first compressed signal sub-block;

[0012] Arrange all of the first compressed signal sub-blocks in time sequence to obtain a compressed signal.

[0013] The signal processing method for the display device, wherein the signal receiving chip decodes the compressed signal to obtain a plurality of groups of second parallel signals, specifically comprises:

[0014] The signal receiving chip divides the compressed signal into blocks according to a second preset time interval to obtain second compressed signal sub-blocks;

[0015] Decoding the second compressed signal sub-block to obtain a plurality of second signal sub-blocks within the same time interval;

[0016] All of the second signal sub-blocks are arranged in time sequence to obtain multiple groups of second parallel signals.

[0017] The signal processing method for the display device, wherein the first preset time interval is equal to the second preset time interval.

[0018] The present application also discloses a signal processing device for a display device, which includes a mainboard chip, a signal output chip, a transmission cable, a signal receiving chip and a logic board chip, wherein the mainboard chip is used to receive a control signal, encode the control signal for the first time, process it into multiple groups of first parallel signals, and output multiple groups of first parallel signals; the signal output chip is electrically connected to the mainboard chip, used to receive the first parallel signal and encode the multiple groups of the first parallel signals for the second time, process them into a group of compressed signals, and output the compressed signals; the transmission cable is connected to the signal output chip, used to transmit the compressed signal; the signal receiving chip is connected to the transmission cable, used to receive the compressed signal and decode the compressed signal, process it into multiple groups of second parallel signals, and output multiple groups of second parallel signals; the logic board chip is electrically connected to the signal receiving chip, used to receive multiple groups of the second parallel signals, encode the second parallel signals for the third time, process them into display signals, and output the display signals to a display screen.

[0019] The signal processing device of the display device, wherein the transmission cable includes at least one of a compression rate electronic cable or an optical fiber.

[0020] The signal processing device of the display device, wherein the main board chip and the signal output chip are arranged on the same printed circuit board, and the main board chip and the signal output chip are connected through a first printed circuit; and / or the logic board chip and the signal receiving chip are arranged on the same printed circuit board, and the logic board chip and the signal receiving chip are connected through a second printed circuit.

[0021] The present application also discloses a signal processing system for a display device, which is characterized by comprising:

[0022] A receiving module, used for receiving a control signal and first encoding to obtain multiple groups of parallel signals;

[0023] A compression module, used for encoding the multiple groups of parallel signals for a second time to obtain compressed signals;

[0024] A decompression module, used for decoding the compressed signal to obtain multiple sets of parallel signals;

[0025] The sending module is used for encoding the multiple groups of parallel signals for the third time to obtain display signals, and sending the display signals.

[0026] The present application also discloses a storage medium, characterized in that the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps in the signal processing method of the display device as described above.

[0027] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0028] In the signal processing method disclosed in the present application, after receiving the control signal, the mainboard chip encodes the first parallel signal, and then does not directly transmit the first parallel signal to the logic board chip, but encodes the second time through the signal output chip, converting the original low-speed multiple groups of parallel signals into fewer high-speed compressed signals for transmission, thereby reducing the number of transmission lines required during the transmission process; the signals are decoded into multiple groups of second parallel signals on the signal receiving chip, and then encoded for the third time on the logic board to obtain display signals, thereby completing signal transmission; during the transmission process, the number of connections on the display signal hardware can be greatly reduced, the number of wires can be reduced, and the number of sockets can be reduced accordingly, and at the same time, during the signal regulation and detection process, the reduction in the number of transmitted signals makes testing and control more convenient; in short, the wiring process is simpler, and the reliability of the connection is higher than that of the previous multi-socket form. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 is a flow chart of a signal processing method of a display device in the present invention;

[0031] Figure 2 A schematic diagram of the working process of the signal output chip of the display device in the present invention;

[0032] Figure 3 It is a structural schematic diagram of a signal processing device of a display device in the present invention;

[0033] Figure 4 It is a schematic diagram of the structure of the signal processing system of the display device in the present invention.

[0034] Among them, 10, main board chip; 20, signal output chip; 30, transmission cable; 40, signal receiving chip; 50, logic board chip; 100, receiving module; 200, compression module; 300, decompression module; 400, sending module. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] In the prior art, the signal control structure of the display screen mainly includes two parts: a main board and a logic driver board, which are connected by electronic cables. As the performance requirements of the display screen become higher and higher, the number of components and cables loaded inside the product increases, and the requirements for the wiring process itself are very high. The emergence of 8K display screens further increases the requirements for the number of wiring in display products.

[0037] See also Figure 1 In one embodiment of the present invention, a signal processing method for a display device is disclosed, which includes:

[0038] S100, the mainboard chip obtains a control signal, and performs a first encoding on the control signal to obtain multiple groups of first parallel signals;

[0039] S200, the signal output chip performs a second encoding on the plurality of groups of the first parallel signals to obtain compressed signals;

[0040] S300, the signal receiving chip decodes the compressed signal to obtain multiple groups of second parallel signals;

[0041] S400 , the logic board chip encodes the plurality of groups of the second parallel signals for a third time to obtain display signals, and transmits the display signals to a display screen.

[0042] In the signal processing method disclosed in the present embodiment, the control signal is generally sent by a mobile terminal such as a remote control, a mobile phone, and a computer. After receiving the control signal, the mainboard chip encodes it for the first time to obtain a first parallel signal, and then does not directly transmit the first parallel signal to the logic board chip, but encodes it for the second time through the signal output chip, converting the original low-speed multiple groups of parallel signals into fewer high-speed compressed signals for transmission, thereby reducing the number of transmission lines required during the transmission process; the signal is decoded into multiple groups of second parallel signals on the signal receiving chip, and then encoded for the third time on the logic board to obtain a display signal, thereby completing the signal transmission; during the transmission process, the connection of the display signal hardware can be greatly reduced, the number of wires can be reduced, and the number of sockets can be reduced accordingly. At the same time, in the process of signal regulation and detection, the reduction in the number of transmitted signals makes it easier to test and control; in short, the wiring process is simpler, and the reliability of the connection is higher than that of the previous multi-socket form.

[0043] In this embodiment, since the multiple groups of first parallel signals output by the mainboard chip are essentially different from other serial signals, the complexity of signal transmission during the transmission process is small, and they are signals that do not interfere with each other and are transmitted in the same time period. Therefore, no confusion will occur when multiple signal segments are compressed during the second encoding process, and there is no need to worry about signal processing issues. There is no need to reorder the decoded signal segments when decoding on the signal receiving chip. In other words, the signal processing burden on the signal output chip and the signal receiving chip will not be increased too much during the signal transmission process, and thus no large delay will be generated. A large amount of display data can be transmitted in a concise, accurate, and fast manner.

[0044] Specifically, as an implementation method of this embodiment, the decoding method of the second parallel signal is disclosed as the reverse encoding method of the second encoding. In this embodiment, a coding method is used to compress and decompress multiple groups of first parallel signals, and the first parallel signals are compressed and encoded into compressed signals on the signal output chip; the compressed signals are decoded into second parallel signals on the signal receiving chip; only one coding method is used to process the signal, so that the first parallel signal output on the mainboard chip and the second parallel signal received on the logic board chip can be consistent, with no difference in specifications, and the data before decompression can be better restored to avoid signal loss.

[0045] See also Figure 2 Specifically, as another implementation of this embodiment, step S200 is disclosed, which specifically includes:

[0046] S210: The signal output chip divides the first parallel signal into blocks according to a first preset time interval to obtain a plurality of first parallel signal sub-blocks;

[0047] S220, merging all of the first parallel signal sub-blocks in the same time period to obtain a first compressed signal sub-block;

[0048] S230. Arrange all of the first compressed signal sub-blocks in chronological order to obtain a compressed signal.

[0049] In this embodiment, because the display signal is a relatively special signal, it is a unidirectional parallel signal for the television system, and the content is mainly a color data signal. During the transmission process, the pairs of color data signals are parallel signals; therefore, when the transmission information of the high-speed signal is re-encoded after passing through the signal output chip, only the first parallel signal sub-blocks of different groups in the same time interval are compressed and processed, and no sequence transmission is adopted. Therefore, the image information transmitted in the same time is consistent with that before the conversion. This method can maximize the integrity and real-time nature of signal transmission, and ensure that the display delay is within an acceptable range in terms of signal transmission.

[0050] Specifically, as another implementation of this embodiment, step S300 is disclosed, which specifically includes:

[0051] S310, the signal receiving chip divides the compressed signal into blocks according to a second preset time interval to obtain second compressed signal sub-blocks;

[0052] S320, decoding the second compressed signal sub-block to obtain multiple second signal sub-blocks within the same time interval;

[0053] S330. Arrange all of the second signal sub-blocks in time sequence to obtain multiple groups of second parallel signals.

[0054] In the present embodiment, the method for processing the compressed signal according to the second preset time interval encodes the compressed signal into a second parallel signal in order. The decompression encoding method is the same as the encoding method for compressing the first parallel signal, but both are processed in blocks according to a certain time interval. First, after blocking, the fragmented signal sub-blocks are easier to compress and decompress without being damaged; second, the workload of continuing to compress and decompress after blocking is small, and the processing requirements for the signal output chip and the signal receiving chip are low, and it is easy to implement.

[0055] Moreover, in this embodiment, the first preset time interval can be set equal to the second preset time interval, so that the decompressed second parallel signal can better restore the first parallel signal output by the mainboard chip, which is convenient for the logic board chip to identify.

[0056] See also Figure 3 As another embodiment of the present application, a signal processing device for a display device is disclosed, which includes a mainboard chip 10, a signal output chip 20, a transmission cable 30, a signal receiving chip 40 and a logic board chip 50. The mainboard chip 10 is used to receive a control signal, encode the control signal for the first time, process it into multiple groups of first parallel signals, and output multiple groups of first parallel signals; the signal output chip 20 is electrically connected to the mainboard chip 10, and is used to receive the first parallel signal and encode multiple groups of the first parallel signals for the second time, process them into a group of compressed signals, and output the compressed signals; the transmission cable 30 is connected to the signal output chip 20, and is used to transmit the compressed signal; the signal receiving chip 40 is connected to the transmission cable 30, and is used to receive the compressed signal and decode the compressed signal, process it into multiple groups of second parallel signals, and output multiple groups of the second parallel signals; the logic board chip 50 is electrically connected to the signal receiving chip 40, and is used to receive multiple groups of the second parallel signals, encode the second parallel signals for the third time, process them into display signals, and output the display signals to the display screen.

[0057] The signal processing device disclosed in this embodiment is wirelessly connected to a mobile phone, a computer, a remote controller, etc. through a mainboard chip 10, such as a WiFi connection, a Bluetooth connection, an infrared connection, etc., and then obtains a control signal; the control signal is used to control the display state of the display device, including power on, power off, standby, adjusting the image mode, etc. The output end of the mainboard chip 10 is connected to the signal output chip 20, and then the output end of the signal output chip 20 is connected to the input end of the signal receiving chip 40 through a transmission cable 30, and the signal is transmitted from one end of the transmission cable 30 to the other end by a compression and decompression method. On the basis of the code, the original parallel transmission lines are merged and converted into a higher-speed signal transmission method. The transmission rate of the compressed signal can be increased by 3-4 times compared with the transmission rate of the first parallel signal, and the transmission cable 30 can be reduced by 3-4 times accordingly, thereby saving material costs and reducing the space occupied by the transmission cable 30 in the signal processing device, which is convenient for the design of the routing process; the signal receiving chip 40 decompresses the compressed signal to obtain the second parallel signal, which can be directly encoded and output after being transmitted to the logic board chip 50. There is no need to make improvements on the logic board chip 50, reducing the workload of software design.

[0058] Specifically, as an implementation mode of this embodiment, plugs are provided at both ends of the transmission cable 30, and sockets adapted to the plugs are provided on the signal output chip 20 and the signal receiving chip 40. The electrical connection between the transmission cable 30 and the signal output chip 20 and the signal receiving chip 40 can be quickly and conveniently achieved through the plugging of the plug and the socket, and the plugging method is also convenient for disassembly, and it is convenient to separate the main board and the logic board when maintenance or replacement is required.

[0059] Specifically, as an implementation of this embodiment, the transmission cable 30 is disclosed to include at least one of a compression rate electronic cable or an optical fiber. The transmission speeds of the compression rate electronic cable and the optical fiber are very fast, so the transmission time of the signal in the transmission cable 30 can be reduced, the response time of the signal processing device can be shortened, and a high-speed transmission mode of the display device can be realized.

[0060] Specifically, as another implementation of this embodiment, the mainboard chip 10 and the signal output chip 20 are provided on the same printed circuit board, and the mainboard chip 10 and the signal output chip 20 are connected through a first printed circuit. First, the positions of the mainboard chip 10 and the signal output chip 20 fixed on the same printed circuit board are fixed, and can remain stable during use; second, the mainboard chip 10 and the signal output chip 20 are connected through the first printed circuit, and the mainboard chip 10 and the signal output chip 20 are respectively welded at both ends of the first printed circuit, and the circuit connection is stable, and it is not easy to cause a circuit break during use; third, the first printed circuit replaces the circuit routing, which can save costs, reduce the use of connectors, and reduce the occupied space.

[0061] Similarly, in another implementation of this embodiment, the logic board chip 50 and the signal receiving chip 40 are disposed on the same printed circuit board, and the logic board chip 50 and the signal receiving chip 40 are connected via a second printed circuit. In this embodiment, by providing the second printed circuit, the occupied space can be reduced, the electrical connection can be stabilized, and the production cost can be saved, just like providing the first printed circuit.

[0062] See also Figure 4 As another embodiment of the present application, a signal processing system for a display device is disclosed, characterized in that it includes:

[0063] A receiving module 100 is used to receive a control signal and obtain multiple groups of parallel signals through first encoding;

[0064] A compression module 200, used for encoding the plurality of parallel signals for a second time to obtain a compressed signal;

[0065] A decompression module 300, used for decoding the compressed signal to obtain multiple groups of parallel signals;

[0066] The sending module 400 is used to encode the multiple groups of parallel signals for the third time to obtain a display signal, and send the display signal.

[0067] As another embodiment of the present application, a storage medium is disclosed, characterized in that the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps in the signal processing method of the display device as described above.

[0068] In summary, the present application discloses a signal processing method for a display device, which includes:

[0069] S100, the mainboard chip obtains a control signal, and performs a first encoding on the control signal to obtain multiple groups of first parallel signals;

[0070] S200, the signal output chip performs a second encoding on the plurality of groups of the first parallel signals to obtain compressed signals;

[0071] S300, the signal receiving chip decodes the compressed signal to obtain multiple groups of second parallel signals;

[0072] S400 , the logic board chip encodes the plurality of groups of the second parallel signals for a third time to obtain display signals, and transmits the display signals to a display screen.

[0073] In the signal processing method disclosed in the present embodiment, the control signal is generally sent by a mobile terminal such as a remote control, a mobile phone, and a computer. After receiving the control signal, the mainboard chip encodes it for the first time to obtain a first parallel signal, and then does not directly transmit the first parallel signal to the logic board chip, but encodes it for the second time through the signal output chip, converting the original low-speed multiple groups of parallel signals into fewer high-speed compressed signals for transmission, thereby reducing the number of transmission lines required during the transmission process; the signal is decoded into multiple groups of second parallel signals on the signal receiving chip, and then encoded for the third time on the logic board to obtain a display signal, thereby completing the signal transmission; during the transmission process, the connection of the display signal hardware can be greatly reduced, the number of wires can be reduced, and the number of sockets can be reduced accordingly. At the same time, in the process of signal regulation and detection, the reduction in the number of transmitted signals makes it easier to test and control; in short, the wiring process is simpler, and the reliability of the connection is higher than that of the previous multi-socket form.

[0074] In this embodiment, the parallel signal processing method is used to reduce the hardware requirements for the transmission wires. Without making major changes, less wires can be used to transmit signals farther. In some special TV designs, such as split TVs, only very little signal transmission is performed, which can meet the simplicity and beauty of the overall design. In a large number of scenarios, such as the future 8K 120HZ large-size and high-resolution display screen application scenarios, there is a simpler hardware connection.

[0075] It should be noted that the present invention takes the signal processing method and device of an 8K display screen as an example to introduce the specific structure and working principle of the present invention, but the application of the present invention is not limited to 8K display screens, and can also be applied to the production and use of other similar workpieces.

[0076] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0077] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A signal processing method for a display device, characterized in that: include: The mainboard chip obtains the control signal, performs a first encoding on the control signal, and obtains a plurality of groups of first parallel signals; The signal output chip performs a second encoding on the plurality of groups of the first parallel signals to obtain compressed signals; The signal receiving chip decodes the compressed signal to obtain multiple groups of second parallel signals; The logic board chip performs a third encoding on the plurality of groups of the second parallel signals to obtain display signals, and transmits the display signals to the display screen; The signal output chip performs a second encoding on the plurality of groups of the first parallel signals to obtain a compressed signal, specifically comprising: The signal output chip divides the first parallel signal into blocks according to a first preset time interval to obtain a plurality of first parallel signal sub-blocks; Merging all of the first parallel signal sub-blocks in the same time period to obtain a first compressed signal sub-block; Arrange all of the first compressed signal sub-blocks in time sequence to obtain a compressed signal.

2. The signal processing method of a display device according to claim 1, characterized in that: The decoding method of the second parallel signal is the reverse encoding method of the second encoding.

3. The signal processing method of a display device according to claim 1, characterized in that: The signal receiving chip decodes the compressed signal to obtain multiple groups of second parallel signals, specifically comprising: The signal receiving chip divides the compressed signal into blocks according to a second preset time interval to obtain second compressed signal sub-blocks; Decoding the second compressed signal sub-block to obtain a plurality of second signal sub-blocks within the same time interval; All of the second signal sub-blocks are arranged in time sequence to obtain multiple groups of second parallel signals.

4. The signal processing method of a display device according to claim 3, characterized in that: The first preset time interval is equal to the second preset time interval.

5. A signal processing device for a display device, characterized in that: include: A mainboard chip, used for receiving a control signal, performing a first encoding on the control signal, processing the control signal into a plurality of groups of first parallel signals, and outputting the plurality of groups of first parallel signals; A signal output chip, electrically connected to the mainboard chip, for receiving the first parallel signal, performing a second encoding on a plurality of groups of the first parallel signals, processing the plurality of groups of the first parallel signals into a group of compressed signals, and outputting the compressed signals; A transmission cable, connected to the signal output chip, for transmitting the compressed signal; A signal receiving chip connected to the transmission cable, configured to receive the compressed signal, decode the compressed signal, process the compressed signal into a plurality of groups of second parallel signals, and output the plurality of groups of second parallel signals; as well as a logic board chip, electrically connected to the signal receiving chip, for receiving a plurality of groups of the second parallel signals, performing a third encoding on the second parallel signals, processing the second parallel signals into display signals, and outputting the display signals to a display screen; The second encoding of the plurality of groups of the first parallel signals to form a group of compressed signals and outputting the compressed signals specifically includes: The first parallel signal is divided into blocks according to a first preset time interval to obtain a plurality of first parallel signal sub-blocks; all the first parallel signal sub-blocks in the same time period are merged to obtain a first compressed signal sub-block; all the first compressed signal sub-blocks are arranged in chronological order to obtain a compressed signal, and the compressed signal is output.

6. The signal processing device of the display device according to claim 5, characterized in that: The transmission cable includes at least one of a compression rate electronic cable or an optical fiber.

7. The signal processing device of the display device according to claim 5, characterized in that: The mainboard chip and the signal output chip are arranged on the same printed circuit board, and the mainboard chip and the signal output chip are connected via a first printed circuit; and / or, The logic board chip and the signal receiving chip are arranged on the same printed circuit board, and the logic board chip and the signal receiving chip are connected via a second printed circuit.

8. A signal processing system for a display device, characterized in that: include: A receiving module, used for receiving a control signal and first encoding to obtain a plurality of groups of first parallel signals; A compression module, used for encoding the multiple groups of parallel signals for a second time to obtain compressed signals; A decompression module, used for decoding the compressed signal to obtain multiple groups of second parallel signals; A sending module, used for encoding the plurality of groups of second parallel signals for a third time to obtain a display signal, and sending the display signal; The second encoding of the plurality of parallel signals to obtain the compressed signal specifically includes: The first parallel signal is divided into blocks according to a first preset time interval to obtain a plurality of first parallel signal sub-blocks; all the first parallel signal sub-blocks in the same time period are merged to obtain a first compressed signal sub-block; and all the first compressed signal sub-blocks are arranged in chronological order to obtain a compressed signal.

9. A storage medium, characterized in that: The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps in the signal processing method of the display device according to any one of claims 1 to 4.

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