A simultaneous multi-frequency bioelectrical impedance measurement system and method based on parallel processing

Abstract

The present invention discloses a simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing, which includes a host computer interaction module, an FPGA processing and peripheral circuit module, a digital-to-analog conversion DAC module, a low-pass filtering module, an addition operation circuit module, a voltage-controlled constant current source module, an instrumentation operational amplifier circuit module, a single-ended to differential circuit module, and a multi-channel high-speed ADC module. This system can perform parallel processing to simultaneously and synchronously output mixed-frequency excitation signals and perform synchronous and simultaneous signal detection, improving the detection efficiency. The present invention also provides a method for detecting current loss according to the above system to calibrate the detection system and monitor whether the output current is normal.

Description

Technical Field

[0001] The present invention belongs to the technical field of medical devices, and particularly relates to bioelectrical impedance measurement technology. Background Art

[0002] The multi-frequency bioelectrical impedance measurement technology injects weak current signals with different frequencies into biological tissues through excitation electrodes, and the detection electrodes measure voltage signals to obtain the electrical characteristics of biological tissues, and further conduct biomedical information analysis. It is a non-invasive biomedical detection technology. This technology is widely used in the fields of body composition analysis, disease diagnosis of the pulmonary vascular circulation system, edema detection, early diagnosis of tumors, etc. In body composition measurement, the excitation current is generally less than 2 mA. The smaller the excitation current, the safer it is for the human body. For individual instruments for measuring the body composition of pregnant women, the excitation current is less than 100 μA, but the weaker the signal, the smaller the signal-to-noise ratio, and it is more vulnerable to interference. At the same time, the cables of body composition devices based on eight electrodes often exceed one meter in length, and weak signals are extremely easy to attenuate during transmission. Using bioelectrical impedance imaging for pulmonary circulation system monitoring, blood flow monitoring, early tumor diagnosis, etc. requires real-time and rapid imaging. In order to obtain high-quality images, each frame of bioelectrical impedance image generated is preferably multi-frequency bioelectrical impedance data at the same moment, and it is required to have strong anti-interference ability and small signal attenuation.

[0003] With the development of theory and technology, the multi-frequency bioelectrical impedance measurement technology has been rapidly developed and widely applied. For example, the multi-frequency bioelectrical impedance measurement method mentioned in Chinese Patent CN109793516B does not use simultaneous multi-frequency bioelectrical impedance measurement within the same time period, and there is no processing method for the attenuation generated by the weak excitation current on the passing path. Therefore, when measuring multi-frequency bioelectrical impedance in the prior art, different frequencies of excitation currents are injected in different time periods. This method has a long measurement time and low measurement efficiency. If changes in biological tissues and external interference occur in different time periods, the measurement results will be inaccurate. At the same time, it is necessary to process the attenuation generated by the weak excitation current on the passing path. Summary of the Invention

[0004] Object of the Invention: Aiming at the above-mentioned shortcomings, the present invention provides a simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing to solve the problems of how to parallelly process and simultaneously synchronously output mixed-frequency excitation signals and synchronously detect signals.

[0005] The present invention also provides a current loss detection method according to the above-mentioned simultaneous multi-frequency bioelectrical impedance measurement system to improve the measurement efficiency and accuracy.

[0006] Technical Solution: To solve the above problems, the simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing of the present invention can adopt the following technical solutions:

[0007] A simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing, including an FPGA processing and peripheral circuit module; a digital-to-analog conversion DAC module, an addition operation circuit module, an instrumentation operational amplifier circuit module, a single-ended to differential circuit module, and a multi-channel high-speed ADC module;

[0008] The digital-to-analog conversion DAC module includes multiple DAC chips, and the multiple DAC chips generate waveforms with controllable phases using the same clock frequency; the digital-to-analog conversion DAC module is used to convert the DDS signal into an analog signal waveform;

[0009] The addition operation circuit module uses an addition circuit composed of operational amplifiers to add each analog signal waveform and convert it into a mixed-frequency signal S mix ;

[0010] The instrumentation operational amplifier circuit module is mainly composed of three instrumentation operational amplifiers, and the three instrumentation operational amplifiers respectively convert each single-ended voltage signal at both ends of the sampling resistors R S1 、R S2 、and the two single-ended voltage signals at both ends of the measured area M into single-ended signals, a total of three single-ended signals, and amplify the three single-ended signals and transmit them to the single-ended to differential circuit module;

[0011] The single-ended to differential circuit module includes three single-ended to differential amplifiers, which are used to convert three single-ended analog signals into three differential analog signals and transmit the signals to the multi-channel high-speed ADC module;

[0012] The multi-channel high-speed ADC module is used to convert the three differential analog signals into three digital signals and send the three digital signals in parallel to the FPGA processing and peripheral circuit module to simultaneously process the three collected digital signals;

[0013] The FPGA processing and peripheral circuit module includes an FPGA processing module, a DDR storage circuit outside the FPGA, and a clock source circuit; the FPGA processing module synchronously and parallelly generates multiple DDSs and synchronously and parallelly processes the three digital signals;

[0014] The FPGA processing module includes a clock frequency division module, a communication module, a parallel DDS module, an ADC control module, a FIFO read / write and DDR control module, a digital signal processing module, and a result operation and processing module; the clock frequency division module performs frequency division processing on an external clock signal; the multi-channel parallel DDS uses the same clock signal; the parallel DDS module generates multi-channel parallel waveform signals; the ADC control module mainly initializes and configures the mode of the ADC, and performs timing control on the three-channel digital signal data through a clock signal; the FIFO read / write and DDR control module caches the received three-channel digital signals and stores them in an external DDR memory, and then reads the data from the DDR and sends it to the next step for processing; the result operation and processing module mainly performs parallel operations on the obtained amplitude and impedance data, monitors the signal attenuation situation in real time, monitors in real time whether the excitation current signal is within the required range, and obtains the resistance impedance, resistance, capacitive reactance, and phase angle data of the measured area.

[0015] Beneficial effects: The simultaneous multi-frequency bioelectrical impedance measurement system provided by the present invention provides a means for simultaneous multi-frequency bioelectrical impedance detection, can parallel process and simultaneously synchronously output mixed-frequency excitation signals, and perform synchronous and simultaneous signal detection, improving the detection efficiency.

[0016] The current loss detection method of the simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing according to the present invention adopts the following technical solutions:

[0017] Let the current flowing through the sampling resistor R S1 be I RS1 , the current flowing through the sampling resistor R S2 be I RS2 , the current lost on the long cable L1 be I 损1 , the current lost on the long cable L2 be I 损2 , and the current flowing through the measured area M be I M ;

[0018] Let the allowable current deviation value at the frequency fi be T Ifi ; the upper computer interaction module presets the output current at the frequency fi to be I 设fi , and takes the current I RS2fi flowing through the sampling resistor RS2 as a comparison signal. If it meets I 设fi -T Ifi <I RS2fi <I 设fi +T Ifi , then the current output value at the frequency fi is within the normal range, otherwise the output current is abnormal or there is a problem with the connection system;

[0019] Let the allowable current reduction value flowing through between RS1 and RS2 at the frequency fi be T损fi ,T 损fi It is set in the host computer interaction module or preset in the FPGA processing module. If it meets I RS1fi -I RS2fi <T 损fi ,then the current reduction value at the frequency fi is within the normal range; otherwise, the current reduction value flowing through between RS1 and RS2 at the frequency fi exceeds the standard.

[0020] Beneficial effects: This current loss detection method can verify the detection system and monitor whether the output current is normal. Description of the Drawings

[0021] Figure 1 is a schematic structural diagram of a simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing in the present invention.

[0022] Figure 2 is a block diagram of a digital signal processing module.

[0023] Figure 3 is an attenuation impedance model diagram considering long cables. Specific Embodiments

[0024] The following describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0025] Combined with Figure 1 ,this embodiment provides a simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing, mainly including a host computer interaction module, an FPGA processing and peripheral circuit module, a digital-to-analog conversion DAC module, a low-pass filter module, an addition operation circuit module, a voltage-controlled constant current source module, an instrumentation operational amplifier circuit module, a single-ended to differential circuit module, and a multi-channel high-speed ADC module.

[0026] The host computer interaction module has functions such as display, input, and data adjustment. For example, a touch screen display can be used. In the host computer interaction module, the bioelectrical impedance data at each frequency of the detected area can be displayed, including data such as impedance, resistance, capacitance reactance, and phase angle. In the host computer interaction module, the waveform type, frequency, phase, and current value of each excitation signal can be adjusted. In different applications or application scenarios, users can adjust the waveform type, frequency, phase, and magnitude of the excitation current of each path according to the situation. For example, when detecting pregnant women, the excitation current can be adjusted to a smaller value to improve safety. For example, in a scenario with strong external interference, the excitation current can be increased to improve the signal-to-noise ratio of the signal and obtain more accurate information. By adjusting the excitation frequency values of each path, bioelectrical impedance data at multiple desired frequencies can be obtained, and corresponding biomedical information can be further analyzed.

[0027] The FPGA processing and peripheral circuit module mainly includes an FPGA processing module and a DDR storage circuit, a clock source circuit, etc. outside the FPGA.

[0028] The clock source circuit outside the FPGA mainly provides a clock source signal for the FPGA, and the clock frequency required for internal processing of the FPGA can be divided or multiplied based on this. The DDR storage circuit outside the FPGA is used to cache a large number of high-speed data signals, such as using a DDR3 SDRAM memory.

[0029] The FPGA processing module mainly includes a clock division module, a communication module, a parallel DDS (Direct Digital Frequency Synthesis) module, an ADC control module, an FIFO read / write and DDR control module, a digital signal processing module, a result operation and processing module, etc. The FPGA processing module can utilize the advantage of parallel operation processing of the FPGA to synchronously and parallelly generate multiple DDSs, and can synchronously and parallelly process multiple ADC signals.

[0030] The clock division module performs frequency division processing on the external clock signal, mainly generating clock signals including DDS_CLK, DDR_CLK, ADC_CLK, COM_CLK, etc. DDS_CLK provides a unified clock signal for the parallel DDS module. Multiple parallel DDSs use the same clock signal, which is convenient for timing control and phase control of the generated signals. DDR_CLK is the clock signal when the FPGA interacts with the external DDR for data. ADC_CLK is the clock signal when the FPGA communicates with the high-speed ADC. COM_CLK is the clock signal of the communication module inside the FPGA.

[0031] The communication module mainly conducts data communication with the host computer interaction module, such as transmitting data such as the calculated bioelectrical impedance to the host computer, receiving data on the waveform type, waveform frequency, waveform phase, and current magnitude of each channel, and processing the data to convert it into waveform type control data WC, frequency control data FC, phase control data PC, and amplitude control data AC required for each DDS signal of the parallel DDS module.

[0032] The parallel DDS module mainly generates multiple parallel waveform signals, which can be sine waves, square waves, or irregular waveforms. The ROM of the FPGA stores data of different waveforms in different address segments in advance. The type, frequency, phase, and amplitude of the waveform are controlled by WC, FC, PC, and AC data respectively. The WC value is the initial address of each waveform in the ROM. By adding different WC data through the adder, different waveforms can be adjusted. By adjusting the FC value, the accumulation speed of the accumulator is changed, and by adjusting the speed of reading a certain waveform data from the ROM lookup table, the waveform frequency can be adjusted. PC is the initial self-increment value of the initial ROM address of a certain waveform. By adjusting the self-increment initial value PC, the phase can be adjusted. AC is the coefficient value. After looking up the data in the ROM and then multiplying it by the coefficient AC through the multiplier, the data in the ROM is scaled, and the amplitude value can be adjusted. For the convenience of subsequent addition operations and signal processing, the parallel DDS module uses the same clock signal DDS_CLK and the same phase at the same time.

[0033] The ADC control module mainly performs communication configuration on the ADC, initializes and configures the mode of the ADC, and performs timing control on the multiple-channel ADC data through the clock signal.

[0034] The FIFO read / write and DDR control module mainly caches the received multiple-channel parallel ADC data and stores it in the external DDR memory, and then reads the data from the DDR and sends it to the next step for processing.

[0035] Combined Figure 1 and Figure 2 , the digital signal processing module mainly performs parallel processing on the three-channel ADC data in a pipelined manner, and performs band-pass filtering on the voltage data R S1 _Data1 at both ends of the sampling resistor R S1 , the voltage data M_Data2 at both ends of the measured area M, and the voltage data R S2 _Data1 at both ends of the sampling resistor R S2 through three FIR filters to filter out the interference signal data. After filtering, it is further processed by fast Fourier transform (FFT) to obtain the amplitude and phase at each frequency in the mixed-frequency signal. At the frequency fi, the voltage amplitude at both ends of the sampling resistor R S1 is R S1 _A fi , and the phase is R S1 _θ fi . At the frequency fi, the voltage amplitude at both ends of the measured area M is M_A fi , and the phase is M_θ fi . At the frequency fi, the voltage amplitude at both ends of the sampling resistor R S2 is R S2 _Afi , the phase is R S2 _θ fi .

[0036] The result operation and processing module mainly performs parallel operations on the acquired amplitude and impedance data, monitors the signal attenuation in real time, monitors whether the excitation current signal is within the required range in real time, and acquires the impedance, resistance, reactance, and phase angle data of the measured area.

[0037] The digital-to-analog conversion DAC module is mainly composed of multiple DAC chips. The multiple DACs use the same clock frequency, which is convenient for generating waveforms with controllable phases. The DDS generates a digital signal approximate to an analog waveform, and the DAC module converts each DDS signal into an analog signal waveform.

[0038] The low-pass filter module is mainly composed of multiple low-pass filter circuits LPF, which perform low-pass filtering on each signal to filter out high-frequency interference signals in the signal and make the signal smoother. The output of the i-th signal is S i . i is a natural number greater than 0.

[0039] The addition operation circuit can adopt an addition circuit composed of operational amplifiers to add each signal and convert it into a mixed-frequency signal S mix . Converting multiple parallel signals into one mixed-frequency signal reduces the circuit complexity. While improving the anti-interference ability, it can also inject the biological tissue to be detected at the same time. For example, if there are six signals, then S mix = S1 + S2 + S3 + S4 + S5 + S6.

[0040] The voltage-controlled constant current source module converts the voltage signal into a constant current signal, and its current value is controlled by the magnitude of the input voltage. The current magnitude can be adjusted by adjusting the input amplitude of each signal. The constant current signal passes through the sampling resistor R S1 , long cable L1, selection switch SW, measured area M, long cable L2, sampling resistor R S2 , and finally forms a loop. In practical applications, the sampling resistors R S1 、R S2 have known and equal resistance values and are placed on the circuit board. There is a certain distance from the circuit board to the measured area M, and long cables L1 and L2 will be used for connection.

[0041] The instrumentation operational amplifier circuit module is mainly composed of three instrumentation operational amplifiers. The three instrumentation operational amplifiers respectively convert the differential voltage signals at both ends of the sampling resistors R S1 、R S2 、and the measured area M into single-ended signals, and amplify the signals and then transmit them to the single-ended to differential circuit module.

[0042] The single-ended to differential circuit module is mainly composed of three single-ended to differential amplifiers, which are also three differential ADC driver circuits. They convert single-ended analog signals into differential analog signals and transmit the signals to the multi-channel high-speed ADC module. This is the differential ADC driver circuit for the front stage of the precision ADC, which can reduce high-frequency power supply ripple interference, improve the common-mode rejection ratio, and enhance the anti-interference ability.

[0043] The multi-channel high-speed ADC module can convert the three-channel differential analog signals into digital signals and send the three-channel digital signals to the FPGA in parallel, so that the three-channel collected signals can be processed simultaneously.

[0044] Combined Figure 3 , Figure 3 To consider the long cable attenuation impedance model, since there is a certain distance between the sampling resistor on the circuit board and the measured area in practical applications, the connected long cable itself has a certain impedance, and there are stray resistors and capacitors between the signal line and the ground. The excitation current will generate a certain attenuation when transmitted through the long cable. Let the current flowing through the sampling resistor R S1 be I RS1 , the current flowing through the sampling resistor R S2 be I RS2 , the current lost on the long cable L1 be I 损1 , the current lost on the long cable L2 be I 损2 , and the current flowing through the measured area M be I M . According to Kirchhoff's current law, we know that:

[0045] I RS1 =I 损1 +I M ;

[0046] I M =I 损2 +I RS2 ;

[0047] In practical applications, the long cables L1 and L2 have the same design and technology, etc., and the current losses on the cables are close. It can be assumed that I 损1 is equal to I 损2 , then we know that:

[0048]

[0049] The current of the measured area M at the frequency fi is I Mfi , the current of the sampling resistor R S1 at the frequency fi is I RS1fi , the current of the sampling resistor R S2 at the frequency fi is I RS2fi , and the impedance value of the measured area M at the frequency fi is Z fi, the differential signals at both ends of the measured area M are amplified by a total magnification of K through an instrument operational amplifier circuit module and a single-ended to differential circuit module. Let the sampling resistances R S1 and R S1 be R, then:

[0050]

[0051]

[0052]

[0053]

[0054] Then:

[0055]

[0056] The phase angle of the measured area M at frequency fi is θ fi , then:

[0057] θ fi = M_θ fi - R S1 _θ fi ;

[0058] The resistance of the measured area M at frequency fi is R fi , then:

[0059] R fi = Z fi cos(θ fi );

[0060] Then:

[0061]

[0062] The bioelectrical impedance of the measured biological tissue consists of resistance and reactance. Reactance mainly includes capacitive reactance and inductive reactance. In biological tissue, the inductive reactance component is very small. Here, the reactance is equal to the capacitive reactance. The capacitive reactance of the measured area M at frequency fi is X fi , then:

[0063] X fi = Z fi sin(θ fi );

[0064] Then:

[0065]

[0066] Thus, the final calculation results Z fi , R fi , X fi, both consider signal attenuation and perform synchronous calculations, reducing the result errors caused by signal attenuation and data asynchrony.

[0067] Let the allowable current deviation value at frequency fi be T Ifi , T Ifi can be set in the host computer interaction module or pre-set in the FPGA. The current output by the host computer interaction module pre-set at frequency fi is I 设fi , and the current I S2 flowing through the sampling resistor R RS2fi is used as the comparison signal. If it meets I 设fi -T Ifi < I RS2fi < I 设fi +T Ifi , then the current output value at this frequency fi is within the normal range; otherwise, the output current is abnormal or there is a problem with the connection system, which can be used as a basis for verifying the detection system and monitoring whether the output current is normal.

[0068] Let the allowable current loss value between R S1 and R S2 at frequency fi be T 损fi , T 损fi can be set in the host computer interaction module or pre-set in the FPGA. If it meets I RS1fi -I RS2fi < T 损fi , then the current loss value at this frequency fi is within the normal range; otherwise, the current loss value between R S1 and R S2 at frequency fi exceeds the standard, and it is necessary to detect whether the system between R S1 and R S2 is normal, which can remind the user to check. In particular, it can be used to detect whether the long cables L1 and L2 meet the current loss requirements.

[0069] The simultaneous multi-frequency bioelectrical impedance measurement system in this embodiment provides a means for simultaneous multi-frequency bioelectrical impedance detection, which can process and output mixed-frequency excitation signals in parallel and synchronously, and detect signals synchronously, improving the detection efficiency. At the same time, the user can adjust the output parameters of the excitation signal of the system, etc., to adapt to different application scenarios, and can reduce the result errors caused by signal attenuation and data asynchrony.

[0070] The signal attenuation monitoring method provided in this embodiment is used to verify the detection system and monitor whether the output current is normal.

[0071] There are many methods and ways to specifically implement this technical solution in the present invention. The above description is only the preferred implementation manner of the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention. Each component not clearly defined in this embodiment can be implemented by using the prior art.

Claims

1. A simultaneous multi-frequency bioelectrical impedance measurement system based on parallel processing, characterized in that It includes an FPGA processing and peripheral circuit module; a digital-to-analog conversion DAC module, an addition operation circuit module, an instrumentation operational amplifier circuit module, a single-ended to differential circuit module, and a multi-channel high-speed ADC module; The digital-to-analog conversion DAC module includes multiple DAC chips, and the multiple DAC chips generate waveforms with controllable phases using the same clock frequency; The digital-to-analog conversion DAC module is used to convert the DDS signal into an analog signal waveform; The addition operation circuit module uses an addition circuit composed of operational amplifiers to add each analog signal waveform and convert it into a mixed-frequency signal S mix ; The instrument operational amplifier circuit module is mainly composed of three instrument operational amplifiers. The three instrument operational amplifiers respectively convert the differential voltage signals of one path at both ends of the sampling resistors R S1 , R S2 and the measured area M into single-ended signals, with a total of three single-ended signals, and amplify the three single-ended signals and then transmit them to the single-ended to differential circuit module; The single-ended to differential circuit module includes three single-ended to differential amplifiers, which are used to convert three single-ended analog signals into three differential analog signals and transmit the signals to the multi-channel high-speed ADC module; The multi-channel high-speed ADC module is used to convert the three differential analog signals into three digital signals and parallelly send the three digital signals to the FPGA processing and peripheral circuit module to simultaneously process the three collected digital signals; The FPGA processing and peripheral circuit module includes an FPGA processing module, a DDR storage circuit outside the FPGA, and a clock source circuit; the FPGA processing module synchronously and parallelly generates multiple DDSs and synchronously and parallelly processes three digital signals; The FPGA processing module includes a clock division module, a communication module, a parallel DDS module, an ADC control module, an FIFO read / write and DDR control module, a digital signal processing module, and a result operation and processing module; the clock division module performs frequency division processing using an external clock signal; The multiple parallel DDSs use the same clock signal; the parallel DDS module generates multiple parallel waveform signals; the ADC control module mainly initializes and configures the mode of the ADC and performs timing control on the data of the three digital signals through the clock signal; the FIFO read / write and DDR control module caches the three received digital signals and stores them in the external DDR memory, and then reads the data from the DDR and sends it to the next step for processing; the result operation and processing module mainly performs parallel operations on the obtained amplitude and impedance data, monitors the signal attenuation situation in real time, monitors whether the excitation current signal is within the required range in real time, and obtains the resistance impedance, resistance, capacitance reactance, and phase angle data of the measured area; The digital signal processing module performs parallel processing on the three-channel ADC data in a pipelined manner, and for the voltage data R S1 across both ends of the sampling resistor R S1 _Data1, the voltage data M_Data2 across both ends of the measured area M, and the voltage data R S2 across both ends of the sampling resistor R S2 _Data1 simultaneously pass through three FIR filters for band-pass filtering to remove the interference signal data, and after filtering, perform fast Fourier transform for further processing to obtain the amplitude and phase at each frequency in the mixed-frequency signal.

2. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 1, wherein Sampling resistor R at frequency fi S1 The voltage amplitude across both ends is R S1 _A fi and the phase is R S1 _θ fi At frequency fi, the voltage amplitude across both ends of the measured area M is M_A fi and the phase is M_θ fi At frequency fi, sampling resistor R S2 The voltage amplitude across both ends is R S2 _A fi and the phase is R S2 _θ fi .

3. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 2, characterized in that, It also includes that the ROM of the FPGA processing module stores data of different waveforms in different address segments in advance; the type, frequency, phase, and amplitude of the waveform are respectively controlled by WC, FC, PC, and AC data; the WC value is the initial address of each waveform in the ROM, and different waveforms are adjusted by adding different WC data through an adder; by adjusting the FC value, the accumulation speed of the accumulator is changed, and the speed of reading a certain waveform data from the ROM lookup table is adjusted to adjust the waveform frequency; PC is the self-increment initial value of the initial ROM address of a certain waveform, and the phase is adjusted by adjusting the self-increment initial value PC; AC is a coefficient value, and after looking up the data in the ROM and then multiplying by the coefficient AC through a multiplier, the data in the ROM is scaled to adjust the amplitude value; The multiple parallel DDS modules use the same clock signal DDS_CLK and the same phase at the same time.

4. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 1 or 2 or 3, characterized in that It further includes a low-pass filtering module, which includes multiple low-pass filtering circuits LPF to perform low-pass filtering on each analog signal to filter out high-frequency interference signals in the analog signal.

5. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 1 or 2 or 3, characterized in that, It also includes a voltage-controlled constant current source module for converting a voltage signal into a constant current signal, and the current magnitude can be adjusted by adjusting the input amplitude of each signal; the constant current signal passes through a sampling resistor R S1 , long cable L1, selector switch SW, measured area M, long cable L2, sampling resistor R S2 to finally form a loop; among them, the sampling resistors R S1 , R S2 have known and equal resistances and are placed on the circuit board. There is a certain distance between the circuit board and the measured area M, and long cables L1 and L2 are used for connection.

6. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 3, characterized in that It further includes a communication module and a host computer interaction module. The communication module conducts data communication with the host computer interaction module, including transmitting the calculated bioelectrical impedance data to the host computer, receiving the waveform type, waveform frequency, waveform phase, and current magnitude data of each path, and processing the data to convert it into the waveform type control data WC, frequency control data FC, phase control data PC, and amplitude control data AC required for each DDS signal of the parallel DDS module.

7. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 6, characterized in that The host computer interaction module has the functions of display, input, and data adjustment. The bioelectrical impedance data at each frequency in the detected area can be displayed on the host computer interaction module, and the waveform type, frequency, phase, and current value of the excitation signal for each path can be adjusted on the host computer interaction module.

8. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 6, wherein The clock source circuit outside the FPGA provides a clock source signal for the FPGA, and the clock frequency required for internal processing of the FPGA is divided or multiplied according to the clock source signal; the DDR storage circuit outside the FPGA is used to cache a large number of high-speed data signals.

9. The simultaneous multi-frequency bioelectrical impedance measurement system according to claim 6, characterized in that The current flowing through the sampling resistor R S1 is I RS1 , the current flowing through the sampling resistor R S2 is I RS2 , the current lost on the long cable L1 is I 损1 , the current lost on the long cable L2 is I 损2 , the current flowing through the measured area M is I M ; the current of the measured area M at the frequency fi is I Mfi , the current of the sampling resistor R S1 at the frequency fi is I RS1fi , the current of the sampling resistor R S2 at the frequency fi is I RS2fi , the impedance value of the measured area M at the frequency fi is Z fi , the total amplification factor of the differential signal at both ends of the measured area M through the instrument operational amplifier circuit module and the single-ended to differential circuit module is K. Assume the resistance of the sampling resistors R S1 、R S1 is R; the capacitive reactance of the measured area M at the frequency fi is X fi ; 10. A method for detecting current loss of a simultaneous multi-frequency bioelectrical impedance measurement system according to any one of claims 1 to 9, characterized in that, It includes: Let the current flowing through the sampling resistor R S1 be I RS1 , the current flowing through the sampling resistor R S2 be I RS2 , the current lost on the long cable L1 be I 损1 , the current lost on the long cable L2 be I 损2 , the current flowing through the area M to be measured be I M ; Let the allowable current deviation value at frequency fi be T Ifi ; the host computer interaction module presets the output current at frequency fi as I 设fi , and takes the current I RS2fi flowing through the sampling resistor RS2 as the comparison signal. If it meets I 设fi - T Ifi < I RS2fi < I 设fi + T Ifi , then the current output value at this frequency fi is within the normal range; otherwise, the output current is abnormal or there is a problem with the connection system Let the allowable current loss value flowing between RS1 and RS2 at frequency fi be T 损fi , T 损fi Be set in the host computer interaction module or preset in the FPGA processing module. If it meets I RS1fi -I RS2fi <T 损fi , then the current loss value at this frequency fi is within the normal range; otherwise, the current loss value flowing between RS1 and RS2 at frequency fi exceeds the standard.

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