Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device comprises a bridge redistribution layer comprising a high-density circuit area and a low-density circuit area; a first electronic component disposed below the bridge redistribution layer, a front surface of the first electronic component being provided with a first high-density input-output (I / O) area and a first low-density I / O area, the first high-density I / O area being electrically connected to the high-density circuit area, and the first low-density I / O area being electrically connected to the low-density circuit area through wire bonding; and a second electronic component disposed adjacent to the first electronic component, a front surface of the second electronic component being provided with a second high-density I / O area and a second low-density I / O area, the second high-density I / O area being electrically connected to the high-density circuit area.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device and a manufacturing method thereof. BACKGROUND

[0002] In the existing packaging structure, such as the FOCoS (Fan Out Chip on Substrate) packaging structure, the ASIC (Application Specific Integrated Circuit) electronic element and the HBM (High Bandwidth Memory) electronic element are prone to offset problems in the FCB (Flip Chip Bonding) process, which in turn causes the phenomenon of non-joint at the low-density input-output I / O area bump. SUMMARY

[0003] The present disclosure provides a semiconductor packaging device and a manufacturing method thereof.

[0004] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising:

[0005] a bridge redistribution layer comprising a high-density circuit area and a low-density circuit area;

[0006] a first electronic element disposed below the bridge redistribution layer, a first active surface of the first electronic element being provided with a first high-density I / O area and a first low-density I / O area, the first high-density I / O area being electrically connected to the high-density circuit area, and the first low-density I / O area being electrically connected to the low-density circuit area through wire bonding;

[0007] a second electronic element disposed adjacent to the first electronic element, a second active surface of the second electronic element being provided with a second high-density I / O area and a second low-density I / O area, the second high-density I / O area being electrically connected to the high-density circuit area.

[0008] In some optional embodiments, the second low-density I / O area is electrically connected to the low-density circuit area through wire bonding.

[0009] In some optional embodiments, the bridge redistribution layer further comprises a via, and the wire bonding connects the low-density circuit area through the via.

[0010] In some optional embodiments, a protective layer is provided on the bridge redistribution layer corresponding to the via, and the protective layer covers the wire bonding passing through the via.

[0011] In some alternative embodiments, the low-density circuit area is provided with solder balls.

[0012] In some alternative embodiments, the bridge redistribution layer is provided with a circuit layer, the circuit layer comprising a first via hole electrically connecting the bridge redistribution layer.

[0013] In some alternative embodiments, the circuit layer further comprises a second via hole electrically connecting the second low-density I / O area.

[0014] In some alternative embodiments, the circuit layer is provided with solder balls.

[0015] In some alternative embodiments, the first electronic component, the second electronic component, and the high-density circuit area are filled with an underfilling agent.

[0016] In some alternative embodiments, the device further comprises:

[0017] a packaging layer disposed under the bridge redistribution layer and covering the first electronic component and the second electronic component.

[0018] In some alternative embodiments, a surface of the packaging layer is substantially coplanar with a non-active surface of the first electronic component or a non-active surface of the second electronic component.

[0019] In some alternative embodiments, a surface of the packaging layer is provided with a heat dissipation layer.

[0020] In some alternative embodiments, the first high-density I / O area and the high-density circuit area are electrically connected by solder, and the second high-density I / O area and the high-density circuit area are electrically connected by solder.

[0021] In some alternative embodiments, a via hole diameter of the first low-density I / O area is greater than a via hole diameter of the first high-density I / O area, and a via hole diameter of the second low-density I / O area is greater than a via hole diameter of the second high-density I / O area.

[0022] In a second aspect, the present disclosure provides a manufacturing method of a semiconductor packaging device, comprising:

[0023] providing a bridge redistribution layer, the bridge redistribution layer comprising a high-density circuit area and a low-density circuit area;

[0024] providing a first electronic component and a second electronic component, the first electronic component being provided with a first high-density input-output (I / O) area and a first low-density I / O area on an active surface thereof, and the second electronic component being provided with a second high-density I / O area and a second low-density I / O area on an active surface thereof;

[0025] electrically connecting the first high-density I / O area and the second high-density I / O area with the high-density circuit area;

[0026] electrically connecting the first low-density I / O area and the second low-density I / O area with the low-density circuit area by wire bonding.

[0027] In some optional embodiments, before the step of electrically connecting the first low-density I / O area and the second low-density I / O area with the low-density circuit area by wire bonding, the method further comprises:

[0028] turning over the bridge redistribution layer.

[0029] In the semiconductor packaging device and the manufacturing method thereof provided by the present disclosure, by designing the semiconductor packaging device to include a bridge redistribution layer including a high-density circuit area and a low-density circuit area, a first electronic component disposed below the bridge redistribution layer, a first active surface of the first electronic component provided with a first high-density I / O area and a first low-density I / O area, the first high-density I / O area electrically connected with the high-density circuit area, and the first low-density I / O area electrically connected with the low-density circuit area by wire bonding, and a second electronic component disposed adjacent to the first electronic component, a second active surface of the second electronic component provided with a second high-density I / O area and a second low-density I / O area, the second high-density I / O area electrically connected with the high-density circuit area, and the second low-density I / O area electrically connected with the low-density circuit area by wire bonding, the problem of welding failure caused by the offset between the first low-density I / O area and the low-density circuit area when directly connected by FCB process is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0030] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the drawings:

[0031] FIG. 1A is a longitudinal cross-sectional structure schematic diagram of one embodiment of a semiconductor packaging device according to the present disclosure;

[0032] FIG. 1B 、 1C , 1D, 1E, 1F are longitudinal cross-sectional structure schematic diagrams of different embodiments of a semiconductor packaging device according to the present disclosure;

[0033] FIGS. 2A-2H is a cross-sectional view of a semiconductor packaging device manufactured at each stage according to one embodiment of the present disclosure.

[0034] SYMBOL DESCRIPTION:

[0035] 11 - bridge rewiring layer; 111 - high-density circuit area; 112 - low-density circuit area; 113 - via; 12 - first electronic component; 121 - first high-density I / O area; 122 - first low-density I / O area; 13 - second electronic component; 131 - second high-density I / O area; 132 - second low-density I / O area; 14 - circuit layer; 141 - first via; 142 - second via; 15 - solder ball; 16 - encapsulation layer; 17 - heat dissipation layer; 18 - wire; 19 - underfill; 20 - protection layer; 21 - carrier; 22 - seed layer; DETAILED DESCRIPTION

[0036] The technical problems solved by the present disclosure and the technical effects generated by the present disclosure can be easily understood by those skilled in the art through the content recorded in the present specification. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, only the parts related to the application are shown in the drawings for ease of description.

[0037] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and do not have technical significance to limit the implementation of the present disclosure. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be generated by the present disclosure, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second" and "one" in the present specification are only for the convenience of clear description, and not to limit the scope of the present disclosure, and the change or adjustment of the relative relationship, without substantially changing the technical content, is also regarded as the implementation of the present disclosure.

[0038] It should also be noted that the embodiments of the present disclosure correspond to the longitudinal cross-section in the front view direction, the transverse cross-section in the right view direction, and the horizontal cross-section in the upper view direction.

[0039] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the drawings and in combination with the embodiments.

[0040] Reference FIG. 1A , FIG. 1A is a longitudinal cross-sectional structure schematic diagram of one embodiment of a semiconductor packaging device according to the present disclosure.

[0041] As FIG. 1AAs shown, the semiconductor package device 100A can include a bridge redistribution layer 11, a first electronic element 12, and a second electronic element 13. Among them:

[0042] The bridge redistribution layer 11 includes a high-density circuit area 111 and a low-density circuit area 112.

[0043] The bridge redistribution layer 11 can be a redistribution layer (RDL) composed of a conductive trace and a dielectric material. It should be noted that the process can use the current known or future developed redistribution layer forming technology, and the present disclosure does not make specific limitations, for example, the redistribution layer can be formed by photolithography, plating, electroless plating, etc. Here, the dielectric material can include organic and / or inorganic materials, where the organic material can be, for example: polyamide (PA), polyimide (PI), epoxy, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, pre-impregnated material or semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., and the inorganic material can be, for example: silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example: titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer can be, for example: gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or its alloy.

[0044] The bridge redistribution layer 11 can also include interconnection structures such as conductive traces, conductive vias, etc. Here, the conductive vias can be through holes, buried holes or blind holes, and the through holes, buried holes or blind holes can be filled with conductive materials such as metals or metal alloys, where the metal can be, for example: gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or its alloy.

[0045] Here, the densities corresponding to the high-density circuit area 111 and the low-density circuit area 112 can include the I / O density of the redistribution layer. In the present disclosure, the I / O can include conductive vias.

[0046] The first electronic component 12 is disposed under the bridge redistribution layer 11. The active surface of the first electronic component 12 is provided with a first high-density I / O area 121 and a first low-density I / O area 122. The first high-density I / O area 121 is electrically connected to the high-density circuit area 111. The first low-density I / O area 122 is electrically connected to the low-density circuit area 112 through the wire 18.

[0047] The second electronic component 13 is disposed adjacent to the first electronic component 12. The active surface of the second electronic component 13 is provided with a second high-density I / O area 131 and a second low-density I / O area 132. The second high-density I / O area 131 is electrically connected to the high-density circuit area 111.

[0048] In the present disclosure, the types of the first electronic component 12 and the second electronic component 13 are not specifically limited. The first electronic component 12 and the second electronic component 13 can be electronic components of the same type or different types. For example, the first electronic component 12 and the second electronic component 13 can include a die, an ASIC (Application Specific Integrated Circuit) chip, a PMIC (Power Management Integrated Circuit) chip, or an HBM (High Bandwidth Memory) chip, etc.

[0049] In some optional embodiments, as shown in FIG. 1B, the first low-density I / O area 122 is electrically connected to the low-density circuit area 112 through the wire 18. FIG. 1A

[0050] In some optional embodiments, as shown in FIG. 1B, the first low-density I / O area 122 is electrically connected to the low-density circuit area 112 through the wire 18. FIG. 1A

[0051] In some optional embodiments, the first high-density I / O area 121 and the high-density circuit area 111 are electrically connected through solder, and the second high-density I / O area 131 and the high-density circuit area 111 are electrically connected through solder.

[0052] In some optional embodiments, the diameter of the via of the first low-density I / O area 122 is greater than the diameter of the via of the first high-density I / O area 121, and the diameter of the via of the second low-density I / O area 132 is greater than the diameter of the via of the second high-density I / O area 131.

[0053] In some optional embodiments, as shown in FIG. 1B, the bridge redistribution layer 11 further includes a via hole 113. The wire 18 is connected to the low-density circuit area 112 through the via hole 113. FIG. 1A ​​As shown, the bridge redistribution layer 11 is provided with a circuit layer 14, and the circuit layer 14 includes a first via 141 electrically connected to the bridge redistribution layer 11.

[0054] The circuit layer 14 can be a circuit layer or a redistribution layer composed of a conductive trace and a dielectric material. It should be noted that the process can adopt a currently known or future developed redistribution layer forming technology, and the present disclosure does not make specific limitations thereon, for example, the redistribution layer can be formed by processes including but not limited to photolithography, plating, electroless plating, etc. Here, the dielectric material can include organic and / or inorganic materials, wherein the organic material can be, for example, polyamide (PA), PI, epoxy, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP, ABF, etc., and the inorganic material can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

[0055] The circuit layer 14 can further include an interconnection structure, such as a conductive trace, a conductive via, etc. Here, the conductive via can be a through hole, a buried hole, or a blind hole, and the through hole, the buried hole, or the blind hole can be filled with a conductive material such as a metal or a metal alloy, wherein the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

[0056] In some optional embodiments, as shown in FIG. 1C, the semiconductor package device 100A further includes a solder ball 15 provided on the circuit layer 14. FIG. 1A

[0057] In some optional embodiments, as shown in FIG. 1C, the semiconductor package device 100A further includes a solder ball 15 provided on the circuit layer 14. FIG. 1A

[0058] In some optional embodiments, as shown in FIG. 1C, the semiconductor package device 100A further includes a solder ball 15 provided on the circuit layer 14. FIG. 1A In some optional embodiments, as shown in FIG. 1C, the semiconductor package device 100A further includes a solder ball 15 provided on the circuit layer 14.​​

[0059] The encapsulation layer 16 can be formed of various molding compounds. For example, the molding compound can include an epoxy resin, a filler, a catalyst, a pigment, a release agent, a flame retardant, a coupling agent, a hardener, a low stress absorber, an adhesion promoter, an ion trapping agent, etc.

[0060] Reference will now be made to FIG. 1B , FIG. 1B is a longitudinal cross-sectional structure schematic diagram of one embodiment 100B of a semiconductor package device according to the present disclosure. FIG. 1B The semiconductor package device 100B shown is similar to the semiconductor package device 100A shown in FIG. 1A , except that in the semiconductor package device 100B, the surface of the encapsulation layer 16 is substantially coplanar with the non-active side of the first electronic element 12.

[0061] Here, the two surfaces being substantially coplanar can be considered as: the height difference between the two surfaces is no more than 5 micrometers (pm), no more than 2 micrometers (pm), no more than 1 micrometer (pm), or no more than 0.5 micrometers (pm).

[0062] In some alternative embodiments, the surface of the encapsulation layer 16 is substantially coplanar with the non-active side of the first electronic element 12 or the non-active side of the second electronic element 13.

[0063] Reference will now be made to FIG. 1C , FIG. 1C is a longitudinal cross-sectional structure schematic diagram of one embodiment 100C of a semiconductor package device according to the present disclosure. FIG. 1C The semiconductor package device 100C shown is similar to the semiconductor package device 100A shown in FIG. 1A , except that in the semiconductor package device 100C, the surface of the encapsulation layer 16 is provided with a heat dissipation layer 17. In some alternative embodiments, the heat dissipation layer 17 is provided against the non-active side of the first electronic element 12. The heat dissipation layer 17 is capable of conducting heat with the encapsulation layer 16 and the first electronic element 12, improving the heat dissipation performance of the semiconductor package device.

[0064] Reference will now be made to FIG. 1D , FIG. 1D is a longitudinal cross-sectional structure schematic diagram of one embodiment 100D of a semiconductor package device according to the present disclosure.FIG. 1D The semiconductor package device 100D shown is similar to the semiconductor package device 100A shown in FIG. 1A , except that in the semiconductor package device 100D, the bridge redistribution layer 11 is also provided with the same structure as the bridge redistribution layer 11, the first electronic element 12 and the second electronic element 13 in the extending direction, and the structure of the bridge redistribution layer 11 in the extending direction corresponds to the structure of the bridge redistribution layer 11 shown in FIG. 1A , which will not be described here again.

[0065] Reference will now be made to FIG. 1E , FIG. 1E is a longitudinal sectional structure schematic diagram of one embodiment 100E of the semiconductor package device according to the present disclosure. FIG. 1E The semiconductor package device 100E shown is similar to the semiconductor package device 100A shown in FIG. 1A , except that in the semiconductor package device 100E, the circuit layer 14 further comprises a second via hole 142, and the second via hole 142 is electrically connected to the second low-density I / O area 132.

[0066] Reference will now be made to FIG. 1F , FIG. 1F is a longitudinal sectional structure schematic diagram of one embodiment 100F of the semiconductor package device according to the present disclosure. FIG. 1F The semiconductor package device 100F shown is similar to the semiconductor package device 100A shown in FIG. 1A , except that in the semiconductor package device 100F, a protective layer 20 is provided on the bridge redistribution layer 11 corresponding to the via hole, and the protective layer 20 covers the wire 18 passing through the via hole; and a solder ball 15 is provided on the low-density circuit area 112.

[0067] The protective layer 20 can include liquid and / or thin-film organic matter, such as: non-conductive plastic (NCP), non-conductive film (NCF), anisotropic conductive adhesive film (ACF), anisotropic conductive adhesive plastic (ACP), PI, Epoxy, resin, PP, ABF, glue, etc.

[0068] Reference will now be made to FIGS. 2A-2H , FIGS. 2A-2H are longitudinal sectional structure schematic diagrams of the semiconductor package devices 200A, 200B, 200C, 200D, 200E, 200F, 200G and 200H manufactured at various stages according to one embodiment of the present disclosure.

[0069] Referring to FIG. 2A , a carrier plate 21 is provided, and the bridge redistribution layer 11 is disposed on the carrier plate 21.

[0070] The bridge redistribution layer 11 includes a high-density circuit area 111 and a low-density circuit area 112, and a through hole 113 is formed in the bridge redistribution layer 11.

[0071] Referring to FIG. 2B , a first electronic element 12 and a second electronic element 13 are provided, and the first electronic element 12 is provided with a first high-density I / O area 121 and a first low-density I / O area 122 on the active surface, and the second electronic element 13 is provided with a second high-density I / O area 131 and a second low-density I / O area 132 on the active surface.

[0072] The first high-density I / O area 121 of the first electronic element 12 and the second high-density I / O area 131 of the second electronic element 13 are bonded to the high-density circuit area 111, so that the first high-density I / O area 121 and the second high-density I / O area 131 are electrically connected to the high-density circuit area 111.

[0073] In the electrical connection process, flip chip bonding (FCB), thermal compression bonding (TCB) or the like can be used.

[0074] The first low-density I / O area and the second low-density I / O area are electrically connected to the low-density circuit area by wire bonding.

[0075] Referring to FIG. 2C , a bottom filler 19 is filled between the first electronic element 12, the second electronic element 13 and the high-density circuit area 111.

[0076] Referring to FIG. 2D , a mold is sealed to form a packaging layer 16, and the packaging layer 16 covers the first electronic element 12 and the second electronic element 13.

[0077] Referring to FIG. 2E , the carrier plate 21 is removed after being turned over.

[0078] Referring to FIG. 2F , the first low-density I / O area 122 and the second low-density I / O area 132 are electrically connected to the low-density circuit area 112 by wire bonding 18.

[0079] Referring to FIG. 2G , a circuit layer 14 is disposed on the bridge redistribution layer 11, and the circuit layer 14 includes a first via hole 141 electrically connected to the bridge redistribution layer 11.

[0080] Referring toFIG. 2H Solder balls 15 are provided on the circuit layer 14.

[0081] The provided method of manufacturing a semiconductor structure of the present disclosure can achieve similar technical effects as the aforementioned semiconductor structure, which will not be repeated here.

[0082] Although the present disclosure has been described and illustrated with reference to specific embodiments, these are intended only to illustrate the present disclosure and are not intended to limit the present disclosure. Various changes in form and detail can be made without departing from the true spirit and scope of the present disclosure as defined by the following claims. The drawings are not necessarily to scale. There can be differences between the technology reproduction in the present disclosure and the actual implementation due to variables in the manufacturing process, etc. There can be other embodiments of the present disclosure that are not specifically illustrated. The specification and drawings should be considered illustrative only and not restrictive of the disclosure. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations can be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not a limitation of the present disclosure.

Claims

1. A semiconductor packaging device, comprising: a bridge redistribution layer, comprising a high-density circuit area and a low-density circuit area; a first electronic component disposed under the bridge redistribution layer, a front surface of the first electronic component being provided with a first high-density input-output (I / O) area and a first low-density I / O area, the first high-density I / O area being electrically connected to the high-density circuit area through solder, and the first low-density I / O area being electrically connected to the low-density circuit area through wire bonding; a second electronic component disposed adjacent to the first electronic component, a front surface of the second electronic component being provided with a second high-density I / O area and a second low-density I / O area, the second high-density I / O area being electrically connected to the high-density circuit area; in a vertical direction, the first low-density I / O area is exposed from the bridge redistribution layer.

2. The apparatus of claim 1, wherein, the second low-density I / O area is electrically connected to the low-density circuit area through wire bonding.

3. The apparatus of claim 1 or 2, wherein, the bridge redistribution layer further comprises a via, and wire bonding connects the low-density circuit area through the via.

4. The apparatus of claim 3, wherein, a protective layer is provided on the bridge redistribution layer corresponding to the via, and the protective layer covers the wire bonding through the via.

5. The apparatus of claim 4, wherein, solder balls are provided on the low-density circuit area.

6. The apparatus of claim 1, wherein, a circuit layer is provided on the bridge redistribution layer, the circuit layer comprising a first via hole, and the first via hole electrically connects the bridge redistribution layer.

7. The apparatus of claim 6, wherein, the circuit layer further comprises a second via hole, and the second via hole electrically connects the second low-density I / O area.

8. The apparatus of claim 6, wherein, solder balls are provided on the circuit layer.

9. The apparatus of claim 1, wherein, underfill is provided between the first electronic component, the second electronic component, and the high-density circuit area.

10. The apparatus of claim 1, wherein, a via hole diameter of the first low-density I / O area is greater than a via hole diameter of the first high-density I / O area, and a via hole diameter of the second low-density I / O area is greater than a via hole diameter of the second high-density I / O area.

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