Semiconductor memory device

Abstract

A semiconductor storage device having a low resistance of an electrode film. The semiconductor storage device includes a first electrode film extending in a first direction; a second electrode film provided in a second direction of the first electrode film and extending in the first direction; a third electrode film provided in the second direction of the first electrode film and extending in the first direction; an insulating member provided between the second electrode film and the third electrode film and extending in the first direction; a first semiconductor member extending in the second direction and penetrating the first electrode film and the second electrode film; a second semiconductor member extending in the second direction and penetrating the first electrode film and the third electrode film; and a third semiconductor member extending in the second direction, a first portion of which is disposed between the second electrode film and the third electrode film and is in contact with the insulating member, and a second portion of which penetrates the first electrode film. In the first direction, the arrangement density of the third semiconductor member is lower than the arrangement density of the first semiconductor member and the arrangement density of the second semiconductor member.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on March 8, 2017, with application number 201710133175.3 and title "Semiconductor Memory Device".

[0003] [Related Applications]

[0004] This application enjoys priority to Japanese Patent Application No. 2016-217885 (filed on November 8, 2016). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0005] The implementation relates to a semiconductor memory device. Background Technology

[0006] In recent years, multilayer semiconductor memory devices that integrate memory cells three-dimensionally have been proposed. In such multilayer semiconductor memory devices, a multilayer structure is formed by alternately depositing electrode films and insulating films on a semiconductor substrate, and semiconductor pillars are provided penetrating the multilayer structure. Furthermore, memory cell transistors are formed at each intersection of the electrode films and semiconductor pillars. In such multilayer semiconductor memory devices, there is a problem that the resistance of the electrode films increases with increasing integration. Summary of the Invention

[0007] One embodiment provides a semiconductor memory device with a low resistance electrode film.

[0008] A semiconductor memory device according to an embodiment includes: a first electrode film extending along a first direction; a second electrode film disposed on the first electrode film in a second direction intersecting the first direction and extending along the first direction; a third electrode film disposed on the first electrode film in the second direction and extending along the first direction; an insulating member disposed between the second electrode film and the third electrode film and extending along the first direction; a first semiconductor member extending along the second direction and penetrating the first electrode film and the second electrode film; a second semiconductor member extending along the second direction and penetrating the first electrode film and the third electrode film; and a third semiconductor member extending along the second direction, wherein a first portion is disposed between the second electrode film and the third electrode film and is in contact with the insulating member, and a second portion penetrates the first electrode film. In the first direction, the arrangement density of the third semiconductor member is less than the arrangement density of the first semiconductor member and the arrangement density of the second semiconductor member. Attached Figure Description

[0009] Figure 1 This is a perspective view of a semiconductor memory device according to the first embodiment.

[0010] Figure 2 This is a top view showing the semiconductor memory device according to the first embodiment.

[0011] Figure 3 It is along Figure 2 The cross-sectional view of line A-A' shown.

[0012] Figure 4 It is along Figure 2 The cross-sectional view of line B-B' shown.

[0013] Figure 5 It means Figure 2 An enlarged top view of region C.

[0014] Figure 6 It means Figure 3 An enlarged sectional view of region D.

[0015] Figure 7 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment.

[0016] Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment.

[0017] Figure 9 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment.

[0018] Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment.

[0019] Figure 11 This is a top view of the semiconductor memory device of the first comparative example.

[0020] Figure 12 It is along Figure 11 The cross-sectional view of line E-E' shown.

[0021] Figure 13 This is a top view of the semiconductor memory device of the second comparative example.

[0022] Figure 14 This is a top view showing the semiconductor memory device according to the second embodiment.

[0023] Figure 15 This is a top view showing the semiconductor memory device according to the third embodiment.

[0024] Figure 16This is a top view showing the semiconductor memory device according to the fourth embodiment.

[0025] Figure 17 This is a top view showing the semiconductor memory device according to the fifth embodiment.

[0026] Figure 18 This is a top view showing the semiconductor memory device according to the sixth embodiment.

[0027] Figure 19 This is a top view showing the semiconductor memory device according to the seventh embodiment. Detailed Implementation

[0028] (First Implementation)

[0029] First, the first embodiment will be described.

[0030] Figure 1 This is a perspective view showing the semiconductor memory device according to this embodiment.

[0031] Figure 2 This is a top view showing the semiconductor memory device according to this embodiment.

[0032] Figure 3 It is along Figure 2 The cross-sectional view of line A-A' shown.

[0033] Figure 4 It is along Figure 2 The cross-sectional view of line B-B' shown.

[0034] Figure 5 It means Figure 2 A magnified top view of region C.

[0035] Figure 6 It means Figure 3 An enlarged sectional view of region D.

[0036] Furthermore, each figure is a schematic diagram, depicted with appropriate exaggeration and omission. For example, each component is depicted as fewer and larger than it actually is. In addition, the number of components and size ratios may not be consistent between different figures.

[0037] The semiconductor memory device in this embodiment is a multilayer NAND flash memory.

[0038] like Figure 1 As shown, in the semiconductor memory device 1 (hereinafter also simply referred to as "device 1") of this embodiment, a silicon substrate 10 is provided. The silicon substrate 10 is formed, for example, from a single crystal of silicon. A silicon oxide film 11 is provided on the silicon substrate 10.

[0039] For ease of explanation, the XYZ orthogonal coordinate system is used in this specification. The two directions parallel and orthogonal to the upper surface 10a of the silicon substrate 10 are designated as the "X direction" and the "Y direction," and the direction perpendicular to the upper surface 10a of the silicon substrate 10 is designated as the "Z direction." Furthermore, the direction in the Z direction from the silicon substrate 10 towards the silicon oxide film 11 is referred to as "up," and its opposite as "down," but this designation is for convenience and is independent of the direction of gravity.

[0040] Furthermore, in this specification, the term "silicon oxide film" refers to a film whose main component is silicon oxide (SiO), comprising silicon (Si) and oxygen (O). Similarly, for other constituent elements, if the name of a constituent element includes a material name, then the main component of that constituent element is that material. Additionally, silicon oxide is generally an insulating material, so unless otherwise specified, silicon oxide film is an insulating film. Likewise, for other components, as a principle, the characteristics of the component reflect the characteristics of the main component.

[0041] On a silicon oxide film 11, silicon oxide films 12 and electrode films 13 are alternately deposited along the Z direction. A stack 15 is formed by the silicon oxide film 11 and the alternately deposited silicon oxide films 12 and electrode films 13. The length direction of the stack 15 is the X direction. A source electrode plate 17 is disposed at a position in the Y direction, separating the stack 15. The lower end of the source electrode plate 17 is connected to the silicon substrate 10. The electrode film 13 is a strip extending along the X direction, with the longest length direction in the X direction, the second longest width direction in the Y direction, and the shortest thickness direction in the Z direction.

[0042] In device 1, a plurality of stacked layers 15 and a plurality of source electrode plates 17 are disposed and arranged alternately along the Y direction. Between the stacked layers 15 and the source electrode plates 17, for example, an insulating plate 18 comprising silicon oxide is disposed (see reference). Figure 2 ).

[0043] A columnar member 20 extending along the Z direction and penetrating the stacked layer 15 is disposed within the stacked layer 15. The lower end of the columnar member 20 is in contact with the silicon substrate 10, and the upper end is exposed on the upper surface of the stacked layer 15. As described below, a silicon pillar 30 (see reference) is disposed within each columnar member 20. Figure 5 and Figure 6 ).

[0044] A source line 21 extending along the Y direction and multiple bit lines 22 are disposed on the laminate 15. The source line 21 is disposed above the bit lines 22. The source line 21 is connected to the upper end of the source electrode plate 17 via a plug 24. In addition, the bit lines 22 are connected to the upper end of the silicon pillars 30 via plugs 23. Thus, a current path is formed (bit line 22-plug 23-silicon pillar 30-silicon substrate 10-source electrode plate 17-plug 24-source line 21), with each silicon pillar 30 connected between the bit line 22 and the source line 21.

[0045] In the stacked layer 15, one or more electrode films 13 from the top function as the upper select gate line (SGD), and each intersection of the upper select gate line (SGD) and the pillar member 20 constitutes an upper select gate transistor (STD). Similarly, one or more electrode films 13 from the bottom function as the lower select gate line (SGS), and each intersection of the lower select gate line (SGS) and the pillar member 20 constitutes a lower select gate transistor (STS). Electrode films 13 other than the lower select gate line (SGS) and the upper select gate line (SGD) function as word lines (WL), and each intersection of the word line (WL) and the pillar member 20 constitutes a memory cell transistor (MC). Thus, multiple memory cell transistors (MC) are connected in series along each silicon pillar 30, and lower select gate transistors (STS) and upper select gate transistors (STD) are connected to the two ends of these memory cell transistors (MC) to form a NAND string.

[0046] An insulating member 19 extending in the X direction is disposed at the central portion of the upper Y direction of the stacked layer 15, dividing the electrode film 13, which will become the upper select gate line SGD, into two parts in the Y direction. The insulating member 19 comprises, for example, silicon oxide. The insulating member 19 is strip-shaped. The insulating member 19 does not reach the electrode film 13, which becomes the word line WL, therefore, the electrode film 13, which becomes the word line WL, is not divided. Therefore, on a certain word line WL, two upper select gate lines SGD arranged at the same height are disposed. In other words, the insulating member 19 is disposed between the two upper select gate lines SGD arranged at the same height.

[0047] like Figure 2 As shown, the columnar members 20 are arranged approximately periodically along the XY plane. However, the periodicity is disrupted by omitting the columnar members 20 at the center of the laminate 15 in the Y direction.

[0048] More specifically, the columnar component 20 is positioned such that it includes a grid point Lp of an imaginary grid La set in the XY plane. The grid La is composed of multiple parallel imaginary lines L1 and multiple parallel imaginary lines L2. Line L1 is parallel to the XY plane and extends in a direction intersecting both the X and Y directions. Line L2 is also parallel to the XY plane and extends in a direction intersecting both the X and Y directions. Line L2 also intersects line L1.

[0049] For ease of explanation, the columnar member 20 located at the center of the laminate 15 in the Y direction, i.e., within the insulating member 19, will be referred to as "columnar member 20a". The columnar members 20a are arranged in a row along the X direction, dividing the insulating member 19. Furthermore, within a laminate 15, the columnar member 20 located on one side of the row formed by the columnar members 20a in the Y direction will be referred to as "columnar member 20b", and the columnar member 20 located on the other side of the Y direction will be referred to as "columnar member 20c". "Columnar member 20" will be the general term for columnar members 20a, 20b, and 20c. Figure 2 In the example shown, four columnar components 20b are arranged along a straight line L1, and four columnar components 20c are also arranged along a straight line L1. That is, in a laminate 15, four columns of columnar components 20b and 20c are arranged on each side of the insulating component 19.

[0050] Next, the positional relationship between each columnar component 20 and each electrode film 13 will be explained. The upper part of the columnar component 20a is disposed between two adjacent upper select gate lines SGD in the Y direction. The middle part of the columnar component 20a passes through the word line WL. The lower part of the columnar component 20a passes through the lower select gate line SGS. On the other hand, the upper part of the columnar component 20b passes through the upper select gate line SGD, the middle part passes through the word line WL, and the lower part passes through the lower select gate line SGS. The positional relationship between the columnar component 20c and each electrode film 13 is the same as that between the columnar component 20b and each electrode film 13.

[0051] Columnar members 20b and 20c are arranged at grid points Lp that are continuously arranged along the X direction. On the other hand, columnar member 20a is arranged at grid points Lp that are continuously arranged along the X direction, every few grid points. Figure 2In the example shown, columnar components 20a are arranged at a ratio of one per every three grid points Lp, with no columnar components 20a arranged at the remaining two grid points Lp. Therefore, the arrangement period Pa of columnar components 20a in the X direction is longer than the arrangement period Pb of columnar components 20b and Pc of columnar components 20c in the X direction. Furthermore, the arrangement period Pb is equal to the arrangement period Pc, i.e., Pa > Pb = Pc. The arrangement period Pa is an integer multiple of the arrangement periods Pb and Pc. Figure 2 In the example shown, it is 3 times. Therefore, the arrangement density of columnar component 20a in the X direction is less than the arrangement density of columnar component 20b and columnar component 20c in the X direction.

[0052] like Figures 2-4 As shown, the columnar member 20 is generally cylindrical in shape, but more specifically bowling ball shaped. That is, the diameter of the columnar member 20 reaches its maximum value at a position slightly below the top, continuously decreases upwards and downwards from that position, and reaches its minimum value at the bottom.

[0053] A void 28 is formed between the columnar members 20a in the electrode film 13. The void 28 is isolated from the silicon oxide film 12, the columnar members 20, and the insulating member 19. A gas containing fluorine (F) is, for example, sealed within the void 28. The void 28 is relatively large in the upper and middle parts of the laminate 15 and relatively small in the lower part. The formation of the void 28 depends on the manufacturing conditions of the device 1, and depending on the manufacturing conditions, there may be cases where the void 28 is not formed.

[0054] Additionally, the plug 24 is disposed on and connected to the silicon pillars 30 disposed in the pillar member 20b and the pillar member 20c, but not on the silicon pillars 30 disposed in the pillar member 20a. Therefore, the silicon pillars 30 disposed in the pillar member 20a are insulated from the bit line 22 and do not form a NAND string.

[0055] like Figure 5 and Figure 6 As shown, in the columnar component 20, a core component 29, a silicon pillar 30, a tunnel insulating film 31, a charge storage film 32, and a silicon oxide layer 33 are disposed from the central axis toward the peripheral surface. The core component 29 comprises silicon oxide and is approximately cylindrical with the Z-direction as its axial direction. The core component 29 is positioned at the central axis containing the columnar component 20. The silicon pillar 30 comprises polycrystalline silicon and is cylindrical, extending along the Z-direction and closed at its lower end. The tunnel insulating film 31 is disposed around the silicon pillar 30, the charge storage film 32 is disposed around the tunnel insulating film 31, and the silicon oxide layer 33 is disposed around the charge storage film 32. The tunnel insulating film 31, the charge storage film 32, and the silicon oxide layer 33 are all cylindrical with the Z-direction as their axial direction.

[0056] The tunnel insulating film 31 is generally insulating, but if a specific voltage within the range of the driving voltage of device 1 is applied, it becomes a film that allows tunneling current to pass through, for example, an ONO film formed by sequentially stacking silicon oxide layer 31a, silicon nitride layer 31b, and silicon oxide layer 31c. The charge storage film 32 is a film capable of storing charge, and contains, for example, a material containing electron trapping points, such as silicon nitride.

[0057] On the other hand, an aluminum oxide layer 34 is disposed on the surface of the electrode film 13. A barrier insulating film 35 is formed by the silicon oxide layer 33 and the aluminum oxide layer 34. The barrier insulating film 35 is a film that does not substantially allow current to flow even when a voltage is applied within the range of the driving voltage of the device 1. A memory film 36 is formed by the tunnel insulating film 31, the charge storage film 32, and the barrier insulating film 35. For example, the average nitrogen concentration of the charge storage film 32 is higher than the average nitrogen concentration of the tunnel insulating film 31 and the average nitrogen concentration of the barrier insulating film 35.

[0058] In the electrode film 13, a main body portion 38 containing tungsten (W) is provided, and a barrier metal layer 39 formed by stacked titanium (Ti) layers and titanium nitride (TiN) layers is provided on the surface of the main body portion 38. The main body portion 38 is in contact with the source electrode plate 17. The area of ​​the surface of the main body portion 38 other than the area in contact with the source electrode plate 17 is in contact with the barrier metal layer 39. The barrier metal layer 39 is in contact with the alumina layer 34.

[0059] Next, the manufacturing method of the semiconductor memory device according to this embodiment will be described.

[0060] Figures 7-10 This is a cross-sectional view showing the manufacturing method of the semiconductor memory device according to this embodiment.

[0061] Figures 7-10 It means equivalent to Figure 3 The cross section.

[0062] First, such as Figure 7 As shown, a silicon substrate 10 is prepared. Next, a silicon oxide film 11 is formed on the entire surface of the silicon substrate 10. Then, a silicon oxide film 12 and a silicon nitride film 51 are alternately formed on the silicon oxide film 11 to form a laminate 15.

[0063] Next, grooves 53 extending in the X direction are formed on the upper part of the multilayer 15 by, for example, photolithography. Multiple grooves 53 are formed and arranged periodically in the Y direction. The grooves 53 will be replaced with upper select gate lines (SGD) in subsequent steps (see reference). Figure 3 The predetermined silicon nitride film 51 is segmented and will not be replaced with word lines WL in subsequent steps (see reference). Figure 3 ) or lower gate selection line SGS (refer to Figure 3 The predetermined silicon nitride film 51 is cut. Then, silicon oxide is embedded in the trench 53 to form an insulating component 19.

[0064] Next, as Figure 8 As shown, a photoresist mask (not shown) is formed on the stacked layer 15 using photolithography, and anisotropic etching such as RIE (Reactive Ion Etching) is performed using this photoresist mask. This forms a memory hole 55 on the stacked layer 15. The memory hole 55 is approximately cylindrical in shape, extending along the Z-direction. The diameter of the memory hole 55 increases continuously downwards from the upper surface of the stacked layer 15, reaching its maximum value slightly below the upper surface, and then continuously decreases downwards from that position, reaching its minimum value on the lower surface of the stacked layer 15. The bottom surface of the memory hole 55 exposes the silicon substrate 10. The insulating member 19 is interrupted by a portion of the memory hole 55.

[0065] Next, as Figure 9 As shown, a columnar component 20 is formed within the memory hole 55. Specifically, an epitaxial silicon component (not shown) is formed by epitaxial growth of silicon starting from the silicon substrate 10 on the bottom surface of the memory hole 55.

[0066] Next, as Figure 5 and Figure 6 As shown, a silicon oxide layer 33 is formed on the inner surface of the memory hole 55. Next, a charge storage film 32 is formed by depositing silicon nitride. Then, a tunnel insulating film 31 is formed by sequentially depositing silicon oxide, silicon nitride, and silicon oxide to form a silicon oxide layer 31c, a silicon nitride layer 31b, and a silicon oxide layer 31a.

[0067] Next, a capping silicon layer (not shown) is formed by silicon deposition. RIE (Removal of Silicon Injection) is then performed to remove the capping silicon layer, tunnel insulating film 31, charge storage film 32, and silicon oxide layer 33, exposing the epitaxial silicon component. Next, a body silicon layer is formed by silicon deposition. The body silicon layer is bonded to the epitaxial silicon component and tunnel insulating film 31. A silicon pillar 30 is formed from the capping silicon layer and the body silicon layer. Next, a core component 29 is formed by silicon oxide deposition. A memory via 55 is embedded through the core component 29. In this manner, a pillar-shaped component 20 is formed.

[0068] Next, as Figure 9 As shown, a slit 57 is formed in the laminate 15. The slit 57 extends along the XZ plane and penetrates the laminate 15 in both the X and Z directions.

[0069] Next, as Figure 10 As shown, the silicon nitride film 51 (see figure) is deposited via slit 57 by performing a wet etching process, for example, using hot phosphoric acid. Figure 9The silicon oxide film 12, the insulating component 19, and the columnar component 20 are not actually removed, and the columnar component 20 supports the silicon oxide film 12. As a result, a space 59 is formed between the silicon oxide films 12.

[0070] Next, as Figures 2-6 As shown, aluminum oxide is deposited through slit 57 to form an aluminum oxide layer 34 on the inner surface of space 59. The aluminum oxide layer 34 is in contact with the silicon oxide layer 33, silicon oxide film 12, and insulating component 19 of columnar component 20. The silicon oxide layer 33 and aluminum oxide layer 34 constitute a barrier insulating film 35. The tunnel insulating film 31, charge storage film 32, and barrier insulating film 35 form a memory film 36.

[0071] Next, a barrier metal layer 39 is formed on the aluminum oxide layer 34 by depositing titanium nitride and titanium through the slit 57. Then, for example, tungsten is deposited into the space 59 through the slit 57 using CVD (Chemical Vapor Deposition) with tungsten hexafluoride gas (WF6) as the feed gas to form the main body 38. Next, tungsten, titanium, titanium nitride, and aluminum oxide are removed from the slit 57 by etching, leaving only the space 59. Thus, an electrode film 13 is formed within the space 59. In this way, the silicon nitride film 51 is replaced by the electrode film 13.

[0072] However, during the tungsten deposition step, the portion of space 59 located at the center of the stack 15 in the Y direction is difficult to deposit tungsten due to its distance from the slits 57 on both sides of the Y direction, and may not be completely embedded. In this case, voids 28 are formed within the electrode film 13. These voids 28 are primarily filled with a fluorine (F)-containing gas from the CVD feed gas (WF6).

[0073] In the upper and middle parts of the laminate 15 with relatively large diameter columnar components 20, tungsten is difficult to deposit due to the relatively short distance between the columnar components 20, thus voids 28 are easily formed. On the other hand, in the lower part of the laminate 15 with relatively small diameter columnar components 20, tungsten is easily deposited due to the relatively long distance between the columnar components 20, thus voids 28 are not easily formed. As a result, voids 28 formed in the lower part of the laminate 15 are mostly smaller than those formed in the middle and upper parts of the laminate 15. In addition, there are cases where voids 28 are formed in the middle and upper parts of the laminate 15, but not in the lower part of the laminate 15.

[0074] Next, silicon oxide is deposited to form an insulating plate 18 on the side of the slit 57. Then, a conductive material such as tungsten is deposited to form a source electrode plate 17 within the slit 57.

[0075] Next, as Figure 1As shown, a plug 23 is formed on the silicon pillar 30, and a plug 24 is formed on the source electrode plate 17. Next, a bit line 22 extending in the Y direction is formed and connected to the plug 23. Next, a source line 21 extending in the Y direction is formed and connected to the plug 24. In this manner, the semiconductor memory device 1 of this embodiment is manufactured.

[0076] Next, the effects of this embodiment will be explained.

[0077] In this embodiment, a columnar member 20a is provided at the center of the laminate 15 in the Y direction, thus reducing the size of each gap 28. Consequently, the resistance of the electrode film 13 in the X direction decreases. As a result, the operating speed of the semiconductor memory device 1 can be increased.

[0078] Furthermore, since the arrangement density of the columnar members 20a in the X direction is lower than that of the columnar members 20b and 20c in the X direction, fewer current paths are accommodated by the columnar members 20 at the central portion in the Y direction of the electrode film 13. This suppresses the increase in resistance of the electrode film 13 caused by the columnar members 20, thus reducing the resistance of the electrode film 13. Consequently, the operating speed of the semiconductor memory device 1 can also be improved.

[0079] Furthermore, by suppressing the formation of voids 28, the laminated body 15 is less prone to collapse. In addition, the laminated body 15 is also less prone to collapse by being supported by columnar members 20a, 20b, and 20c.

[0080] (First comparative example)

[0081] Next, the first comparative example will be explained.

[0082] Figure 11 This is a top view showing the semiconductor memory device of this comparative example.

[0083] Figure 12 It is along Figure 11 The cross-sectional view of line E-E' shown.

[0084] like Figure 11 and Figure 12 As shown, in the semiconductor memory device 101 of this comparative example, no columnar member 20a is provided at the central portion of the laminate 15 in the Y direction (see reference). Figure 2 Therefore, a large gap 28 is formed in the central part of the electrode film 13 in the Y direction. As a result, the semiconductor memory device 101 and the semiconductor memory device 1 (see reference 1) Figure 2 In contrast, electrode film 13 has higher resistance and lower operating speed. Furthermore, depending on the situation, the laminate 15 may collapse.

[0085] (Second Comparative Example)

[0086] Next, the second comparative example will be explained.

[0087] Figure 13 This is a top view showing the semiconductor memory device of this comparative example.

[0088] like Figure 13 As shown, in the semiconductor memory device 102 of this comparative example, columnar members 20a are provided at each grid point Lp of grid La in the central part of the stacked layer 15 in the Y direction. That is, the arrangement period Pa of columnar members 20a in the X direction is equal to the arrangement period Pb of columnar members 20b and the arrangement period Pc of columnar members 20c.

[0089] In the semiconductor memory device 102 of this comparative example, since it differs from the semiconductor memory device 1 of the first embodiment (see reference 1) Figure 2 Compared to the columnar components 20a, the columnar components 20a have a higher density, thus suppressing the formation of voids 28. However, the higher density of the columnar components 20a results in a correspondingly shorter effective width of the electrode film 13, i.e., its length in the Y direction. Therefore, the semiconductor memory device 102 and the semiconductor memory device 1 (see reference 1) have different densities. Figure 2 Compared to the previous method, the electrode film 13 has a higher resistance in the X direction.

[0090] (Second Implementation)

[0091] Next, the second embodiment will be described.

[0092] Figure 14 This is a top view showing the semiconductor memory device according to this embodiment.

[0093] like Figure 14 As shown, in the semiconductor memory device 2 of this embodiment, when viewed from the Z direction, the maximum diameter Da of the columnar member 20a is greater than the maximum diameter Db of the columnar member 20b and the maximum diameter Dc of the columnar member 20c. That is, Da > Db and Da > Dc. Furthermore, when the shape of the columnar member 20 is not a perfect circle when viewed from the Z direction, the diameter of the circumscribed circle of the columnar member 20 is set as the maximum diameter.

[0094] In the first embodiment, columnar component 20a differs from columnar components 20b and 20c in that it is not arranged at each grid point Lp of grid La (refer to...). Figure 2 Therefore, in Figure 8 In the photolithography steps shown, depending on the conditions, there are cases where it is difficult to form the memory hole 55 used to form the columnar component 20a.

[0095] Therefore, in this embodiment, the memory hole 55 used to form the columnar member 20a is set to be larger than the memory hole 55 used to form the columnar members 20b and 20c. This facilitates the formation of the memory hole 55. However, as a result, in the manufactured semiconductor memory device 2, there is a case where the maximum diameter of the columnar member 20a becomes larger than the maximum diameter of the columnar member 20b and the maximum diameter of the columnar member 20c. Furthermore, since the columnar member 20a does not form a memory cell transistor MC, its electrical characteristics do not need to be considered. The configuration, manufacturing method, and effects in this embodiment are the same as in the first embodiment, except as described above.

[0096] (Third Implementation)

[0097] Next, the third embodiment will be described.

[0098] Figure 15 This is a top view showing the semiconductor memory device according to this embodiment.

[0099] like Figure 15 As shown, in the semiconductor memory device 3 of this embodiment, regions Ra and Rb are arranged alternately along the X direction. The length of region Rb in the X direction is longer than the length of region Ra in the X direction. Furthermore, as explained in the sixth embodiment below, the length of region Rb may be shorter than the length of region Ra, or the length of region Rb may be equal to the length of region Ra. In this embodiment, multiple, for example, three columnar members 20a are provided in region Ra. For example, in region Ra, columnar members 20a are provided at each grid point Lp (see reference). Figure 2 In this case, in region Ra, the arrangement period Pa of columnar member 20a in the X direction is approximately equal to the arrangement period Pb of columnar member 20b and the arrangement period Pc of columnar member 20c. On the other hand, in region Rb, columnar member 20a is not provided. Columnar members 20b and 20c are periodically provided throughout both regions Ra and Rb.

[0100] According to this embodiment, in region Ra, at each grid point Lp (refer to...) Figure 2 A columnar component 20a is provided. Therefore, in order to form the memory hole 55 (refer to...) Figure 8 This facilitates photolithography. As a result, memory holes 55 and columnar components 20a can be stably formed. The configuration, manufacturing method, and effects in this embodiment are the same as in the first embodiment, except as described above.

[0101] (Fourth Implementation)

[0102] Next, the fourth embodiment will be described.

[0103] Figure 16 This is a top view showing the semiconductor memory device according to this embodiment.

[0104] like Figure 16 As shown, in the semiconductor memory device 4 of this embodiment, region Ra is located directly below the source line 21, and region Rb is located in a region other than the region directly below the source line 21. Therefore, the pillar-shaped member 20a is disposed between the silicon substrate 10 and the source line 21.

[0105] According to this embodiment, a pillar-shaped member 20a that does not form a NAND string and therefore does not form a memory cell transistor MC is disposed in the region directly below the source line 21. Since bit lines 22 cannot be disposed in the region where the source line 21 is formed, the pillar-shaped member 20a disposed in the region directly below the source line 21 cannot form a NAND string. Therefore, according to this embodiment, the formation of gaps 28 can be suppressed by effectively utilizing idle space to arrange the pillar-shaped member 20a. The configuration, manufacturing method, and effects in this embodiment are the same as those in the third embodiment, except as described above.

[0106] (Fifth Implementation)

[0107] Next, the fifth embodiment will be described.

[0108] Figure 17 This is a top view showing the semiconductor memory device according to this embodiment.

[0109] like Figure 17 As shown, in the semiconductor memory device 5 of this embodiment, a memory cell region Rm is provided, and stepped regions Rs are provided on both sides of the memory cell region Rm in the X direction. In the memory cell region Rm, a stacked layer 15 is provided up to the top layer, and columnar members 20 are provided in a manner that penetrates the stacked layer 15 to form a plurality of memory cell transistors MC.

[0110] On the other hand, in the stepped region Rs, the laminate 15 is processed into a stepped shape, with a stepped surface T formed on each electrode film 13. A support member 40 is provided in the stepped region Rs. The support member 40 is generally cylindrical in shape, extending along the Z direction, and extends through the laminate 15, with its lower end contacting the silicon substrate 10. The structure of the support member 40 is the same as that of the columnar member 20. In addition, a contact 41 is provided on the laminate 15 in the stepped region Rs. The lower end of the contact 41 is connected to the electrode film 13 at the stepped surface T. No memory cell transistor MC is formed in the stepped region Rs.

[0111] Furthermore, region Ra is positioned within the memory cell region Rm, adjacent to the stepped region Rs. Additionally, region Rb is also positioned within the memory cell region Rm. Region Ra is located between the stepped region Rs and region Rb. As described above, the columnar member 20a is positioned only in region Ra. Alternatively, region Ra may also be positioned at other locations within the memory cell region Rm. Therefore, the distance da between region Ra and contact 41 is shorter than the distance db between region Rb and contact 41. That is, da < db.

[0112] Furthermore, the boundary between region Ra and region Rb can be defined as the YZ plane, which contains two adjacent grid points Lp in the X direction (refer to...). Figure 2 Furthermore, the midpoint between the grid point Lp with the columnar member 20a and the grid point Lp without the columnar member 20a is defined as follows: the boundary between the memory cell region Rm and the stepped region Rs can be defined as a YZ plane that includes the grid point Lp contained in the columnar member 20 at the far end in the X direction, and the midpoint between the grid point Lp adjacent to it in the X direction and the grid point Lp without the columnar member 20.

[0113] According to this embodiment, a columnar member 20a that does not form a memory cell transistor MC is disposed in the region of the memory cell region Rm that is connected to the stepped region Rs. However, the columnar member 20a disposed in this region is originally formed as a dummy component and does not constitute a memory cell transistor MC. Therefore, according to this embodiment, the formation of gaps 28 can be suppressed by effectively utilizing the idle space to arrange the columnar member 20a. The configuration, manufacturing method, and effects of this embodiment are the same as those of the third embodiment, except as described above.

[0114] (Sixth Implementation Method)

[0115] Next, the sixth embodiment will be described.

[0116] Figure 18 This is a top view showing the semiconductor memory device according to this embodiment.

[0117] like Figure 18 As shown, in the semiconductor memory device 6 of this embodiment, in the X direction, the length of the region Rb where the columnar member 20a is not provided is shorter than the length of the region Ra where the columnar member 20a is provided. Therefore, the same effect as in the third embodiment can be obtained. Except for the above description, the configuration, manufacturing method, and effects in this embodiment are the same as in the third embodiment.

[0118] (Seventh Implementation)

[0119] Next, the seventh embodiment will be described.

[0120] Figure 19 This is a top view showing the semiconductor memory device according to this embodiment.

[0121] like Figure 19 As shown, in the semiconductor memory device 7 of this embodiment, six columnar members 20b are arranged along a straight line L1, and six columnar members 20c are also arranged along a straight line L1.

[0122] According to this embodiment, in a multilayer 15, six rows of columnar members 20b and 20c are arranged on each side of the insulating member 19. Therefore, compared with the semiconductor memory device 1 of the first embodiment (see reference 1), Figure 2 Compared to the first embodiment, the memory cell transistor (MC) has a higher integration density. On the other hand, in this embodiment, the central portion of the laminate 15 in the Y direction is further away from the slit 57, and there are more columnar members 20 between the central portion in the Y direction and the slit 57, making it more difficult for the material of the electrode film 13 to reach. As a result, gaps 28 are more easily formed. Therefore, the effect of providing columnar members 20a in the central portion of the laminate 15 in the Y direction is greater. The configuration, manufacturing method, and effects in this embodiment are the same as in the first embodiment, except as described above.

[0123] According to the embodiments described above, a semiconductor memory device with low resistance of the electrode film can be realized.

[0124] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims. Furthermore, the embodiments described can be combined with each other.

[0125] [Explanation of Symbols]

[0126] 1-7 Semiconductor memory devices

[0127] 10 Silicon substrate

[0128] 10a Upper surface

[0129] 11. Silica film

[0130] 12 Silica film

[0131] 13 Electrode film

[0132] 15. Laminated bodies

[0133] 17 Source electrode plate

[0134] 18 Insulation Board

[0135] 19 Insulating components

[0136] 20, 20a, 20b, 20c Columnar components

[0137] 21 Source Line

[0138] 22-bit line

[0139] 23. Plug

[0140] 24 Plugs

[0141] 28 gaps

[0142] 29 core components

[0143] 30 silicon pillars

[0144] 31 Tunnel insulation film

[0145] 31a Silicon oxide layer

[0146] 31b silicon nitride layer

[0147] 31c silicon oxide layer

[0148] 32 Charge storage membrane

[0149] 33 Silicon oxide layer

[0150] 34 Alumina layer

[0151] 35 Barrier Insulating Film

[0152] 36. Memory membrane

[0153] 38 Main body

[0154] 39 barrier metal layer

[0155] 40 Support components

[0156] 41 contacts

[0157] 51 Silicon nitride film

[0158] 53 slots

[0159] 55 memory holes

[0160] 57 Slit

[0161] 59 Space

[0162] 101, 102 Semiconductor memory devices

[0163] Maximum diameters of Da, Db, and Dc

[0164] Lines L1 and L2

[0165] La grid

[0166] Lp grid points

[0167] MC memory cell transistor

[0168] Pa, Pb, Pc arrangement period

[0169] Ra, Rb regions

[0170] Rm memory cell region

[0171] Rs stepped area

[0172] SGD upper select gate line

[0173] SGS Lower Select Gate Line

[0174] STD upper gate select transistor

[0175] STS (Lower Select Gate Transistor)

[0176] T-step

[0177] WL lettering

[0178] da, db distance

Claims

1. A semiconductor memory device, characterized in that... have: A first electrode film extends along a first direction; The second electrode film is disposed on the first electrode film in a second direction orthogonal to the first direction, and extends along the first direction; The third electrode film is disposed in the second direction of the first electrode film, and in a third direction of the second electrode film that is orthogonal to the first direction and the second direction, and extends along the first direction; An insulating component is disposed between the second electrode film and the third electrode film and extends along the first direction; A first semiconductor component is arranged in a first period along the first direction, extends along the second direction, and penetrates the first electrode film and the second electrode film; The second semiconductor component is arranged in a first period along the first direction, extends along the second direction, and penetrates the first electrode film and the third electrode film; A third semiconductor component is arranged along the first direction with a second period longer than the first period, disposed in the second direction of the insulating component, extending along the second direction and penetrating the first electrode film; A first insulating film is disposed between the first semiconductor component and the first electrode film; A second insulating film is disposed between the first semiconductor component and the first insulating film; as well as A third insulating film is disposed between the first insulating film and the first electrode film; and The nitrogen concentration of the first insulating film is higher than that of the second insulating film and the third insulating film.

2. The semiconductor memory device according to claim 1, characterized in that: The second period is an integer multiple of the first period.

3. The semiconductor memory device according to claim 1, characterized in that: Viewed from the second direction, the maximum diameter of the third semiconductor component is greater than the maximum diameter of the first semiconductor component and the maximum diameter of the second semiconductor component.

4. The semiconductor memory device according to claim 1, characterized in that... It also includes wiring, which extends along the third direction, and The first semiconductor component and the second semiconductor component are connected to the wiring, and the third semiconductor component is insulated from the wiring.

5. The semiconductor memory device according to claim 1, characterized in that: The first semiconductor component, the second semiconductor component, and the third semiconductor component are arranged in a grid pattern comprising: a plurality of imaginary first straight lines extending along the third direction and arranged periodically; and a plurality of imaginary second straight lines extending along a fourth direction intersecting the plane containing the first direction and the second direction and the third direction, and arranged periodically.

6. The semiconductor memory device according to claim 1, characterized in that: In the third direction, four of the first semiconductor components are arranged, and four of the second semiconductor components are arranged.

7. The semiconductor memory device according to claim 1, characterized in that: Six of the first semiconductor components are arranged in the third direction, and six of the second semiconductor components are arranged in the third direction.

8. The semiconductor memory device according to claim 1, characterized in that: A void is formed between the third semiconductor components in the first electrode film.

9. The semiconductor memory device according to claim 8, characterized in that: The gap is isolated from the first semiconductor component, the second semiconductor component, and the third semiconductor component.

10. A semiconductor memory device, characterized in that... have: A first electrode film extends along a first direction; The second electrode film is disposed on the first electrode film in a second direction orthogonal to the first direction, and extends along the first direction; The third electrode film is disposed in the second direction of the first electrode film, and in a third direction of the second electrode film that is orthogonal to the first direction and the second direction, and extends along the first direction; An insulating component is disposed between the second electrode film and the third electrode film and extends along the first direction; A first semiconductor component is arranged in a first period along the first direction, extends along the second direction, and penetrates the first electrode film and the second electrode film; The second semiconductor component is arranged in a first period along the first direction, extends along the second direction, and penetrates the first electrode film and the third electrode film; A third semiconductor component is disposed in the second direction of the insulating component, extends along the second direction, and penetrates the first electrode film; A first insulating film is disposed between the first semiconductor component and the first electrode film; A second insulating film is disposed between the first semiconductor component and the first insulating film; as well as A third insulating film is disposed between the first insulating film and the first electrode film; and In the first region, the third semiconductor components are arranged along the first direction at the first period. In a second region located in the first direction of the first region, and whose length in the first direction is longer than the first period, the first semiconductor component and the second semiconductor component are disposed, but the third semiconductor component is not disposed. The nitrogen concentration of the first insulating film is higher than that of the second insulating film and the third insulating film.

11. The semiconductor memory device according to claim 10, characterized in that... It also has: substrate; Wiring, disposed in the first region and extending along the third direction; and A conductive component is connected between the substrate and the wiring; and The third semiconductor component is disposed between the substrate and the wiring.

12. The semiconductor memory device according to claim 10, characterized in that... It also includes a contact point connected to the end of the second electrode film in the first direction, and The distance between the first region and the connection point is shorter than the distance between the second region and the connection point.

13. The semiconductor memory device according to claim 10, characterized in that: The length of the second region in the first direction is longer than the length of the first region in the first direction.

14. The semiconductor memory device according to claim 10, characterized in that: The length of the second region in the first direction is shorter than the length of the first region in the first direction.

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