A timing method, device and storage medium

Abstract

The present application discloses a timing method, which relates to the technical field of timing, and solves the problems in the prior art that CPU timing is inaccurate, hardware does not support timing using 1PPS output function, and timing accuracy requirements are not high. The method comprises: setting the delay error of the timing statement to DTime 1 ; Continuously receive the current time in multiple timing statements, and record the current time as Time 1 ,Time 2 , ..., Time n ; Calculate the time interval between two adjacent current times, determine whether the time interval is greater than the threshold, if it is greater than the threshold, restart recording until the time interval is less than the threshold; if the time interval meets the judgment condition, record the current time as the time value of the next reception Time n+1 ; The updated time is: second upper time + second lower time + serial port output statement delay error; among which, second upper time is Time n The time extracted from the timing statement received at the moment. The time in seconds is Time n+1 ‑Time n , achieving high timing accuracy and low hardware requirements. Only a simple microcontroller is needed to complete the timing, which is low cost and easy to use.

Description

Technical Field

[0001] The present application relates to the field of timing technology, and in particular to a timing method, device and storage medium. Background Art

[0002] The traditional timing scheme is that after the device is powered on, the CPU uses the RTC circuit to run the time, and the timing statement is received through the UART (serial port) at the rising edge of 1PPS to calibrate the time of the RTC circuit. That is, the RTC time is adjusted at the whole second, and the receiver or timing board outputs the timing statement through the UART.

[0003] In the existing technology, in order to achieve accurate timing, the CPU must be connected to the RTC circuit or a CPU with integrated RTC function, and the receiver or timing board must have the 1PPS function.

[0004] The existing problems in the prior art are that the CPU timing is inaccurate, the hardware does not support the use of 1PPS output function for timing, and the timing accuracy requirement is not high. Summary of the invention

[0005] The embodiment of the present application solves the problems in the prior art of inaccurate CPU timing, hardware not supporting the use of 1PPS output function for timing, and low timing accuracy requirements by providing a timing method, thereby achieving high timing accuracy and low hardware requirements. Only a simple single-chip microcomputer is needed to complete the timing, which is low cost and easy to use.

[0006] In a first aspect, an embodiment of the present invention provides a timing method, the method comprising:

[0007] Set the delay error of the timing statement to DTime1;

[0008] Continuously receive the current time in multiple timing statements, and record the current time as Time1, Time2, ..., Time n ;

[0009] Calculate the time interval between two adjacent current times, determine whether the time interval is greater than a threshold, and restart recording if the time interval is greater than the threshold until the time interval is less than the threshold;

[0010] If the time interval meets the judgment condition, the current time is recorded as the time value of the next reception. n+1 ;

[0011] The updated time is: the second upper time + the second lower time + the serial port output statement delay error; where the second upper time is Time n The time when the timing statement is extracted, the time in seconds is Timen+1 -Time n .

[0012] In combination with the first aspect, in a possible implementation manner, the timing statement delay error DTime1=1 / baud rate*timing statement character string length*8.

[0013] In combination with the first aspect, in a possible implementation manner, the continuously receiving the current time in the plurality of timing statements includes: receiving the timing statements output before the position is solved.

[0014] In combination with the first aspect, in a possible implementation manner, the continuously receiving the current time in the plurality of timing statements includes: continuously receiving the current time in at least three of the timing statements.

[0015] In combination with the first aspect, in a possible implementation, the second-down moment includes eliminating software processing delay.

[0016] In combination with the first aspect, in a possible implementation manner, the frequency of outputting the timing statement is 1 Hz.

[0017] In a second aspect, an embodiment of the present invention provides a timing device, including:

[0018] The error setting module is used to set the delay error of the timing statement to DTime1;

[0019] The current time recording module is used to continuously receive the current time in multiple timing statements and record the current time as Time1, Time2, ..., Time n ;

[0020] A time interval comparison module, used for calculating the time interval between two adjacent current times, judging whether the time interval is greater than a threshold, and restarting recording if the time interval is greater than the threshold until the time interval is less than the threshold;

[0021] The current time determination module is used to record the current time as the time value Time of the next reception if the time interval meets the judgment condition. n+1 ;

[0022] The time determination module of the timing service, the updated time is: the second upper time + the second lower time + the serial port output statement delay error; wherein, the second upper time is Time n The time when the timing statement is extracted, the second time is = Time n+1 -Time n .

[0023] In combination with the second aspect, in a possible implementation, the error setting module includes a delay error calculation unit, which calculates the delay error according to DTime1=1 / baud rate*timing statement string length*8.

[0024] In combination with the second aspect, in a possible implementation manner, the current time recording module includes a receiving time determination unit, which is used to receive the timing statement output before the position is solved.

[0025] In combination with the second aspect, in a possible implementation, the current time recording module includes a time number counting unit, which is used to continuously receive the current time in at least three of the timing statements.

[0026] In combination with the second aspect, in a possible implementation, the timing time determination module includes a delay elimination unit for eliminating software processing delay.

[0027] In a third aspect, an embodiment of the present invention provides a timing server, including a memory and a processor;

[0028] The memory is used to store computer executable instructions;

[0029] The processor is used to execute the computer executable instructions to implement the method described in the first aspect.

[0030] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores executable instructions, and when a computer executes the executable instructions, the method described in the first aspect can be implemented.

[0031] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0032] The embodiment of the present invention adopts a timing method, including: setting the delay error of the timing statement as DTime1; continuously receiving the current time in multiple timing statements, recording the current time as Time1, Time2, ..., Time n ; Calculate the time interval between two adjacent current times, determine whether the time interval is greater than the threshold, if it is greater than the threshold, restart recording until the time interval is less than the threshold; if the time interval meets the judgment condition, record the current time as the time value of the next reception Time n+1 ; The updated time is: second upper time + second lower time + serial port output statement delay error; among which, second upper time is Time n The time extracted from the timing statement received at the moment. The time in seconds is Time n+1 -Time nIt effectively solves the problems in the prior art of inaccurate CPU timing, hardware not supporting the use of 1PPS output function timing, and low timing accuracy requirements. It achieves high timing accuracy and low hardware requirements. Only a simple single-chip microcomputer is needed to complete the timing, which is low cost and easy to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments of the present invention or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A flowchart of a timing method provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of hardware connection in the prior art of a timing method provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of the hardware connection of a timing method provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the ZDA data format of a timing method provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of ZDA data reception in a timing method provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a UTC time calibration process of a timing method provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a timing device provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of a timing server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The traditional timing scheme is that after the device is powered on, the CPU uses the RTC circuit to run the time, and the timing statement is received through the UART (serial port) at the rising edge of 1PPS to calibrate the time of the RTC circuit. That is, the RTC time is adjusted at the whole second, and the receiver or timing board outputs the timing statement through the UART.

[0044] In the existing technology, in order to achieve accurate timing, the CPU must be connected to the RTC circuit or a CPU with integrated RTC function, and the receiver or timing board must have the 1PPS function.

[0045] Traditional timing schemes such as Figure 2 As shown in the figure, after the device is powered on, the CPU uses the RTC circuit to calibrate the time of the RTC circuit by receiving the timing statement through the UART (serial port) at the rising edge of 1PPS. That is, the RTC time is adjusted at the whole second. The receiver or timing card board outputs the timing statement through the UART, such as the ZDA statement. The ZDA statement contains the time.

[0046] The objective disadvantage of the prior art is that in order to achieve accurate timing, the CPU must be connected to the RTC circuit or the CPU with integrated RTC function, and the receiver or timing card must have the 1PPS function. This technology has the following defects: (1) There are errors in the timing process of the CPU; (2) The hardware does not support the use of the 1PPS function for timing; (3) The timing accuracy requirement is not high, and the ms level can meet the requirements, such as the airborne Beidou position tracking equipment.

[0047] Based on the above problems, the present invention provides a timing method, such as Figure 1 The steps shown include:

[0048] Step S101, setting the delay error of the timing statement to DTime1.

[0049] Step S102, continuously receive the current time in multiple timing statements, and record the current time as Time1, Time2, ..., Time n .

[0050] Step S103, calculating the time interval between two adjacent current times, and determining whether the time interval is greater than a threshold. If it is greater than the threshold, restarting the recording until the time intervals are all less than the threshold.

[0051] Step S104: If the time interval meets the judgment condition, record the current time as the time value Time for the next reception. n+1 .

[0052] Step S101, the updated time is: the second upper time + the second lower time + the serial port output statement delay error; where the second upper time is Time nThe time extracted from the timing statement received at the moment. The time in seconds is Time n+1 -Time n .

[0053] In the above steps, the delay error caused by the instability of the program running time of the position solution is eliminated, and multiple timing times are recorded until the calculated time intervals are all less than the threshold, reducing the timing error caused by the inaccurate current time received. The problem of inaccurate CPU timing, hardware not supporting the use of 1PPS output function timing, and low timing accuracy requirements in the prior art is effectively solved, and high timing accuracy is achieved, and the requirements for hardware are low. Only a simple single-chip microcomputer is needed to complete the timing, which is low in cost and easy to use.

[0054] like Figure 3 As shown in the figure, it is a specific scheme of this patent. According to the figure, only the UART serial port needs to be connected between the receiver and the single-chip microcomputer, and the CPU can be implemented by a simple and fast single-chip microcomputer, using the TIMER inside the single-chip microcomputer. In a preferred scheme of this application, the timely reference in the single-chip microcomputer is 1ms. The main errors in the above scheme are as follows.

[0055] (1) Generally speaking, the ZDA statement is output by the receiver after the position is solved. Because the program running time of the position solution is uncertain, there is an error of Dtime0. In conjunction with the first aspect, in a possible implementation, continuously receiving the current time in multiple timing statements includes: receiving the timing statement output before the position is solved.

[0056] (2) Serial port output statement delay error. The format of the ZDA statement is fixed, such as Figure 4 As shown, the timing statement delay error is also a constant. Combined with the first aspect, in a possible implementation, the timing statement delay error DTime1=1 / baud rate*timing statement string length*8.

[0057] (3) The long-term drift of the microcontroller crystal oscillator. If the crystal oscillator is 20ppm, it may be delayed or advanced by 1.7s in 24 hours. This error is recorded as Dtime2.

[0058] In this application, the output time of the receiver ZDA statement is dynamically adjusted with 1PPS. Therefore, this feature can be used to calibrate the local elimination Dtime2, and then calibrate the local UTC time. The specific solution is as follows.

[0059] In a possible implementation manner, continuously receiving the current time in multiple timing statements includes: continuously receiving the current time in at least three timing statements.

[0060] In one possible implementation, the second-down moment includes eliminating software processing delays.

[0061] In a possible implementation, the frequency of outputting the timing sentences is 1 Hz.

[0062] ① The initial UTC time when the machine is turned on is 0 year 0 month 0 day, 0 hour 0 minute 0 second 0 millisecond, and the internal TIMER of the microcontroller is used for timing, and the unit is 1ms;

[0063] ②The output frequency of ZDA timing statement is 1HZ;

[0064] ③Use the 1ms timing inside the microcontroller, and when the serial port receiving interrupt receives the ZDA statement and determines that the positioning mark is valid, record the current timing values ​​as Time1, Time2, ..., Time n In a preferred embodiment of the present application, the value of n is 5. If the interval between two ZDAs is greater than 1s±50ms, the timing is restarted. For example, if the interval between Time2 and Time3 is greater than 1s±50ms, the timing is restarted from Time3 until 5 ZDAs with valid positioning identifiers are received in succession and the interval is less than 1s±10ms before the next step is performed. Figure 4 As shown in the figure, Time1, Time2, Time3, Time4, Time5, and Time6 are all local 1ms timings.

[0065] ④ When the above conditions are met, the current time is recorded as Time6, and the updated UTC time is the second upper time + second lower time + serial port output statement delay error; wherein, the second upper time is Time n The time when the timing statement received at the time is extracted, and the second time is Time6-Time5. ;

[0066] Seconds time = Seconds time extracted from the ZDA statement received at Time5;

[0067] Seconds time = Time6-Time5;

[0068] The data received by the ZDA statement is as follows: Figure 5 As shown in the figure, when the positioning identifier of the ZDA statement is invalid, the UTC time is not adjusted and the local 1ms clock continues to run.

[0069] The specific flow chart for calibrating the local UTC time is as follows Figure 6 As shown, as mentioned above, in this patent, the method of using software timing is mainly solved, including the program running time error Dtime0 of position solution, the timing statement delay error DTime1, the CPU clock crystal drift and the processing delay Dtime2.

[0070] Generally, the receiver performs position calculation on the rising edge of 1PPS, because the running time of the position calculation program is affected by the number of satellites involved in positioning, the amount of data, etc., and the running time is uncertain. Therefore, the receiver can be constrained to output the ZDA statement on the serial port before the position calculation, and the output of ZDA is consistent with the rising edge of 1PPS. This method can eliminate the error Dtime0. Because the solution requires time calibration in the positioning state, Dtime0 is basically a fixed value. If the receiver software cannot be changed, Dtime0 can be ignored.

[0071] The delay error DTime1 of the timing statement can be calculated according to the baud rate as DTime1 = (1 / baud rate * ZDA string length * 8). This method can eliminate this error without considering any hardware delay.

[0072] In order to obtain a stable timing state, the time is calibrated when the receiver is in the positioning state. The clock is not calibrated when it is not positioned. Therefore, the MCU in the scheme calibrates the UTC time only when it receives 5 ZDA statements with valid positioning identifiers in succession and the interval is less than 1s±50ms. Time6-Time5 is to eliminate the software processing delay of the MCU.

[0073] Through the above analysis, the timing accuracy can be controlled within 50ms. In the process of sending short messages of airborne position tracking equipment, the minute card is used, and the timing needs to be 1 minute. The timing accuracy does not need to be very high. In this case of low-precision timing, a single-chip microcomputer without RTC circuit can be used to replace the CPU. The receiver and timing board can also use boards without 1PPS function. Simplify the hardware and reduce costs.

[0074] The embodiment of the present invention provides a timing device, including: an error setting module 701, a current time recording module 702, a time interval comparison module 703, a current time determination module 704, and a timing time determination module 705. The error setting module 701 is used to set the delay error of the timing statement as DTime1. The current time recording module 702 is used to continuously receive the current time in multiple timing statements, and record the current time as Time1, Time2, ..., Time n The time interval comparison module 703 is used to calculate the time interval between two adjacent current times and determine whether the time interval is greater than the threshold. If it is greater than the threshold, the recording is restarted until the time interval is less than the threshold. The current time determination module 704 is used to record the current time as the time value Time of the next reception if the time interval meets the judgment condition. n+1 The time determination module 705 updates the time as follows: the upper time in seconds + the lower time in seconds + the delay error of the serial port output statement; where the upper time in seconds is Time nThe time extracted from the timing statement received at the moment. The time in seconds is = Time n+1 -Time n .

[0075] In a possible implementation, the error setting module 701 includes a delay error calculation unit, which calculates the delay error according to DTime1=1 / baud rate*length of the timing statement string*8.

[0076] In a possible implementation, the current time recording module 702 includes a receiving time determination unit, which is used to receive a timing statement output before the position is solved.

[0077] In a possible implementation, the current time recording module 702 includes a time number counting unit, which is used to continuously receive the current time in at least three timing statements.

[0078] In a possible implementation, the timing time determination module 705 includes a delay elimination unit for eliminating software processing delay.

[0079] Although the present application provides method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in this embodiment is only one way of executing the order of many steps and does not represent the only execution order. When the actual device or client product is executed, it can be executed in sequence or in parallel according to the method shown in this embodiment or the accompanying drawings (for example, in a parallel processor or multi-threaded processing environment).

[0080] The devices or modules described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. For the convenience of description, the above devices are described in various modules according to their functions. When implementing this application, the functions of each module can be implemented in the same or multiple software and / or hardware. Of course, the module that implements a certain function can also be implemented by combining multiple sub-modules or sub-units.

[0081] The embodiment of the present invention provides a timing server, such as Figure 8 The system shown includes a memory 801 and a processor 802 ; the memory 801 is used to store computer executable instructions; the processor 802 is used to execute the computer executable instructions to implement the above method.

[0082] An embodiment of the present invention provides a computer-readable storage medium, which stores executable instructions. When a computer executes the executable instructions, the above method can be implemented.

[0083] The above storage media include but are not limited to random access memory (RAM), read-only memory (ROM), cache, hard disk (HDD) or memory card. The memory can be used to store computer program instructions.

[0084] The methods, devices or modules described in this application can be implemented in the form of computer-readable program codes. The controller can be implemented in any appropriate manner. For example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program codes (such as software or firmware) that can be executed by the (micro) processor, logic gates, switches, application-specific integrated circuits (English: Application Specific Integrated Circuit; Abbreviation: ASIC), programmable logic controllers and embedded microcontrollers. Examples of controllers include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code, the controller can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included in it for implementing various functions can also be regarded as structures within the hardware component. Or even, the means for realizing various functions may be regarded as both a software module for realizing the method and a structure within a hardware component.

[0085] Some modules in the apparatus described in the present application can be described in the general context of computer executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0086] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary hardware. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, or it can be reflected in the implementation process of data migration. The computer software product can be stored in a storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a mobile terminal, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0087] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. All or part of this application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, mobile communication terminals, multi-processor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0088] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit the present application. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some or all of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present application.

Claims

1. A timing method, characterized in that: include: Set the delay error of the timing statement to DTime1; Continuously receive the current time in multiple timing statements, and record the current time as Time1, Time2, ..., Time n ; Calculate the time interval between two adjacent current times, determine whether the time interval is greater than a threshold, and restart recording if the time interval is greater than the threshold until the time interval is less than the threshold; If the time interval meets the above judgment conditions, the current time is recorded as the time value of the next reception. n+1 ; The updated time is determined as: the second upper time + the second lower time + the delay error of the timing statement; wherein the second upper time is Time n The time when the timing statement is extracted when received, and the time in seconds is Time n+1 -Time n ; The time delay error DTime1 of the timing statement = 1 / baud rate*length of the timing statement string*8; The continuously receiving the current time in the plurality of timing statements includes: receiving the timing statements output before the position is solved.

2. The method according to claim 1, characterized in that: The continuously receiving the current time in the plurality of timing statements includes: continuously receiving the current time in at least three timing statements.

3. The method according to claim 1, characterized in that: The second-down time includes eliminating software processing delays.

4. The method according to claim 1, characterized in that: The frequency of the timing statement output is 1 Hz.

5. A timing device, characterized in that: include: The error setting module is used to set the delay error of the timing statement to DTime1; The current time recording module is used to continuously receive the current time in multiple timing statements and record the current time as Time1, Time2, ..., Time n ; A time interval comparison module, used for calculating the time interval between two adjacent current times, judging whether the time interval is greater than a threshold, and restarting recording if the time interval is greater than the threshold until the time interval is less than the threshold; The current time determination module is used to record the current time as the time value Time of the next reception if the time interval meets the above judgment conditions. n+1 ; The timing time determination module is used to determine the updated time as: the second upper time + the second lower time + the delay error of the timing statement; wherein, the second upper time is Time n The time when the timing statement is extracted, the second time is = Time n+1 -Time n ; The time delay error DTime1 of the timing statement = 1 / baud rate*length of the timing statement string*8; The continuously receiving the current time in the plurality of timing statements includes: receiving the timing statements output before the position is solved.

6. A timing server, characterized in that: including memory and processor; The memory is used to store computer executable instructions; The processor is used to execute the computer executable instructions to implement the method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores executable instructions, and when a computer executes the executable instructions, the method according to any one of claims 1 to 4 can be implemented.

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