Realization system, method, program and device of timer unit

Abstract

The invention provides a method, a system, a program and a device for realizing a timer unit, and particularly, the system is used for writing expiration time of a plurality of timer instances in a memory and reading expiration time of the timer instances written in the memory through an atomic operation engine; and comparing the expiration time of the timer instance with the current system timestamp through the micro-core unit, and judging whether the expired timer instance exists or not. According to the technical scheme, the problem that in the prior art, when the number of the timer units is expanded, the precision of the timer units and the flexibility of application cannot be considered at the same time can be solved.

Description

Technical Field

[0001] The present application relates to the field of electronic communications, and in particular to a system, method, program and device for implementing a timer unit. Background Art

[0002] With the development of technology, the demand for the number of timer units in data processing units (DPU network cards) is growing. For example, in the field of cloud computing, due to the exponential growth of network traffic, the number of network packets that the DPU network card needs to process has increased dramatically, which requires the DPU to process and manage a large amount of data in a short period of time, thus putting forward higher requirements on the number and accuracy of timers; for example, in the field of diversified protocol processing, it has become necessary to support multiple communication protocols and standards in modern network environments, and different protocols have different requirements for time control. Therefore, the DPU needs to configure multiple timers for each protocol to ensure the correct processing of data packets, timeout management and the normal operation of the protocol. This demand also puts forward higher requirements on the number of timer units; and, as the DPU network card gradually integrates more functions, such as computing task offloading, load balancing, encryption and decryption, network security, etc., each functional module may require an independent timer for task scheduling and time management, which further promotes the growth of demand for timer units.

[0003] Traditional methods for expanding the number of timer units are mostly hardware-fixed implementations, that is, the timer module is directly solidified inside the chip through hardware design. This implementation method determines the number and purpose of the timer during the chip design stage, and it cannot be dynamically expanded or modified later, and the number of timers provided by this method is relatively small. In some systems, the expansion of the number of timers can be achieved through time-sharing multiplexing, that is, multiple tasks share the same timer, and the system simulates the effect of multiple timers through fast switching and task scheduling, but this method may lead to a decrease in accuracy and an increase in system complexity. In summary, the timer units in the prior art cannot take into account both the accuracy and flexibility of the timer units when expanding their number. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a system, method, program and device for implementing a timer unit, so as to solve the problem that the timer units in the prior art cannot take into account both accuracy and flexibility in use when expanding the number.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a timer unit implementation system, including: a memory unit, the memory unit including an atomic operation engine, the atomic operation engine is used to write the expiration time of several timer instances in the memory and read the expiration time of the timer instance written in the memory; a micro core unit, the micro core unit including: a clock unit and a control unit; wherein the clock unit is used to provide a system timestamp; the control unit is used to read the current system timestamp from the clock unit, and compare the expiration time of the timer instance with the current system timestamp to determine whether there is an expired timer instance; if there is no expired timer instance, then after a preset time, continue to read the current system timestamp and the expiration time of the timer instance written in the memory, and compare the two to determine whether there is an expired timer instance, until it is determined that there is an expired timer instance; if there is an expired timer instance, the expired timer instance is removed from the memory unit and a notification is sent to the outside.

[0006] In an embodiment of the first aspect of the present application, the memory unit also includes a priority queue, and the expiration time of the timer instance is stored in the priority queue; wherein the timer instances are arranged in the priority queue in order of their expiration time.

[0007] In one embodiment of the first aspect of the present application, the process of the atomic operation engine writing the expiration time of several timer instances into the memory includes: the control unit calls the delay setting interface to set the expiration time of several timer instances, and the atomic operation engine writes the expiration time of the timer instances into the memory respectively.

[0008] In an embodiment of the first aspect of the present application, the micro core unit further includes a notification unit, and the control unit calls the notification unit to send a timer instance expiration notification to the outside through a signal notification interface.

[0009] In an embodiment of the first aspect of the present application, the control unit reads the current system timestamp from the clock unit, and compares the expiration time of the timer instance with the current system timestamp, and the process of determining whether there is an expired timer instance includes: the control unit reads the current system timestamp from the clock unit by calling the system time acquisition interface; the control unit checks the expiration time of the timer instance in the priority queue by calling the expiration check interface; wherein, the process of checking the expiration time of the timer instance includes: starting from the timer instance with the earliest expiration time, traversing and checking in sequence, and ending the check when the expiration time of the first timer instance retrieved is later than the system timestamp information; and determining whether there is an expired timer instance in the check result.

[0010] In an embodiment of the first aspect of the present application, after a preset time has passed, the operation of continuing to read the current system timestamp and the expiration time of the timer instance written in the memory is implemented through a blocking asynchronous mechanism.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a method for implementing a timer unit, which is applied to a DPU control system with an atomic operation engine, and the method includes the following steps: writing the expiration time of several timer instances in the memory; reading the current system timestamp; reading the expiration time of the timer instance written in the memory, and comparing the expiration time of the timer instance with the current system timestamp to determine whether there is an expired timer instance; if there is no expired timer instance, after a preset time, continue to read the current system timestamp and the expiration time of the timer instance written in the memory, and compare the two to determine whether there is an expired timer instance, until it is determined that there is an expired timer instance; if there is an expired timer instance, remove the expired timer instance from the memory unit and send a notification to the outside.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements the above-mentioned method.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer device, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the above-mentioned method.

[0014] As described above, the present application has the following beneficial effects:

[0015] The present application provides a new timer unit implementation system, method, program and device. Specifically, the system includes: a memory unit, the memory unit includes an atomic operation engine, the atomic operation engine is used to write the expiration time of several timer instances in the memory and read the expiration time of the timer instance written in the memory; a micro core unit, the micro core unit includes: a clock unit and a control unit; wherein the clock unit is used to provide a system timestamp; the control unit is used to read the current system timestamp from the clock unit, and compare the expiration time of the timer instance with the current system timestamp to determine whether there is an expired timer instance; if there is no expired timer instance, after a preset time, continue to read the current system timestamp and the expiration time of the timer instance written in the memory, and compare the two to determine whether there is an expired timer instance, until it is determined that there is an expired timer instance; if there is an expired timer instance, the expired timer instance is removed from the memory unit and a notification is sent to the outside.

[0016] The technical solution of implementing the timer unit by hardware fixation in the prior art is based on the principle of directly fixing the timer module inside the chip through hardware design. This method determines the number and purpose of the timer in the chip design stage, and cannot be dynamically expanded or modified later, and the number of timers provided by this method is small. The timer unit implementation system provided by the present invention can write any number of timer instances into the memory according to the needs, so that the method can realize a large number of expansions of the number of timer instances, and the expanded timer instances are not fixed in purpose, so the flexibility of use is achieved. The essence of the present invention is to use the computing and memory access capabilities of the multi-core micro-engine in the DPU control system, and use the atomic operation engine and bus input / output operation (IO) capabilities to realize a solution of the timer unit. The number and specification of the timer instance depends on the atomic input / output operation (atomic IO) capability, the computing power of the multi-core micro-engine, and the required timer accuracy.

[0017] The technical solution for implementing the expansion of the timer unit through time-sharing multiplexing in the prior art is based on the principle that multiple tasks share the same timer, and the system simulates the effect of multiple timers through fast switching and task scheduling. However, this method requires saving and restoring the context each time a task is switched, which takes a certain amount of time, making the timing operation not accurate to the actual needs of each task. This overhead will introduce delays, resulting in reduced accuracy of the timing operation; and, in order to coordinate the use of the same timer by multiple tasks, the system's scheduling algorithm will become more complex, which may introduce more uncertainties and affect the timing accuracy. The present invention reduces the delay and overhead caused by task switching by storing each timer instance independently in the memory, without relying on a shared hardware timer or a complex scheduling mechanism; and, since it does not involve complex scheduling and task switching, the accuracy of each timer instance is mainly determined by the reading speed of the memory and system timestamp, which can maintain a high accuracy, and thus can provide a high timing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a structural schematic diagram of an implementation system of a timer unit of the present application.

[0019] FIG. 2 is a schematic diagram showing an arrangement of timer instances within a priority queue of the present application.

[0020] Figure 3 Shown is a flowchart of a method for implementing a timer unit of the present application.

[0021] Figure 4 Shown is a structural schematic diagram of an implementation device of a timer unit of the present application. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0023] like Figure 1As shown, in order to achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a timer unit implementation system, including: a memory unit, the memory unit includes an atomic operation engine, the atomic operation engine is used to write the expiration time of several timer instances in the memory and read the expiration time of the timer instance written in the memory; a micro core unit, the micro core unit includes: a clock unit (Ticker) and a control unit (Controller); wherein the clock unit is used to provide a system timestamp; the control unit is used to read the current system timestamp from the clock unit, and compare the expiration time of the timer instance with the current system timestamp to determine whether there is an expired timer instance; if there is no expired timer instance, after a preset time, continue to read the current system timestamp and the expiration time of the timer instance written in the memory, and compare the two to determine whether there is an expired timer instance, until it is determined that there is an expired timer instance; if there is an expired timer instance, the expired timer instance is removed from the memory unit and a notification is sent to the outside.

[0024] It should be understood that the present invention is implemented based on an atomic operation engine and a micro-core unit. The atomic operation engine is a hardware or software module for ensuring data consistency and avoiding concurrent conflicts, and is particularly suitable for high-concurrency scenarios. It completes the writing and reading of data in the memory by performing atomic operations in a multi-task or multi-core system, so that these operations cannot be interrupted during execution, thereby avoiding data competition and state inconsistency problems. In the timer unit implementation system of the present application, the atomic operation engine is mainly responsible for two core tasks: one is to write the expiration time of the timer instance, which ensures that there will be no conflict when multiple tasks write data to the memory at the same time, ensuring the accuracy of the time information of the timer instance. The second is to read the expiration time of the timer instance. The atomic operation engine can also read the expiration time of the timer instance that has been written to the memory in an atomic manner to avoid data inconsistency caused by concurrent operations. The atomic operation engine interacts directly with the memory unit, and by providing efficient and safe read and write operations, it ensures the correctness of the timer instance data in the memory during multi-task operations in a multi-core environment. The atomic operation engine inserts, deletes, reads and updates the timer instance data in the memory through the atomic operation mechanism to ensure the integrity and non-interruptibility of these operations.

[0025] It should be understood that the micro core unit is the core control component of the timer system, responsible for managing the life cycle of the timer instance and its interaction with the system clock. It includes two key subunits: the clock unit and the control unit. Among them, the clock unit is responsible for providing the system timestamp, which is usually generated by reading the current time of the system clock or the chip clock. The system timestamp represents the precise time of the current system and is used to compare with the expiration time of the timer instance to determine whether the timer has expired. The system timestamp is an accurate time mark used to indicate the current system time. In the timer unit implementation system, the system timestamp is provided by the clock unit and is the benchmark for core time comparison. The expiration time of the timer is set to a certain moment in the future, and the system timestamp is used to determine whether the moment has arrived. The system timestamp is the key to the timer comparison operation. The micro core unit periodically reads the system timestamp and compares it with the expiration time of the timer instance to determine whether the timer has expired. Once the expiration time of the timer instance is less than or equal to the system timestamp, it means that the timer has expired and the corresponding event processing needs to be triggered. The control unit is responsible for reading the system timestamp provided by the clock unit and comparing it with the expiration time of the timer instance stored in the memory. By comparing, the control unit can determine which timer instances have expired, and then perform subsequent removal and notification operations. If no timer has expired, the control unit continues to repeat the checking process after a preset time interval until an expired timer instance is found.

[0026] In one embodiment of the first aspect of the present application, the process of the atomic operation engine writing the expiration time of several timer instances into the memory includes: the control unit calls the delay setting (Set Delay) interface to set the expiration time of several timer instances, and the atomic operation engine writes the expiration time of the timer instances into the memory respectively.

[0027] In an embodiment of the first aspect of the present application, the memory unit also includes a priority queue (PriorityQueue), and the expiration time of the timer instance is stored in the priority queue; wherein the timer instances are arranged in the priority queue in order of their expiration time.

[0028] It should be understood that the priority queue refers to a data structure in memory used to manage and sort timer instances. Its function is to sort the timer instances according to their expiration time to ensure that the earliest expiring instances can be processed first. In the present invention, the priority queue is responsible for maintaining the timer instances, that is, performing operations such as adding, removing and updating the timer instances.

[0029] As shown in FIG2 , the multi-core micro-engine calls the delay setting interface to set the expiration time of several timer instances (Timer): a1, a2, a3, a4, a5, ..., an (n≥1), and the order of time from first to last is: a1 is earlier than a2, a2 ​​is earlier than a3, a3 is earlier than a4, a4 ​​is earlier than a5, a5 is earlier than a6, ..., a(n-1) is earlier than an. Then the aforementioned several timer instances are written into the priority queue in the memory in sequence through the atomic operation engine. The order of these timer instances from top to bottom in the priority queue is: Timer a1, Timer a2, Timer a3, Timer a4, Timer a5, ..., Timer an, or the order from top to bottom is: Timer an, ..., Timer a5, Timer a4, Timer a3, Timer a2, Timer a1.

[0030] In an embodiment of the first aspect of the present application, the control unit reads the current system timestamp from the clock unit, and compares the expiration time of the timer instance with the current system timestamp, and the process of determining whether there is an expired timer instance includes: the control unit reads the current system timestamp from the clock unit by calling the system time acquisition (Get TS) interface; the control unit checks the expiration time of the timer instance in the priority queue by calling the expired check (Check Expired) interface; wherein, the process of checking the expiration time of the timer instance includes: starting from the timer instance with the earliest expiration time, traversing the check in sequence, and ending the check when the expiration time of the first timer instance retrieved is later than the system timestamp information; and determining whether there is an expired timer instance in the check result.

[0031] It should be understood that the traversal check refers to checking in sequence from the earliest expired timer instance in the priority queue according to the expiration time of the timer instance. When the first unexpired timer instance is checked, the check is terminated and it is determined whether there is an expired timer instance in the check result. For example, the expiration time of the timer instance written in the priority queue is: a1, a2, a3, a4, a5, ..., an (n ≥ 1), wherein the order from first to last is: a1 is earlier than a2, a2 ​​is earlier than a3, a3 is earlier than a4, a4 ​​is earlier than a5, a5 is earlier than a6, ..., a (n-1) is earlier than an, and the order of the timer instances arranged from top to bottom according to their expiration time is: Timer a1, Timer a2, Timer a3, Timer a4, Timera5, ..., Timer an, or Timer an, ..., Timer a5, Timer a4, Timer a3, Timer a2, Timera1. When the arrangement order is Timer a1, Timer a2, Timer a3, Timer a4, Timer a5, ..., Timer an, start from Timer a1 and check from top to bottom. If the expiration time of Timer a3 is after the timestamp of the current system, then Timer a3 is the first timer instance whose expiration time is later than the timestamp information of the system. Since a4 is later than a3, there is no need to check the expiration time after a3, and the check can be stopped when a3 is checked. When the arrangement order is Timer an, ..., Timera5, Timer a4, Timer a3, Timer a2, Timer a1, start from Timer a1 and check from bottom to top. If the expiration time of a5 is after the timestamp of the current system, then Timer a5 is the first timer instance whose expiration time is later than the timestamp information of the system. Since a5 is earlier than a6, there is no need to check the expiration time after a6, and the check can be stopped when a5 is checked.

[0032] This method of arranging timer instances in order in a priority queue and traversing and checking to retrieve expired timer instances can quickly determine which timers have expired and which have not expired. Because the earliest expired timer is always at the front of the queue, the system only needs to check the expiration time of the first timer instance in the queue to determine whether a timer event needs to be triggered. This sorting significantly reduces the number of comparisons required for each check and improves the judgment efficiency of the system. If the timer instances are not sorted by expiration time, each time the system determines whether the timer has expired, it needs to traverse the entire queue and compare the expiration time of each timer one by one, which will bring a large performance overhead. The priority queue arranges the timer instances in order, and can only traverse part of the queue during the check, thereby avoiding unnecessary comparisons. Especially when there are a large number of timers, the complexity of traversal and the consumption of system resources can be greatly reduced. Secondly, by sorting by expiration time, the earliest expired timer is always at the front of the priority queue. The system can process these timer instances in a timely manner to avoid delays or omissions of expiration events, which helps to ensure the accuracy and timeliness of timer events, especially in applications that require precise time control. Furthermore, when a new timer instance is added to the queue, the ordered priority queue ensures that the new instance is correctly inserted into the appropriate position of the queue. By using an effective insertion sort algorithm, the queue always remains in order of expiration time, making it convenient for the system to dynamically add, update, or remove timer instances at runtime without affecting the order and correctness of existing timers.

[0033] In an embodiment of the first aspect of the present application, after a preset time has passed, the operation of continuing to read the current system timestamp and the expiration time of the timer instance written in the memory is implemented through a blocking asynchronous mechanism.

[0034] It should be understood that the blocking asynchronous mechanism refers to that when reading the system's timestamp information, the operation of the timer unit does not return immediately, but blocks the current operation until a certain condition is met (such as the arrival of a preset time interval or an event trigger). During this process, the operation is in a "suspended" state and does not occupy processor resources. Specifically, the mechanism includes the following steps: (1) Triggering of blocking operation: When the timer unit determines that no timer instance has expired, the multi-core micro-engine enters a blocking state by calling the timestamp wait (Wait Timestamps) interface. At this time, the system will not continue to execute other operations, but will pause the current thread and wait for the triggering condition. (2) Setting of waiting condition: In the blocking state, the multi-core micro-engine will set a waiting condition through the atomic operation engine. This condition is usually a trigger based on the system clock, such as the arrival of a preset time interval. When the preset time interval arrives, the system timestamp will be updated, triggering the waiting condition and releasing the blocking state. (3) Unblocking and resuming operation: When the preset condition is met, the blocking state is automatically released, and the multi-core micro-engine resumes execution. At this time, the system will continue to read the latest system timestamp information and recheck the timer instance. If no instance has expired, it will enter the blocking state again until it is checked that an instance has expired. (4) Asynchronous notification mechanism: In order to improve the responsiveness of the system, in the blocking state, if an external event (such as an interrupt or external signal) occurs, the system can wake up the multi-core micro-engine through an asynchronous notification mechanism. For example, when a high-priority timer instance expires ahead of schedule, the notifier will immediately send an asynchronous notification signal to the multi-core micro-engine to force the blocking state to be released and processed immediately.

[0035] In an embodiment of the first aspect of the present application, the micro core unit further includes a notification unit, and the control unit calls the notification unit to send a timer instance expiration notification to the outside through a signal notification interface. After the notification unit sends the timer instance expiration notification to the external protocol module, the business processing flow of the external protocol module is triggered, thereby realizing the corresponding function of the timer.

[0036] like Figure 3 To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a method for implementing a timer unit, which is applied to a DPU control system with an atomic operation engine. The method comprises the following steps:

[0037] S1: Write the expiration time of several timer instances in the memory (unit).

[0038] S2: (Control unit in the micro core unit) reads the current system timestamp.

[0039] S3: (the control unit in the micro core unit) reads the expiration time of the timer instance written in the memory, and compares the expiration time of the timer instance with the current system timestamp to determine whether there is an expired timer instance.

[0040] If there is no expired timer instance, then after a preset time, (the control unit in the micro core unit) continues to read the current system timestamp and the expiration time of the timer instance written in the memory, and compares the two to determine whether there is an expired timer instance, until it is determined that there is an expired timer instance.

[0041] If there is an expired timer instance, the (control unit in the micro core unit) removes the expired timer instance from the memory unit and sends a notification to the outside.

[0042] Since the relevant principles have been introduced in the previous part of the implementation system of a timer unit, the principles of the implementation method of a timer unit in this part are the same as the former, so they will not be repeated here.

[0043] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements any of the methods described above.

[0044] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer device, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement any of the above-mentioned methods.

[0045] Figure 4 is a schematic block diagram of a computer device provided in an embodiment of the present application. Figure 4 As shown, the computer device includes: at least one processor 401, a memory 402, at least one network interface 403 and a user interface 405. The various components in the device are coupled together through a bus system 404. It can be understood that the bus system 404 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 404 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, the bus system 404 is not described in detail. Figure 4 In the specification, various buses are labeled as bus systems.

[0046] The user interface 405 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0047] It is understood that the memory 402 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0048] The memory 402 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic terminal 400. Examples of these data include: any executable program used to operate on the electronic terminal 400, such as an operating system 4021 and an application 4022; the operating system 4021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 4022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The method provided by the embodiment of the present invention can be included in the application 4022.

[0049] The method disclosed in the above embodiment of the present invention can be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 401 or the instruction in the form of software. The above processor 401 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 401 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 401 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0050] In an exemplary embodiment, the electronic terminal 400 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0051] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0052] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0053] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0054] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0055] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0056] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0057] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0058] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0059] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0061] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media integrations. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs), etc.).

[0062] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0063] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0064] In summary, the implementation method, system, program and device of a timer unit provided in the present application effectively overcome various shortcomings in the prior art and have high industrial utilization value.

[0065] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A timer unit implementation system, characterized in that: include: A memory unit, the memory unit comprising an atomic operation engine, the atomic operation engine being used to write expiration times of several timer instances in the memory and to read expiration times of the timer instances already written in the memory; A micro core unit, the micro core unit comprising: a clock unit and a control unit; Wherein, the clock unit is used to provide a system timestamp; The control unit is used to read the current system timestamp from the clock unit, and compare the expiration time of the timer instance with the current system timestamp to determine whether there is an expired timer instance; if there is no expired timer instance, then after a preset time, continue to read the current system timestamp and the expiration time of the timer instance written in the memory, and compare the two to determine whether there is an expired timer instance, until it is determined that there is an expired timer instance; if there is an expired timer instance, remove the expired timer instance from the memory unit and send a notification to the outside.

2. A timer unit implementation system according to claim 1, characterized in that: The memory unit also includes a priority queue, and the expiration time of the timer instance is stored in the priority queue; wherein the timer instances are arranged in the priority queue in sequence according to their expiration time.

3. A timer unit implementation system according to claim 1, characterized in that: The process of the atomic operation engine writing the expiration time of several timer instances into the memory includes: the control unit calls the delay setting interface to set the expiration time of several timer instances, and the atomic operation engine writes the expiration time of the timer instances into the memory respectively.

4. A timer unit implementation system according to claim 1, characterized in that: The micro core unit also includes a notification unit, and the control unit calls the notification unit to send a timer instance expiration notification to the outside through a signal notification interface.

5. A timer unit implementation system according to claim 2, characterized in that: The control unit reads the current system timestamp from the clock unit, and compares the expiration time of the timer instance with the current system timestamp, and the process of determining whether there is an expired timer instance includes: The control unit reads the current system timestamp from the clock unit by calling the system time acquisition interface; The control unit checks the expiration time of the timer instance in the priority queue by calling the expiration check interface; wherein the process of checking the expiration time of the timer instance includes: starting from the timer instance with the earliest expiration time, traversing the check in sequence, and ending the check when the expiration time of the first timer instance retrieved is later than the system timestamp information; Determine whether there is an expired timer instance in the check result.

6. A timer unit implementation system according to claim 1, characterized in that: After the preset time has passed, the operation of continuing to read the current system timestamp and the expiration time of the timer instance written in the memory is implemented through a blocking asynchronous mechanism.

7. A method for implementing a timer unit, applied to a DPU control system with an atomic operation engine, characterized in that: The method comprises the following steps: Write the expiration time of several timer instances in memory; Read the current system timestamp; Read the expiration time of the timer instance written in the memory, and compare the expiration time of the timer instance with the current system timestamp to determine whether there is an expired timer instance; If there is no expired timer instance, then after a preset time, continue to read the current system timestamp and the expiration time of the timer instance written in the memory, and compare the two to determine whether there is an expired timer instance, until it is determined that there is an expired timer instance; If there is an expired timer instance, the expired timer instance is removed from the memory unit and a notification is sent out.

8. A computer program product, characterized in that The computer program product comprises a computer program code, and when the computer program code is run on a computer, the computer is caused to implement the method as claimed in claim 7.

9. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method described in claim 7.

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