A three-stage pipeline Booth multiplier

Abstract

The invention discloses a three-stage pipeline Booth multiplier, which belongs to the field of integrated circuits and comprises a primary pipeline, a secondary pipeline and a tertiary pipeline; the primary pipeline comprises a radix 4-Booth encoding module and a partial product generation module; the radix 4-Booth encoding module encodes a binary multiplier B to obtain four control signals NEG, Z, X1 and X2; the partial product generation module combines the four control signals NEG, Z, X1 and X2 with a binary multiplicand A to generate partial products; the secondary pipeline performs an accumulation operation on a plurality of partial product terms generated by the partial product generation module to obtain two accumulated values; the tertiary pipeline performs parallel carry summation on the two accumulated values ​​obtained in the secondary pipeline to obtain a final product.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a three-stage pipeline Booth multiplier. Background Art

[0002] Today, with the rapid development of the integrated circuit industry, with the rapid development and application of various new technologies, the level of electrical automation is constantly improving, and circuits as a functional industry are widely used in people's daily production and life. Integrated circuits are the basic conditions for the rapid development of the information industry, especially to meet the ever-increasing requirements of contemporary society for electronic information products, and people have higher and higher requirements for processor chip performance.

[0003] The arithmetic unit has always been an important part of the processor chip, and the multiplier, as an important computing module in the processor chip, is the core of real-time image processing and digital signal processing, and is usually the key path of data processing in the processor. The time it takes to complete an operation basically determines the maximum operating frequency of the processor. Therefore, designing and developing a low-power multiplier with good structure, small area and high speed will definitely occupy a certain advantage in the rapidly developing IC industry.

[0004] The core operation steps of the multiplier are the generation of partial products, compression of partial products, and final summation and addition. The design focus is on what kind of structure to use to implement it. Currently, the most widely used multiplier structures are radix 4 Booth algorithm, Wallace tree structure, and carry-lookahead adder. Since these three steps are usually serial, there may be situations such as too long critical path or contention hazards, which may lead to errors in the results. Summary of the invention

[0005] The purpose of the present invention is to provide a three-stage pipeline Booth multiplier to solve the problem that the critical path delay time is too long due to the current serial calculation.

[0006] In order to solve the above technical problems, the present invention provides a three-stage pipeline Booth multiplier, including a first-stage pipeline, a second-stage pipeline and a third-stage pipeline;

[0007] The first-level pipeline includes a radix-4-Booth encoding module and a partial product generation module; the radix-4-Booth encoding module encodes the binary multiplier B to obtain four control signals NEG, Z, X1, and X2; the partial product generation module combines the four control signals NEG, Z, X1, and X2 with the binary multiplicand A to generate partial products;

[0008] The secondary pipeline performs an accumulation operation on the multiple partial product terms generated by the partial product generation module to obtain two accumulated values;

[0009] The three-stage pipeline performs parallel carry summation on the two accumulated values ​​obtained in the two-stage pipeline to obtain a final product.

[0010] Optionally, the process of encoding the binary multiplier B by the radix 4-Booth encoding module is as follows:

[0011] The base 4-Booth encoding requires that the multiplier B is an odd number of digits. If it is an even number of digits, add a 0 to the last digit. The algorithm principle of the base 4-Booth is:

[0012]

[0013] Where B = b n b n-1 ...b1b0, n is the number of digits of the multiplier B, E k is the value after the multiplier is divided, 0≤k≤2 n -1, according to the above formula, the multiplier B is grouped in a way that every three bits are grouped, and every two groups overlap by one bit. Through Booth coding, four corresponding control signals NEG, Z, X1, and X2 are obtained. Let NEG = b 2i+1 , Z = b 2i+1 ⊙b 2i , X1=b 2i ⊙b 2i-1 , X2=b 2i ⊕b 2i-1 , where i∈[0,n].

[0014] Optionally, the process of generating the partial product by the partial product generating module is as follows: Assuming that the multiplicand A is n bits, the expression of the partial product is P j =X1Z9a j-1 ⊕NEG)+X2(a j ⊕NEG), where A=a n a n-1 ...a1a0, j∈[0,n]; perform radix-4-Booth encoding on each three bits of the multiplier B as a group, the number of partial products is 17, and the number of bits of each partial product is 34; the sum of all partial products is the final product, and the signs of the partial products are extended to 66 bits before adding and summing the 17 partial products; the sum of the sign compensation bits of all 17 partial products is taken as the 18th partial product and is included in the summation of the other 17 partial products.

[0015] Optionally, the secondary pipeline uses a hybrid Wallace tree compressor, including a 3:2 compressor and an optimized 4:2 compressor.

[0016] Optionally, the three-stage pipeline is a carry-lookahead adder.

[0017] Optionally, the three-stage pipeline Booth multiplier further includes a multiplier sign extension module and a multiplicand sign extension module, which are used to generate a multiplier B of the input radix 4-Booth encoding module and a multiplicand A of the input partial product generation module.

[0018] The three-stage pipeline Booth multiplier provided by the present invention has the following beneficial effects compared with the prior art:

[0019] (1) A three-stage pipeline is used throughout the entire computing process, which effectively reduces the critical path delay time, improves the multiplier operation speed, and has better performance among multi-stage pipeline processors;

[0020] (2) The sign compensation technique is used in the radix-4-Booth coding module to add a partial product, so that the partial products in the 32-bit multiplication have 18, which is beneficial to the symmetry and balance of the compressor design;

[0021] (3) A hybrid Wallace tree compressor is used to perform accumulation operations on the generated partial products, which fully utilizes the advantages of the small layout area of ​​the 3:2 compressor and the high compression ratio of the 4:2 compressor, thereby achieving a good improvement in area and speed, and facilitating layout and routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a three-stage pipeline Booth multiplier provided by the present invention;

[0023] Figure 2 Optimized circuit diagram for Booth coding;

[0024] Figure 3 It is a structural diagram of a hybrid Wallace tree compressor;

[0025] Figure 4 This is the logic circuit diagram of the optimized 4:2 compressor. DETAILED DESCRIPTION

[0026] The following is a further detailed description of a three-stage pipeline Booth multiplier proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] The present invention provides a three-stage pipeline Booth multiplier, the structure of which is as follows: Figure 1As shown, it includes a first-stage pipeline, a second-stage pipeline and a third-stage pipeline. The first-stage pipeline includes a radix-4-Booth encoding module and a partial product generation module; the second-stage pipeline adopts a hybrid Wallace-Tree compressor; and the third-stage pipeline adopts a carry-lookahead adder module.

[0028] The base 4-Booth encoding module is used to encode the binary multiplier B. The encoding process is as follows: let the multiplier be B. The base 4-Booth encoding requires that the multiplier B is an odd number of bits. If it is an even number of bits, a 0 needs to be added to the last bit. The principle of the base 4-Booth algorithm is:

[0029] Where B = b n b n-1 ...b1b0, n is the number of digits of the multiplier B, where E k is the value after the multiplier is divided, 0≤k≤2 n -1, according to the above formula, the multiplier B is grouped in a way that every three bits are grouped, and every two groups overlap by one bit. Through Booth coding, four corresponding control signals NEG, Z, X1, and X2 are obtained. Let NEG = b 2i+1 , Z = b 2i+1 ⊙b 2i , X1=b 2i ⊙b 2i-1 , X2=b 2i ⊕b 2i-1 , where i∈[0,n]; the truth table of the Booth-encoded control signal is shown in Table 1. The 32-bit multiplier is expanded, 0 is added to the low bit, and two sign bits are added to the high bit to form a 35-bit operand.

[0030] <![CDATA[X 2i+1 ]]> <![CDATA[X 2i ]]> <![CDATA[X 2i-1 ]]> Partial Product <![CDATA[B1]]> <![CDATA[B2]]> NEG Z 0 0 0 0 1 0 0 1 0 0 1 A 0 1 0 1 0 1 0 A 0 1 0 0 0 1 1 2*A 1 0 0 0 1 0 0 -2*A 1 0 1 0 1 0 1 -A 0 1 1 0 1 1 0 -A 0 1 1 1 1 1 1 0 1 0 1 1

[0031] Table 1 Booth coding table

[0032] The partial product generation module is used to combine the signals NEG, Z, X1, and X2 with the binary multiplicand A to generate partial products. The process of generating partial products is as follows: Assuming that the multiplicand A is n bits, the partial product expression is P j =X1Z(a j-1 ⊕NEG)+X2(a j ⊕NEG), where A=a n a n-1 ...a1a0, j∈[0,n]; the optimized circuit of Booth coding is as follows Figure 2As shown. Each three bits of the multiplier B are grouped together for base 4-Booth encoding. At this time, the number of partial products is 17, and the number of bits of each partial product is 34. The sum of all partial products is the final product. Before adding and summing the 17 partial products, the signs of the partial products need to be extended to 66 bits. The sum of the sign compensation bits of all 17 partial products is used as the 18th partial product to participate in the summation of the other 17 partial products. This sign compensation technology involves a small number of bits, is easy to calculate, and will not affect the speed of the entire partial product generation module.

[0033] The present invention adopts a mixed Wallace-Tree compressor to perform accumulation operation on the generated partial products to obtain two accumulated values. Figure 3 Schematic diagram of the hybrid Wallace tree compressor structure, including eight 3:2 compressors (CSA) and four optimized 4:2 compressors, such as Figure 4 As shown, 18 partial product terms are compressed, which takes advantage of the small CSA layout area and the high compression ratio of the 4:2 compressor. Compared with the traditional Wallace, it has better performance in terms of area and speed, and the hybrid structure is symmetrical and balanced, which is conducive to layout and routing.

[0034] Matters not covered by the present invention are well known in the art.

[0035] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A three-stage pipeline Booth multiplier, characterized in that: Including primary assembly line, secondary assembly line and tertiary assembly line; The first-level pipeline includes a radix-4-Booth encoding module and a partial product generation module; the radix-4-Booth encoding module encodes the binary multiplier B to obtain four control signals NEG, Z, X1, and X2; the partial product generation module combines the four control signals NEG, Z, X1, and X2 with the binary multiplicand A to generate partial products; The secondary pipeline performs an accumulation operation on the multiple partial product terms generated by the partial product generation module to obtain two accumulated values; The three-stage pipeline performs parallel carry summation on the two accumulated values ​​obtained in the two-stage pipeline to obtain a final product; The process of encoding the binary multiplier B by the base 4-Booth encoding module is as follows: The base 4-Booth encoding requires that the multiplier B is an odd number of digits. If it is an even number of digits, add a 0 to the last digit. The algorithm principle of the base 4-Booth is: ， Where B=b n b n-1 ...b1b0, n is the number of digits of the multiplier B, E k is the value after the multiplier is divided, 0≤k≤2 n -1, according to the above formula, the multiplier B is grouped into groups of three bits each, with one bit overlapped between two groups, and four corresponding control signals NEG, Z, X1, and X2 are obtained through Booth coding. , , , ,in .

2. The three-stage pipeline Booth multiplier according to claim 1, characterized in that: The process of generating partial products by the partial product generating module is as follows: Assuming that the multiplicand A is n bits, the expression of the partial product is , where A=a n a n-1 ...a1a0, ; Perform radix-4-Booth encoding on every three bits of the multiplier B, the number of partial products is 17, and the number of bits of each partial product is 34; the sum of all partial products is the final product, and the signs of the partial products are extended to 66 bits before adding and summing the 17 partial products; the sum of the sign compensation bits of all 17 partial products is used as the 18th partial product to participate in the summation of the other 17 partial products.

3. The three-stage pipeline Booth multiplier according to claim 1, characterized in that: The two-stage pipeline adopts a hybrid Wallace tree compressor, including a 3:2 compressor and an optimized 4:2 compressor.

4. The three-stage pipeline Booth multiplier according to claim 1, characterized in that: The three-stage pipeline is a carry-lookahead adder.

5. The three-stage pipeline Booth multiplier according to claim 1, characterized in that: The three-stage pipeline Booth multiplier also includes a multiplier sign extension module and a multiplicand sign extension module, which are used to generate a multiplier B input to the radix 4-Booth encoding module and a multiplicand A input to the partial product generation module.

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