Clock detection methods, devices and clock security systems

Abstract

The embodiments of the present invention relate to a clock detection method, device and clock security system, which implement clock security detection through a digital detection circuit. Compared with analog circuit detection solutions, the circuit area required for layout is smaller, the power consumption and cost are lower, and the low power consumption requirements of the clock security system can be better met.

Description

Technical Field

[0001] The present invention relates to the field of clock security, and in particular to a clock detection method, device and clock security system. Background Art

[0002] Low speed external crystal (LSE) is used in many integrated circuit chips for real-time timing and other applications because of its very precise rate. Since the low speed external clock is a component outside the chip, a clock security system (CSS) is required to prevent the low speed external clock from failing to work properly. The clock security system can be implemented by detecting the low speed external clock failure and then notifying the system through interrupts or events. The system can handle this with some backup solutions, such as switching clock sources.

[0003] Due to the low frequency characteristics of LSE, its application usually requires very low power consumption. The same low power consumption requirement also applies to clock security system solutions; however, in the current related technologies, analog circuits are used to detect LSE faults. This implementation method requires the layout of a larger circuit area and generates higher power consumption, which cannot well meet the low power consumption requirements of the clock security system. Summary of the invention

[0004] The embodiments of the present invention provide a clock detection method, device and clock safety system, which mainly solve the problem that the use of analog circuits to detect LSE faults requires the layout of a large circuit area and generates high power consumption, and cannot well meet the low power consumption requirements of the clock safety system.

[0005] In order to solve the above technical problems, the embodiments of the present invention adopt the following technical solutions:

[0006] An embodiment of the present invention provides a clock detection device, including a reference clock, a counter, a signal generator, a first register and a second register;

[0007] The fourth clock terminal of the counter is connected to the reference clock, and is used for cyclically counting between k1 and k2 according to the reference clock signal of the reference clock, and the first cycle T1 of the reference clock and the second cycle T2 of the clock to be measured satisfy: (2 n -1)*T1 is greater than 1.5*T2;

[0008] The signal generator comprises a clear signal generator and a sampling signal generator connected to the output end of the counter, the clear signal generator is used to generate a clear signal when the output of the counter is k1, and the sampling signal generator is used to generate a sampling signal when the output of the counter is k2;

[0009] The first data input terminal, the first clock terminal, the first output terminal and the first reset terminal of the first register are respectively connected to the output terminal of the constant logic signal, the clock to be measured, the second data input terminal of the second register and the output terminal of the clear signal generator; the second clock terminal of the second register is connected to the output terminal of the sampling signal generator, and the second output terminal of the second register outputs a clock detection signal.

[0010] Optionally, it also includes a first logic AND gate, the output end of the first logic AND gate is connected to the fourth clock end of the counter, and the first input end and the second input end of the first logic AND gate are respectively connected to the clock safety system start signal transmission end of the reference clock and the clock to be measured.

[0011] Optionally, a second logic AND gate is further included, wherein the first input terminal and the second input terminal of the second logic AND gate are respectively connected to the output terminal of the clear signal generator and the reference clock, and the output terminal of the second logic AND gate is connected to the first reset terminal.

[0012] Optionally, a third logic AND gate is further included, wherein the first input terminal and the second input terminal of the third logic AND gate are respectively connected to the output terminal of the sampling signal generator and the reference clock, and the output terminal of the second logic AND gate is connected to the second clock terminal.

[0013] Optionally, a third register is also included, wherein the third data input terminal and the third clock terminal of the third register are respectively connected to the second output terminal of the second register and the output terminal of the first logic AND gate, and the third output terminal of the third register outputs the clock detection signal received from the second register.

[0014] Optionally, the constant logic signal is 1, and the clock detection device further includes a fourth logic AND gate and a NOT gate, wherein the first input end of the fourth logic AND gate is connected to the third output end of the third register through the NOT gate, and the second input end of the fourth logic AND gate is connected to the clock safety system start signal transmission end of the clock to be tested;

[0015] or,

[0016] The constant logic signal is 0, and the clock detection device also includes a fourth logic AND gate, a first input end of the fourth logic AND gate is connected to the third output end of the third register, and a second input end of the fourth logic AND gate is connected to the clock safety system start signal transmission end of the clock to be tested.

[0017] Optionally, the reference clock is a low-speed internal clock LSI, and the clock to be tested is a low-speed external clock LSE.

[0018] Optionally, the k1 is 0, the k2 is 2n-1, and the counter counts cyclically in an increasing manner between 0 and 2n-1 according to the reference clock signal of the reference clock;

[0019] or,

[0020] The k1 is 2n-1, the k2 is 0, and the counter counts cyclically in a decreasing manner between 2n-1 and 0 according to the reference clock signal of the reference clock.

[0021] An embodiment of the present invention further provides a clock security system, including a clock to be tested and a clock detection device as shown above for detecting the clock to be tested.

[0022] The embodiment of the present invention further provides a clock detection method, which is applied to the clock detection device shown above, comprising:

[0023] The counter cyclically counts between k1 and k2 according to the reference clock signal of the reference clock and outputs the count value, the clear signal generator generates a clear signal when the counter output is k1, and the sampling signal generator generates a sampling signal when the counter output is k2;

[0024] The first register captures the constant logic signal according to the clock timing to be measured and outputs it to the second register, and is cleared when receiving the clear signal;

[0025] The second register captures the output of the first register according to the sampling signal, and outputs the captured signal as a clock detection signal. Beneficial Effects

[0026] The embodiment of the present invention provides a clock detection method, device and clock safety system, wherein the clock detection device includes a reference clock, a counter, a signal generator, a first register and a second register; the fourth clock terminal of the counter is connected to the reference clock, and is used to cyclically count between k1 and k2 according to the reference clock signal of the reference clock, and the first period T1 of the reference clock and the second period T2 of the clock to be measured satisfy the following conditions: (2 n-1)* T1 is greater than 1.5*T2; the signal generator includes a reset signal generator and a sampling signal generator connected to the output end of the counter, the reset signal generator is used to generate a reset signal when the counter output is k1, and the sampling signal generator is used to generate a sampling signal when the counter output is k2; the first data input end, the first clock end, the first output end and the first reset end of the first register are respectively connected to the output end of the constant logic signal, the clock to be measured, the second data input end of the second register and the output end of the reset signal generator; the second clock end of the second register is connected to the output end of the sampling signal generator, and the second output end of the second register outputs the clock detection signal; in this way, the first register can capture the constant logic signal according to the timing of the clock to be tested and output it to the second register, and clear it when receiving the clear signal; the second register can capture the output of the first register according to the sampling signal, and output the captured signal as a clock detection signal, and according to the clock detection signal, it can be determined whether the clock to be tested (for example, it can be but not limited to LSE) is working normally; it can be seen that the embodiment of the present invention provides a clock safety detection solution through a digital detection circuit. Compared with the analog circuit detection solution, the circuit area required to be deployed is smaller, the power consumption and cost are lower, and the low power consumption requirement of the clock safety system can be better met. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of a clock detection device provided in an embodiment of the present invention Figure 1 ;

[0028] Figure 2 A schematic diagram of the structure of a clock detection device provided in an embodiment of the present invention Figure 2 ;

[0029] Figure 3 A schematic diagram of the structure of a clock detection device provided in an embodiment of the present invention Figure 3 ;

[0030] Figure 4 A schematic diagram of the structure of a clock detection device provided in an embodiment of the present invention Figure 4 ;

[0031] Figure 5 An exemplary circuit diagram of a clock detection device provided by an embodiment of the present invention;

[0032] Figure 6 for Figure 5 A waveform diagram of the circuit shown. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention through specific implementation methods combined with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0034] The problem that the use of analog circuits to detect LSE faults requires the layout of a larger circuit area and generates higher power consumption, which cannot well meet the low power consumption requirements of the clock security system. The clock detection device provided in this embodiment implements clock security detection through a digital detection circuit. Compared with the analog circuit detection solution, the circuit area required to be laid out is smaller, the power consumption and cost are lower, and the low power consumption requirements of the clock security system can be better met. For ease of understanding, this embodiment is combined with Figure 1 The clock detection device shown is for explanation only as an example.

[0035] See also Figure 1 As shown, the clock detection device provided in this embodiment includes a reference clock, a counter, a signal generator, a first register and a second register, wherein:

[0036] See also Figure 1 As shown, the fourth clock terminal of the counter is connected to the reference clock, and is used to cyclically count between k1 and k2 according to the reference clock signal of the reference clock (that is, the counter starts counting from k1, and when the count value reaches k2, it counts again from k1 to k2, and so on). In order to successfully detect the clock failure to be tested, the 2 n -1 cycle total period should be greater than 1.5 cycles of LSE. That is, the first cycle T1 of the reference clock and the second cycle T2 of the clock to be measured satisfy the following relationship: (2 n -1)* T1 is greater than 1.5*T2. For example, when the clock to be measured is LSE, the reference clock can be selected but not limited to the low-speed internal clock LSI. In some application scenarios, when the LSI / LSE frequencies are close to each other, the value of n can be 2, that is, a 2-bit counter is sufficient for the counter.

[0037] See also Figure 1 As shown, the signal generator includes a reset signal generator and a sampling signal generator connected to the output end of the counter. The reset signal generator is used to generate a reset signal when the counter output is k1, and the sampling signal generator is used to generate a sampling signal when the counter output is k2.

[0038] It should be understood that the values ​​of k1 and k2 in this embodiment and the technical methods can be set flexibly. For example, in one example, k1 can be set to 0 and k2 to 2. n -1, the counter is set between 0 and 2 according to the reference clock signal of the reference clock n-1, the counting is performed in an incrementing manner; the clear signal generator is used to generate a clear signal when the counter output is 0, and the sampling signal generator is used to generate a clear signal when the counter output is 2 n A sampling signal is generated when -1.

[0039] In another example, you can set k1 to 2 n -1, k2 is 0, the counter is based on the reference clock signal of the reference clock at 2 n The count is repeated in a decreasing manner between -1 and 0; the reset signal generator is used to reset the counter when the counter output is 2 n The sampling signal generator is used to generate a sampling signal when the counter output is 0.

[0040] In this embodiment, n is the bit width of the counter. In some examples, n can be flexibly set according to the frequency relationship between the reference clock and the clock to be tested (ie, the clock to be detected, such as the low-speed external clock LSE).

[0041] For ease of understanding, k1 is 0 and k2 is 2. n -1, the counter is set between 0 and 2 according to the reference clock signal of the reference clock n -1 is used as an example to illustrate the loop counting in an incremental manner.

[0042] The first data input terminal of the first register is connected to the output terminal of the constant logic signal, the first clock terminal of the first register is connected to the clock to be measured, the first output terminal of the first register is connected to the second data input terminal of the second register, and the first reset terminal of the first register is connected to the output terminal of the clear signal generator; in this way, the first register can capture the constant logic signal according to the timing of the clock to be measured and output it to the second register, and perform clearing processing when receiving the clear signal from the clear signal generator.

[0043] The second clock end of the second register is connected to the output end of the sampling signal generator, and the second output end of the second register outputs a clock detection signal. The second register captures the output of the first register according to the sampling signal received from the sampling signal generator, and outputs the captured signal as the clock detection signal.

[0044] use Figure 1 When the clock detection device shown detects the clock to be detected, the corresponding clock detection method may be, but is not limited to:

[0045] The counter is set to 0 to 2 according to the reference clock signal of the reference clock. n -1 and output the count value. The reset signal generator generates a reset signal when the counter output is 0, and the sampling signal generator generates a reset signal when the counter output is 2. n-1; the first register captures the constant logic signal according to the timing of the clock to be tested and outputs it to the second register, and is cleared when receiving the clear signal; the second register can capture the output of the first register according to the sampling signal, and output the captured signal as a clock detection signal, according to which it can be determined whether the clock to be tested (for example, but not limited to LSE) is working normally; thus, the clock safety detection is realized through the digital detection circuit. Compared with the use of analog circuits to perform clock safety detection on the clock, the circuit area required to be laid out is smaller, the power consumption and cost are lower, and the low power consumption requirement of the clock safety system can be better met.

[0046] In some application examples of this embodiment, the fourth clock terminal of the counter may be connected to the reference clock through, but not limited to, the first logic AND gate. Figure 2 As shown, the clock detection device also includes a first logic AND gate, the output end of the first logic AND gate is connected to the fourth clock end of the counter, and the first input end and the second input end of the first logic AND gate are respectively connected to the reference clock and the clock safety system CSS start signal transmission end of the clock to be measured. The CSS start signal transmission end is used to transmit the corresponding clock safety system start signal to the second input end of the first logic AND gate when the CSS of the clock to be measured is started. At this time, the first logic AND gate outputs a signal 1 to the counter only when it receives the CSS start signal and the reference clock signal of the reference clock at the same time. The counter then outputs a signal 1 to the counter according to the corresponding 0 to 2 of the signal. n -1 loop count.

[0047] In some application examples of this embodiment, the output terminal of the reset signal generator is connected to the first reset terminal through a second logic AND gate. Figure 3 As shown, the clock detection device also includes a second logic AND gate, the first input terminal and the second input terminal of the second logic AND gate are respectively connected to the output terminal of the clear signal generator and the reference clock, and the output terminal of the second logic AND gate is connected to the first reset terminal; in this way, the second logic AND gate outputs the clear signal to the first reset terminal of the first register only when it receives the clear signal from the clear signal generator and receives the corresponding reference clock signal from the reference clock.

[0048] In some application examples of this embodiment, the output terminal of the sampling signal generator is connected to the second clock terminal of the second register through a third logic AND gate. Figure 3As shown, the clock detection device also includes a third logic AND gate, the first input terminal and the second input terminal of the third logic AND gate are respectively connected to the output terminal of the sampling signal generator and the reference clock, and the output terminal of the second logic AND gate is connected to the second clock terminal, so that the third logic AND gate outputs the sampling signal to the second clock terminal of the second register only when it receives the sampling signal from the sampling signal generator and the corresponding reference clock signal from the reference clock, so that the second register can collect the signal from the first output terminal of the first register according to the light collection signal.

[0049] In some application examples of this embodiment, when the reference clock and the clock to be measured are asynchronous, in order to avoid metastability, the clock detection device further includes a third register, four logic AND gates and NOT gates, the third data input terminal and the third clock terminal of the third register are respectively connected to the second output terminal of the second register and the output terminal of the first logic AND gate, and the third output terminal of the third register outputs the clock detection signal received from the second register; the first input terminal of the fourth logic AND gate is connected to the third output terminal of the third register through the NOT gate, and the second input terminal of the fourth logic AND gate is connected to the CSS start signal transmission terminal of the clock to be measured. In this way, the output of the third register is inverted, and indicates whether a fault is detected together with the clock CSS start signal. For example, see Figure 4 As shown, the third clock terminal of the third register is connected to the reference clock, the third data input terminal of the third register is connected to the second output terminal of the second register, the third output terminal of the third register outputs the clock detection signal received from the second register and is not output to the first input terminal of the fourth logic gate, and the transmission interrupt of the clock CSS start signal is connected to the second input terminal of the fourth logic gate. In this way, the output of the third register is inverted, and indicates whether a fault is detected together with the clock CSS start signal.

[0050] It should be understood that in this embodiment, Figures 1 to 4 The constant logic signal outputted by the output terminal of the constant logic signal can be 1 or 0, which can be flexibly set according to the application scenario. When the constant logic signal is 0, Figure 4 The NOT gate in the fourth logic AND gate can be removed, and the first input terminal of the fourth logic AND gate can be directly connected to the third output terminal of the third register. For ease of understanding, this embodiment is combined with a circuit structure of a clock detection device as an example, and the constant logic signal is 1 as an example for explanation. In this application example, the clock to be measured is set to LSE, and the reference clock is set to LSI. LSI also has a low-frequency, low-speed internal RC oscillator. The detection circuit in this example can detect the edge of LSE within several cycles of LSI. Generally, the power consumption of LSI circuits and corresponding edge detection digital circuits is very low, which can better meet the low power consumption requirements of CSS.

[0051] In this example, the frequency of LSE is 32.768kHz and the frequency of LSI is 40kHz. The frequencies of LSI and LSE are close, so the counter can use a 2-bit counter to meet the 2-bit requirement of LSI. n The total period of -1 cycle should be greater than 1.5 periods of LSE, so the LSE failure can be successfully detected.

[0052] See also Figure 5 The circuit structure of the clock detection device shown in the figure includes a first logic AND gate &1, a counter cnt, a reset signal generator all bits0, a sampling signal generator all bits1, a second logic AND gate &2, a third logic AND gate &3, a first register FF1, a second register FF2, a third register FF3 and a fourth logic AND gate &4. The two input ends of the first logic AND gate &1 are respectively connected to the LSI and LSE-CSS-ON signal transmission ends, and the output end of the first logic AND gate &1 is connected to the clock end (i.e., the fourth clock end) of the counter cnt. The counter cn can be set between 0 and 2 according to the clock pulse signal (and reference clock signal) of LSE-CSS-ON and LSI. n -1; the reset signal generator all bits0 generates a reset signal when the counter cnt output is 0 (that is, all bits are 0, that is, the count value is 0), and the sampling signal generator all bits1 generates a reset signal when the counter cnt output is 1 (that is, all bits are 1, that is, the count value is 2). n -1). The two input ends of the second logic AND gate &2 are respectively connected to the output end of the clear signal generator all bits0 and the LSI, and the output end of the second logic AND gate &2 is connected to the first reset end of the first register FF1; the two input ends of the third logic AND gate &3 are respectively connected to the output end of the sampling signal generator all bits1 and the LSI, and the output end of the third logic AND gate &3 is connected to the second clock end of the second register; the first clock terminal of the first register is connected to the LSE, the first data input end is connected to the output end of the constant logic signal 1, the first output end is connected to the second data input end of the second register FF2, the second output end of the second register FF2 is connected to the third data input end of the third register FF3, the third clock end of the third register FF3 is connected to the LSI, the third output port of the third register FF3 is connected to one of the input ends of the fourth logic AND gate &4 through a NOT gate, and the other input end of the fourth logic AND gate &4 is connected to the LSE-CSS-ON signal transmission end.

[0053] See also Figure 6 As shown, when the LSE CSS function of the LSE is enabled, a 2-bit counter (such as Figure 5The counter cnt shown will be enabled. The counter will count from 0 to 2 n -1, and then restart the technology from 0 again. When the counter cnt reaches 0, the clear signal generator all bits0 generates a clear clock pulse (ie, clear signal). When the counter cnt reaches 2n-1, the sampling signal generator all bits1 generates a sampling clock pulse (ie, sampling signal).

[0054] The first register FF1 is clocked by the LSE to capture the logic signal 1. When the LSE is running, FF1 will output logic 1. The first register FF1 is periodically cleared by the clock pulse that clears it to zero. After 3 LSI cycles, the output of the first register FF1 will be captured by the sampling clock pulse into the second register FF2. Because the LSI frequency is close to the LSE, within 3 LSI cycles ( Figure 6 If the LSE is normal, the LSE will switch at least once. In this case, the second register FF2 will always output 1. If the sampling value of the second register FF2 is 0 (for example Figure 6 t3 in the figure), the LSE does not switch within 3 LSI cycles, which means that the LSE is not working properly. The third register FF3 is after the second register FF2, and the third register FF3 runs on the LSI clock. Because the LSE and LSI are asynchronous, setting the third register FF3 can avoid metastability. The output of the third register FF3 is inverted and indicates with the LSE_CSS_ON bit whether an LSE failure is detected when the LSE is high.

[0055] It can be seen that this embodiment Figure 6 The clock detection circuit shown detects the LSE rising edge within a predetermined time by using a very low power internal RC oscillator LSI as a reference clock and combining it with a simple digital fault detection circuit. Compared with the related pure analog solution, the power consumption required is much less, and if the chip is already equipped with large-scale integrated circuits and at least part of these integrated circuits can be reused as Figure 6 When at least a portion of the circuit shown is implemented, the area overhead can be further reduced, the system integration level can be improved, and the cost can be reduced.

[0056] This embodiment may also provide a clock security system implemented based on the clock detection device shown in the above figures, and the clock to be detected can be detected by the clock detection device.

[0057] It can be seen that those skilled in the art should understand that all or some steps, systems, and functional modules / units in the above disclosed methods can be implemented as software (which can be implemented by computer program code executable by a computing device), firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit.

[0058] In addition, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, computer program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery media. Therefore, the present invention is not limited to any specific hardware and software combination.

[0059] The above contents are further detailed descriptions of the embodiments of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A clock detection device, characterized in that: It includes a reference clock, a counter, a signal generator, a first register and a second register; The fourth clock terminal of the counter is connected to the reference clock, and is used for cyclically counting between k1 and k2 according to the reference clock signal of the reference clock, and the first cycle T1 of the reference clock and the second cycle T2 of the clock to be measured satisfy: (2 n -1)*T1 is greater than 1.5*T2; The signal generator comprises a clear signal generator and a sampling signal generator connected to the output end of the counter, the clear signal generator is used to generate a clear signal when the output of the counter is k1, and the sampling signal generator is used to generate a sampling signal when the output of the counter is k2; The first data input terminal, the first clock terminal, the first output terminal and the first reset terminal of the first register are respectively connected to the output terminal of the constant logic signal, the clock to be measured, the second data input terminal of the second register and the output terminal of the clear signal generator; the second clock terminal of the second register is connected to the output terminal of the sampling signal generator, and the second output terminal of the second register outputs a clock detection signal; the constant logic signal is 1 or 0.

2. The clock detection device according to claim 1, characterized in that: It also includes a first logic AND gate, the output end of the first logic AND gate is connected to the fourth clock end of the counter, and the first input end and the second input end of the first logic AND gate are respectively connected to the clock safety system start signal transmission end of the reference clock and the clock to be measured.

3. The clock detection device according to claim 1, characterized in that: It also includes a second logic AND gate, wherein the first input terminal and the second input terminal of the second logic AND gate are respectively connected to the output terminal of the clear signal generator and the reference clock, and the output terminal of the second logic AND gate is connected to the first reset terminal.

4. The clock detection device according to claim 1, characterized in that: It also includes a third logic AND gate, wherein the first input terminal and the second input terminal of the third logic AND gate are respectively connected to the output terminal of the sampling signal generator and the reference clock, and the output terminal of the third logic AND gate is connected to the second clock terminal.

5. The clock detection device according to any one of claims 2 to 4, characterized in that: It also includes a third register, whose third data input terminal and third clock terminal are respectively connected to the second output terminal of the second register and the output terminal of the first logic AND gate, and whose third output terminal outputs the clock detection signal received from the second register.

6. The clock detection device according to claim 5, characterized in that: When the constant logic signal is 1, the clock detection device further includes a fourth logic AND gate and a NOT gate, the first input end of the fourth logic AND gate is connected to the third output end of the third register through the NOT gate, and the second input end of the fourth logic AND gate is connected to the clock safety system start signal transmission end of the clock to be tested; Or, when the constant logic signal is 0, the clock detection device also includes a fourth logic AND gate, the first input end of the fourth logic AND gate is connected to the third output end of the third register, and the second input end of the fourth logic AND gate is connected to the clock safety system start signal transmission end of the clock to be measured.

7. The clock detection device according to any one of claims 1 to 4, characterized in that: The reference clock is a low-speed internal clock LSI, and the clock to be measured is a low-speed external clock LSE.

8. The clock detection device according to any one of claims 1 to 4, characterized in that: k1 is 0, k2 is 2 n -1, the counter is set between 0 and 2 according to the reference clock signal of the reference clock n -1 uses an increasing loop count; Or, k1 is 2 n -1, k2 is 0, the counter is set to 2 according to the reference clock signal of the reference clock n The count is cycled in descending order between -1 and 0.

9. A clock security system, characterized in that: The invention comprises a clock to be tested and a clock detection device as shown in any one of claims 1 to 8 for detecting the clock to be tested.

10. A clock detection method, characterized in that: A clock detection device as claimed in any one of claims 1 to 8, comprising: The counter cyclically counts between k1 and k2 according to the reference clock signal of the reference clock and outputs the count value, the clear signal generator generates a clear signal when the counter output is k1, and the sampling signal generator generates a sampling signal when the counter output is k2; The first register captures the constant logic signal according to the clock timing to be measured and outputs it to the second register, and is cleared when receiving the clear signal; The second register captures the output of the first register according to the sampling signal, and outputs the captured signal as a clock detection signal.

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