A driving apparatus, system and method for testing a display module

Abstract

An embodiment of the present application discloses a kind of test display module driving device, system and method, the driving device includes ARM and FPGA;ARM includes: instruction transceiver control module, display module parameter management module, image data management module and FPGA device management module;Instruction transceiver control module is used to receive and respond the display instruction signal sent by host computer and read test image data from the data storage of ARM and send to image data management module;Display module parameter management module is used to receive the display instruction file sent by host computer and generate test signal according to display instruction file and send to FPGA device management module;Image data management module is used to send test image data to the storage of DDR4 in FPGA and carry out management and scheduling to test image data;FPGA device management module is used to send test signal to FPGA and receive test result data to host computer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing display module driving device, in particular to a kind of testing display module driving device, system and method. BACKGROUND

[0002] In current display test scheme, because of the difference of different product lines of different manufacturers, so test driving board needs to use ARM (Advanced RISC Machines, ARM processor) main control cooperation FPGA (Field-Programmable GateArray, Field Programmable Gate Array) drive to complete the test requirement in different scenes. ARM as traditional CPU, mainly responsible for image data management and the realization of upper test logic, and FPGA is mainly responsible for image data transcoding and interface implementation, and both of them cooperate to realize various test requirements. In this non-standard system architecture, standard data management method on the market cannot be used to manage images. In addition, because of the dynamic nature of test requirements, a management system with easy use, portability and high scalability is needed. SUMMARY

[0003] The purpose of the present application is to provide a kind of testing display module driving device, system and method, by using a high expansion image data management module, a large amount of image data is managed in limited memory, cooperate with the management of FPGA memory, realize a large number of image display requirements, at the same time, by using LUA script, the business requirements of module test are realized, which greatly reduces the development time of new requirements and reduces the development cost.

[0004] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0005] The first aspect of the present application provides a kind of testing display module driving device, and the driving device includes ARM and FPGA;

[0006] ARM includes: instruction transceiver control module, display module parameter management module, image data management module and FPGA device management module;

[0007] Among them,

[0008] The instruction transceiver control module is used to receive and respond to the display instruction signal sent by the host computer to read the test image data from the data storage of ARM and send it to the image data management module;

[0009] The display module parameter management module is used to receive the display instruction file sent by the host computer and generate test signal according to the display instruction file and send it to the FPGA device management module;

[0010] The image data management module is configured to send test image data to the DDR4 in the FPGA for storage and management and scheduling of the test image data.

[0011] The FPGA device management module is configured to send test signals to the FPGA and receive test result data to the host computer.

[0012] The FPGA retrieves the test image data in the DDR4 according to the test signals to perform display testing on the display module under test, and sends test result data fed back by the display module under test to the FPGA device management module.

[0013] In one specific embodiment, the instruction transceiving control module is also capable of receiving read-write instruction signals sent by the host computer to complete read-write operations on the ARM device data.

[0014] In one specific embodiment, the ARM and the FPGA communicate and transmit data through a PCIe bus.

[0015] In one specific embodiment, the ARM further comprises an I2C interface, a UART interface, a USB interface, a GPIO interface and an SDcard interface.

[0016] In one specific embodiment, the instruction transceiving control module, the display module parameter management module and the FPGA device management module are all implemented by a LUA script language.

[0017] In one specific embodiment, the test image data is divided into seven states, i.e., sleep, waiting for transfer, ready for transmission, transfer, waiting for display, display and error.

[0018] In one specific embodiment,

[0019] The image data management module performs image processing on the image in the sleep state, so that the image in the sleep state is changed to an image in the waiting for transfer state.

[0020] If the image data management module detects that the image in the sleep state changed to the waiting for transfer state is an existing image in the waiting for transfer state, the state of the image is changed back to the sleep state.

[0021] The image data management module performs image preprocessing on the image in the waiting for transfer state to change the image to an image in the ready for transmission state.

[0022] If the image data management module detects that the image changed from the waiting for transfer state to the ready for transmission state is an existing image in the ready for transmission state, the state of the image is changed back to the sleep state.

[0023] The image data management module tests the image in the preparation transmission state, and the test image data is transferred from the ARM to the FPGA, and the state of the image for which the test image data is transferred is the transfer state;

[0024] The image transferred to the FPGA enters the waiting display state, and if the image data management module detects that the image changed from the transfer state to the waiting display state is an image in the existing waiting display state, the state of the image is changed back to the dormant state;

[0025] When the FPGA displays the test image data in the DDR4 according to the test signal to test the display module, the image data management module changes the image in the waiting display state to an image in the display state for the FPGA to call, and if the image data management module detects that the image in the display state is an image that has been displayed, the image in the display state is deleted in the DDR4 to release the memory space of the DDR4, and the image in the display state after the display is completed is changed back to the image in the waiting display state.

[0026] In one specific embodiment,

[0027] If the image data management module detects that the image in the waiting transfer state appears to affect the normal display of the image, the state of the image is changed to the error state;

[0028] If the image data management module detects that the image in the transfer state appears to affect the normal display of the image, the state of the image is changed to the error state.

[0029] The second aspect of the present application provides a driving system for testing a display module, and the driving system comprises:

[0030] The driving device for testing a display module and the host computer described above;

[0031] The host computer is configured to send a display instruction signal and a display instruction file to the driving device, and receive test result data sent by the display module under test via the driving device, and analyze the test result.

[0032] The third aspect of the present application provides a driving method for the driving device for testing a display module described above, and the method comprises:

[0033] The host computer sends a display instruction signal to the instruction transceiver control module of the ARM, and sends a display instruction file to the display module parameter management module of the ARM;

[0034] The instruction transceiving control module reads test image data from the data memory of the ARM and sends the test image data to the image data management module of the ARM in response to the display instruction signal, and the image data management module sends the test image data to the DDR4 in the FPGA for storage and management and scheduling of the test image data.

[0035] The display module parameter management module generates a test signal according to the display instruction file and sends the test signal to the FPGA device management module of the ARM, and the FPGA device management module sends the test signal to the FPGA.

[0036] The FPGA retrieves test image data in the DDR4 according to the test signal to perform display testing on the display module under test.

[0037] The display module under test responds to the display testing and feeds back test result data to the FPGA device management module through the FPGA.

[0038] The FPGA device management module sends the received test result data to the host computer.

[0039] The host computer receives the test result data and analyzes the test result.

[0040] The present application has the following advantages:

[0041] The driving device, system and method for testing a display module provided by the present application manage a large amount of image data in limited memory by using a high expansibility image data management module, cooperate with the management of the FPGA memory, realize a large amount of image display requirements, and realize the business requirements of module testing by using LUA scripts, thereby greatly reducing the development time of new requirements and reducing the development cost. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings in the following description are one embodiment of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0043] Figure 1 The composition structure block diagram of a driving system for testing a display module according to one embodiment of the present application is shown.

[0044] Figure 2 The composition structure schematic diagram of an ARM in a driving device for testing a display module according to one embodiment of the present application is shown.

[0045] Figure 3 Fig. 1 shows a schematic diagram of image state switching when an image data management module of an ARM in a driving device of a display module under test manages and schedules test image data according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the technical solutions of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. The present application is described in detail below through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make modifications and improvements without departing from the principles of the present application, which should also be considered within the protection scope of the present application.

[0047] The present embodiment provides a driving system of a display module under test, which comprises: Figure 1 As shown in the figure, the driving system comprises a host computer and a driving device of a display module under test. The host computer is configured to send display instruction signals and display instruction files to the driving device when performing display testing on the display module under test, and receive test result data sent by the display module under test via the driving device and analyze the test result.

[0048] The hardware of the driving device comprises a driving substrate, an ARM and an FPGA. The driving substrate is configured to provide a path for signal or data transmission, and the ARM and the FPGA are arranged on the driving substrate.

[0049] The input end of the ARM is connected to the host computer. The ARM and the FPGA communicate and transmit data via a PCIe bus. The FPGA is connected to the display module under test via a display interface. The PCIe bus used can achieve a bus bandwidth of 32 Gbps, and the actual effective rate can reach 2 GBps, which fully meets the data transmission requirements of large-size display modules at present and in the future. In addition, the ARM is also extended with commonly used I2C interface, UART interface, USB interface, GPIO interface and SDcard interface, which are used to realize additional control requirements or storage expansion.

[0050] As shown in the figure, the software of the ARM mainly comprises four modules, including an instruction transceiving control module, a display module parameter management module, an image data management module and an FPGA device management module. Figure 2 The ARM further comprises a data storage, which is configured to store test image data.

[0051]

[0052] ​The instruction transceiving control module is configured to receive and respond to a display instruction signal sent by the host computer to read test image data from the data storage of the ARM and send the test image data to the image data management module. Those skilled in the art can understand that the display instruction signal is only an example, and the instruction transceiving control module can accept and respond to various instruction signals from different interfaces and different protocols, for example, the instruction transceiving control module can also receive a read-write instruction signal sent by the host computer to complete the read-write operation of the data of the ARM device, for example, adding new test image data to the data storage of the ARM, reading or deleting existing test image data in the data storage of the ARM, and modifying or adding and deleting device parameters of the ARM.

[0053] The display module parameter management module is configured to receive a display instruction file sent by the host computer and generate a test signal according to the display instruction file and send the test signal to the FPGA device management module.

[0054] The image data management module is configured to send test image data to the DDR4 in the FPGA for storage and management and scheduling of the test image data, so as to complete the display of more and larger image data under limited resources.

[0055] The FPGA device management module is configured to send a test signal to the FPGA and receive test result data to the host computer.

[0056] The FPGA retrieves test image data in the DDR4 according to the test signal to display and test the display module under test, and sends test result data fed back by the display module under test to the FPGA device management module.

[0057] The instruction transceiving control module, the display module parameter management module, and the FPGA device management module are closely matched with the LUA script language layer, that is, the instruction transceiving control module, the display module parameter management module, and the FPGA device management module are implemented by the LUA script language, and information related to the module detection business is implemented and scheduled by the LUA script language. Using the LUA script to implement the business requirements of the display module test greatly reduces the development time of new requirements, reduces the workload of maintenance personnel, and reduces the development cost.

[0058] ARM reads the test image data from the data storage and transports the test image data to the FPGA DDR4 memory space through the PCIe high-speed bus for storage and preparation for display. The DDR4 is used as a buffer space. When the total amount of test image data to be displayed is greater than the memory space of the DDR4, a complete management mechanism is needed to solve the contradiction between the limited memory and the large amount of test image data and to ensure the response time of the test image data. The management of the image data depends on the image data management module. For the image to be displayed for testing, the state of the image object is checked, and the processing method is selected according to the actual situation. Finally, the test image data in the DDR4 memory is displayed.

[0059] As shown in the figure, Figure 3 The test image data is divided into seven states: sleep, waiting for transfer, preparing to transfer, transfer, waiting for display, display, and error.

[0060] For images in the sleep state, the image data management module performs image processing on the images in the sleep state, so that the images in the sleep state are converted into images in the waiting for transfer state.

[0061] If the image data management module detects that the image in the sleep state is converted into the waiting for transfer state, the state of the image is converted back to the sleep state. If the image data management module detects that the image in the waiting for transfer state has image loss or image error, etc. affecting normal display of the image, the state of the image is converted to the error state.

[0062] For images in the waiting for transfer state, the image data management module converts the images in the waiting for transfer state into images in the preparing to transfer state after image preprocessing. The preprocessing can extract the key information of the test image data and convert the effective data of the image into a unified RAW format, which is convenient for subsequent processing.

[0063] If the image data management module detects that the image in the waiting for transfer state is converted into the preparing to transfer state, the state of the image is converted back to the sleep state.

[0064] For images in the preparing to transfer state, the image data management module transfers the test image data from the ARM to the FPGA for the images in the preparing to transfer state. The state of the image for test image data transfer is the transfer state. If the image data management module detects that the image in the transfer state has image loss or image error, etc. affecting normal display of the image, the state of the image is converted to the error state.

[0065] The image successfully transferred to the FPGA enters a waiting display state, and if the image data management module detects that the image transferred from the transfer state to the waiting display state is an existing image in the waiting display state, the state of the image is changed back to the dormant state.

[0066] When the FPGA displays the test image data in the DDR4 according to the test signal to test the display module, the image data management module changes the image in the waiting display state to the image in the display state for the FPGA to call, and if the image data management module detects that the image in the display state is an image that has been displayed, the image in the display state is deleted in the DDR4, i.e., changed to the dormant state to release the memory space of the DDR4. The display state image normally called to complete the display is changed back to the image in the waiting display state.

[0067] The state of the test image data stored in the ARM data storage without any operation is called the dormant state. The change back to the dormant state means that no operation is performed on the image, and the test image data of the image only exists in the ARM data storage.

[0068] The image data management module uses data structures such as queues, linked lists, and hash tables, so that the module has high scalability and adaptability, and in the future, for larger image data or more complex images, only the configuration parameters need to be modified to quickly realize.

[0069] In another aspect, the embodiment provides a driving method of the driving device of the test display module, and the method comprises:

[0070] The host computer sends a display instruction signal to the instruction transceiver control module of the ARM and sends a display instruction file to the display module parameter management module of the ARM.

[0071] The instruction transceiver control module reads the test image data from the data storage of the ARM and sends the test image data to the image data management module of the ARM in response to the display instruction signal, and the image data management module sends the test image data to the DDR4 in the FPGA for storage and management and scheduling of the test image data. The data storage of the ARM can store a large amount of test image data, and the instruction transceiver control module can read the required test image data from the data storage according to the display instruction signal.

[0072] The display module parameter management module generates a test signal according to the display instruction file and sends the test signal to an FPGA device management module of the ARM, and the FPGA device management module sends the test signal to the FPGA; wherein the display instruction file comprises display requirement information such as display parameters, display modes, etc., and the FPGA device management module completes the configuration of the display control register of the FPGA through the PCIe bus by sending the test signal.

[0073] The FPGA retrieves test image data in the DDR4 according to the test signal to perform display testing on the display module under test, wherein the retrieval of the test image data according to the test signal is performed according to the display control register of the FPGA configured according to the test signal.

[0074] The display module under test responds to the display testing and feeds back test result data to the FPGA device management module through the FPGA.

[0075] The FPGA device management module sends the received test result data to the host computer.

[0076] The host computer receives the test result data and analyzes the test result.

[0077] The display module testing drive device, system and method provided by the embodiment can realize data transmission and management among different processors, manage a large amount of image data in limited memory by using a high expansibility image data management module, realize a large amount of image display requirements by cooperating with the management of the FPGA memory, realize the business requirements of module testing by using the LUA script, greatly reduce the development time of new requirements, reduce the workload of maintenance personnel, reduce the development cost, achieve the rapid implementation of testing requirements and have portability and scalability, and in the future, the business requirement adjustment image management strategy can be installed to speed up the response time of image display in specific scenarios.

[0078] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the implementation modes of the present application. For those skilled in the art, on the basis of the above description, other different forms of changes or variations can be made, and it is impossible to enumerate all the implementation modes here. Any obvious changes or variations derived from the technical solutions of the present application still fall within the protection scope of the present application.

Claims

1. A driving device for testing display modules, characterized in that, The driving device comprises an ARM and an FPGA; The ARM comprises an instruction transceiving control module, a display module parameter management module, an image data management module and an FPGA device management module; The instruction transceiving control module is configured to receive a display instruction signal sent by a host computer, read test image data from a data storage of the ARM and send the test image data to the image data management module in response to the display instruction signal; The display module parameter management module is configured to receive a display instruction file sent by the host computer, generate a test signal according to the display instruction file and send the test signal to the FPGA device management module; The image data management module is configured to send the test image data to a DDR4 in the FPGA for storage and management and scheduling of the test image data; The FPGA device management module is configured to send the test signal to the FPGA and receive test result data from the FPGA and send the test result data to the host computer; The FPGA retrieves the test image data in the DDR4 according to the test signal, performs display testing on a display module under test and sends test result data fed back by the display module under test to the FPGA device management module; The test image data comprises a dormant state; The image data management module performs image processing on the image in the dormant state, so that the image in the dormant state is converted into an image in a waiting transition state; If the image data management module detects that the image in the waiting transition state is an existing image in the waiting transition state, the state of the image is converted back to the dormant state; If the image data management module detects that the image in the waiting transition state is an existing image in the waiting transition state, the state of the image is converted back to the dormant state; The image data management module performs transfer of the test image data from the ARM to the FPGA, and the state of the image for which the test image data is transferred is a transition state; The image transferred to the FPGA enters a waiting display state, and if the image data management module detects that the image in the transition state is an existing image in the waiting display state, the state of the image is converted back to the dormant state; When the FPGA retrieves the test image data in the DDR4 according to the test signal to perform display testing on the display module under test, the image data management module converts the image in the waiting display state into an image in a display state for the FPGA to retrieve, and if the image data management module detects that the image in the display state is an existing image that has been displayed, the image in the display state is deleted in the DDR4 to release the memory space of the DDR4; the image in the display state after the display is completed is converted back to the image in the waiting display state; The state of the test image data in the ARM data storage that is not operated is referred to as a dormant state; The data structure of the image data management module is one or more of a queue, a linked list and a hash table; The instruction transceiving control module, the display module parameter management module and the FPGA device management module are implemented by a LUA script language. ​ 2. The drive apparatus according to claim 1, characterized by The instruction transceiving control module is also capable of receiving a read-write instruction signal sent by the host computer to complete the read-write operation of the ARM device data.

3. The drive apparatus according to claim 1, characterized by The ARM and the FPGA communicate and transmit data through a PCIe bus.

4. The drive apparatus according to claim 1, characterized by The ARM further comprises an I2C interface, a UART interface, a USB interface, a GPIO interface and an SDcard interface.

5. The drive apparatus according to claim 1, characterized by The test image data further comprises: There are six states: waiting for transfer, preparing for transmission, transfer, waiting for display, display and error.

6. The driving device according to claim 5, wherein, The image data management module converts the image in the waiting for transfer state into an image in the preparing for transmission state after image preprocessing.

7. The driving device according to claim 6, wherein, If the image data management module detects that the image in the waiting for transfer state has an abnormal display, the state of the image is converted into the error state; If the image data management module detects that the image in the transfer state has an abnormal display, the state of the image is converted into the error state.

8. A driving system for a test display module, characterized in that, The driving system comprises: The driving device and the host computer of the test display module according to any one of claims 1-7; The host computer is configured to send a display instruction signal and a display instruction file to the driving device, and receive test result data sent by the display module under test via the driving device, and analyze the test result.

9. A driving method of a driving device of a test display module according to any one of claims 1 to 7, characterized by, The method comprises: The host computer sends a display instruction signal to the instruction transceiving control module of the ARM, and sends a display instruction file to the display module parameter management module of the ARM; The instruction transceiving control module reads test image data from the data storage of the ARM and sends the test image data to the image data management module of the ARM in response to the display instruction signal, the image data management module sends the test image data to the DDR4 in the FPGA for storage and management and scheduling of the test image data; The display module parameter management module generates a test signal according to the display instruction file and sends the test signal to the FPGA device management module of the ARM, and the FPGA device management module sends the test signal to the FPGA; The FPGA retrieves the test image data in the DDR4 according to the test signal to perform display testing on the display module under test; The display module under test responds to the display testing and feeds back test result data to the FPGA device management module through the FPGA; The FPGA device management module sends the received test result data to the host computer; The host computer receives the test result data and analyzes the test result.

Images