Processor verification method and related device

Abstract

The present application discloses a processor verification method and related devices. The method includes: obtaining a target string of a first programming language by an emulated processor, compiling the target string to obtain a target file in an N -ary format, where N is a positive integer; loading the target file into the storage space of a first hardware processor through a backdoor access mechanism, and passing the starting address of the storage space where the target string is located to a second hardware processor, where the first hardware processor includes the emulated processor, and the second hardware processor is another hardware processor different from the first hardware processor; the second hardware processor obtaining the target string based on the starting address in a backdoor read manner. By adopting the embodiments of the present application, it is possible to achieve co - simulation of two different languages during the processor verification process.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a processor verification method and related devices. Background Art

[0002] At present, as the complexity of SOC becomes higher and higher, the challenge of SOC verification is also increasing. There must be a CPU as the brain of SOC. At this time, it is more appropriate to use C program as stimulus, which is also the mainstream CPU, DSP integrated verification and SOC verification method, which can simulate the real behavior of software in the early stage.

[0003] Of course, System Verilog, as a mainstream hardware verification language, is also an indispensable part of chip verification. When combining C and System Verilog to verify the chip, the C program is executed by the CPU inside the SOC, and the SystemVerilog environment is executed by the real physical CPU. The two languages ​​are different and the execution entities are also different. Therefore, how to achieve co-simulation of two different languages ​​in the processor verification process needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a processor verification method and related devices, which can realize collaborative simulation of two different languages ​​during the processor verification process.

[0005] In a first aspect, an embodiment of the present application provides a processor verification method, the method comprising:

[0006] Acquire a target character string of a first programming language by using a simulation processor, and compile the target character string to obtain a target file in an N-base format, where N is a positive integer;

[0007] Loading the target file into a storage space of a first hardware processor through a backdoor access mechanism, and passing the first address of the storage space where the target string is located to a second hardware processor, wherein the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor;

[0008] The second hardware processor obtains the target character string based on the first address in a back-door read manner.

[0009] In a second aspect, an embodiment of the present application provides a processor verification device, the device comprising: a transmission unit and an acquisition unit, wherein:

[0010] The transmission unit is configured as follows:

[0011] Acquire a target character string of a first programming language by simulating a processor, and compile the target character string to obtain a target file in an N-base format, where N is a positive integer;

[0012] Loading the target file into a storage space of a first hardware processor through a backdoor access mechanism, and passing the first address of the storage space where the target string is located to a second hardware processor, wherein the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor;

[0013] The acquisition unit is configured to:

[0014] The target character string is acquired based on the first address in a back-door reading manner by the second hardware processor.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes a first hardware processor and a second hardware processor, wherein:

[0016] The first hardware processor is configured to load the target file into the storage space through the backdoor access mechanism, and pass the first address of the storage space where the target string is located to the second hardware processor;

[0017] The second hardware processor is configured to obtain the target character string based on the first address in a back-door reading manner;

[0018] The target file is obtained by acquiring a target string of a first programming language by using a simulation processor and compiling the target string; the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor.

[0019] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory is used to store one or more programs and is configured to be executed by the processor, wherein the program includes a method for executing some or all of the steps described by the first party.

[0020] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps described in the first aspect of the embodiment of the present application.

[0021] In a sixth aspect, an embodiment of the present application provides a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute some or all of the steps described in the first aspect of the embodiment of the present application. The computer program product may be a software installation package.

[0022] The implementation of the embodiments of the present application has the following beneficial effects:

[0023] It can be seen that the processor verification method and related devices described in the embodiments of the present application use a simulation processor to obtain a target string of a first programming language, compile the target string, and obtain a target file in N-binary format, where N is a positive integer; the target file is loaded into the storage space of the first hardware processor through a backdoor access mechanism, and the first address of the storage space where the target string is located is passed to the second hardware processor, and the first hardware processor includes a simulation processor; the second hardware processor obtains the target string based on the first address in a backdoor reading manner, and the second hardware processor is another hardware processor different from the first hardware processor. During the processor verification process, commands can be transmitted in the form of strings to establish a "bridge" between the two hardware processors, thereby realizing collaborative simulation of two different languages. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0026] Figure 2 It is a schematic diagram of the software structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 3A It is a schematic diagram of the architecture of a collaborative simulation system provided in an embodiment of the present application;

[0028] Figure 3B It is a demonstration schematic diagram based on C and System Verilog communication provided by an embodiment of the present application;

[0029] Figure 3C It is a flow chart of sending a letter to System Verilog based on C provided in an embodiment of the present application;

[0030] Figure 4A It is a schematic flowchart of a processor verification method provided by an embodiment of the present application;

[0031] Figure 4B It is a schematic flowchart of another processor verification method provided by an embodiment of the present application;

[0032] Figure 4C It is a schematic flowchart of another processor verification method provided by an embodiment of the present application;

[0033] Figure 4D It is a schematic flowchart of another processor verification method provided by an embodiment of the present application;

[0034] Figure 5 It is a schematic structural diagram of another electronic device provided by an embodiment of the present application;

[0035] Figure 6 It is a schematic structural diagram of another electronic device provided by an embodiment of the present application;

[0036] Figure 7 It is a block diagram of the functional units of a processor verification device provided by an embodiment of the present application. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings.

[0038] To better understand the solutions of the embodiments of the present application, the following first introduces the relevant terms and concepts that may be involved in the embodiments of the present application.

[0039] In specific implementation, the electronic device may include various devices with processor functions, such as handheld devices (smartphones, tablets, etc.), vehicle-mounted devices (navigators, assisted reverse systems, dash cams, vehicle-mounted refrigerators, etc.), wearable devices (smart bracelets, wireless earphones, smart watches, smart glasses, etc.), computing devices or other processing devices connected to a wireless modem, and various forms of user equipment (User Equipment, UE), mobile station (Mobile Station, MS), virtual reality / augmented reality devices, terminal devices, etc. The electronic device may also be a base station or a server or a verification platform.

[0040] The first part, the software and hardware operating environment of the technical solutions disclosed in the present application is introduced as follows.

[0041] As shown in the figure, Figure 1The structural schematic diagram of the electronic device 100 is shown. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone interface 170D, a sensor module 180, a compass 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0042] It can be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than those illustrated, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0043] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor AP, a modem processor, a graphics processing unit GPU, an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processor NPU, etc. Among them, different processing units may be independent components or integrated in one or more processors. In some embodiments, the electronic device 100 may also include one or more processors 110. Among them, the controller can generate operation control signals according to the instruction operation code and timing signals to complete the control of fetching and executing instructions. In some other embodiments, a memory may also be provided in the processor 110 for storing instructions and data. Exemplarily, the memory in the processor 110 may be a cache memory. This memory can save the instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use this instruction or data again, it can be directly called from the memory. In this way, repeated access is avoided, the waiting time of the processor 110 is reduced, and thus the efficiency of the electronic device 100 in processing data or executing instructions is improved. The processor may also include an image processor, and the image processor may be a preprocess image signal processor (Pre-ISP), which can be understood as a simplified ISP and can also perform some image processing operations. For example, it can obtain image statistical information.

[0044] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a SIM card interface, and / or a USB interface, etc. Among them, the USB interface 130 is an interface that complies with the USB standard specification, and specifically may be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 130 can be used to connect a charger to charge the electronic device 100, and can also be used to transfer data between the electronic device 100 and peripheral devices. The USB interface 130 can also be used to connect headphones to play audio through the headphones.

[0045] It can be understood that the interface connection relationship between the modules illustrated in the embodiments of the present application is only for illustrative purposes and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0046] The charging management module 140 is used to receive a charging input from a charger. The charger may be a wireless charger or a wired charger. In some embodiments of wired charging, the charging management module 140 may receive the charging input of the wired charger through the USB interface 130. In some embodiments of wireless charging, the charging management module 140 may receive the wireless charging input through the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also supply power to the electronic device through the power management module 141.

[0047] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives the inputs from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the external memory, the display screen 194, the camera 193, the wireless communication module 160, etc. The power management module 141 can also be used to monitor parameters such as the battery capacity, the number of battery cycles, and the battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be disposed in the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 can also be disposed in the same device.

[0048] The wireless communication function of the electronic device 100 can be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modulation and demodulation processor, and the baseband processor, etc.

[0049] The antenna 1 and the antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization rate of the antennas. For example: the antenna 1 can be multiplexed as the diversity antenna of the wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0050] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G / 6G, etc. applied to the electronic device 100. The mobile communication module 150 can include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves by the antenna 1, filter, amplify, etc. the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves through the antenna 1 and radiate it out. In some embodiments, at least some functional modules of the mobile communication module 150 can be disposed in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 can be disposed in the same device.

[0051] The wireless communication module 160 may provide solutions for wireless communications applied to the electronic device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite systems (GNSSs), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. The wireless communication module 160 may be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 may also receive the signals to be sent from the processor 110, perform frequency modulation and amplification on them, and convert them into electromagnetic waves through the antenna 2 for radiation.

[0052] The electronic device 100 implements the display function through the GPU, the display screen 194, and the application processor, etc. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to execute mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs, which execute program instructions to generate or change the display information.

[0053] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel may adopt a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini light-emitting diode (miniLED), a MicroLed, a Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include one or more display screens 194.

[0054] The electronic device 100 can implement the shooting function through the ISP, camera 193, video codec, GPU, display screen 194, application processor, etc.

[0055] The ISP is used to process the data fed back by the camera 193. For example, when taking a photo, the shutter is opened, and light passes through the lens and is transmitted to the camera photosensitive element. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing and converts it into an image visible to the naked eye. The ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be disposed in the camera 193.

[0056] The camera 193 is used to capture still images or videos. An object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal and then transmits the electrical signal to the ISP to convert it into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in standard RGB, YUV, etc. formats. In some embodiments, the electronic device 100 may include one or more cameras 193.

[0057] The digital signal processor is used to process digital signals. In addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device 100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy, etc.

[0058] The video codec is used to compress or decompress digital videos. The electronic device 100 can support one or more video codecs. In this way, the electronic device 100 can play or record videos in multiple coding formats, such as: Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0059] The NPU is a neural-network (NN) computing processor. By learning from the biological neural network structure, for example, learning from the transmission mode between human brain neurons, it can quickly process the input information and can also continuously self-learn. Through the NPU, applications such as intelligent cognition of the electronic device 100 can be realized, such as: image recognition, face recognition, speech recognition, text understanding, etc.

[0060] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to implement the storage capacity expansion of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement the data storage function. For example, files such as music and videos are saved in the external memory card.

[0061] The internal memory 121 can be used to store one or more computer programs, and the one or more computer programs include instructions. The processor 110 can run the above instructions stored in the internal memory 121, so that the electronic device 100 executes the method for displaying page elements provided in some embodiments of the present application, as well as various applications and data processing, etc. The internal memory 121 can include a storage program area and a storage data area. Among them, the storage program area can store the operating system; the storage program area can also store one or more applications (such as a gallery, contacts, etc.). The storage data area can store the data created during the use of the electronic device 100 (such as photos, contacts, etc.). In addition, the internal memory 121 can include high-speed random access memory, and can also include non-volatile memory, such as one or more disk storage components, flash memory components, universal flash storage (UFS), etc. In some embodiments, the processor 110 can run the instructions stored in the internal memory 121, and / or the instructions stored in the memory provided in the processor 110, to make the electronic device 100 execute the method for displaying page elements provided in the embodiments of the present application, as well as other applications and data processing. The electronic device 100 can implement audio functions through the audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor, etc. For example, music playback, recording, etc.

[0062] The sensor module 180 can include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0063] Among them, the pressure sensor 180A is used to sense pressure signals and can convert pressure signals into electrical signals. In some embodiments, the pressure sensor 180A can be disposed on the display screen 194. There are many types of pressure sensors 180A, such as resistive pressure sensors, inductive pressure sensors, capacitive pressure sensors, etc. The capacitive pressure sensor can include at least two parallel plates with conductive materials. When a force acts on the pressure sensor 180A, the capacitance between the electrodes changes. The electronic device 100 determines the intensity of the pressure according to the change in capacitance. When a touch operation acts on the display screen 194, the electronic device 100 detects the intensity of the touch operation according to the pressure sensor 180A. The electronic device 100 can also calculate the position of the touch according to the detection signal of the pressure sensor 180A. In some embodiments, touch operations acting on the same touch position but with different touch operation intensities can correspond to different operation instructions. For example: when a touch operation with a touch operation intensity less than the first pressure threshold acts on the short message application icon, the instruction to view the short message is executed. When a touch operation with a touch operation intensity greater than or equal to the first pressure threshold acts on the short message application icon, the instruction to create a new short message is executed.

[0064] The gyroscope sensor 180B can be used to determine the motion posture of the electronic device 100. In some embodiments, the angular velocity of the electronic device 100 around three axes (i.e., the X, Y, and Z axes) can be determined by the gyroscope sensor 180B. The gyroscope sensor 180B can be used for anti-shake during shooting. Exemplarily, when the shutter is pressed, the gyroscope sensor 180B detects the angle of jitter of the electronic device 100, calculates the distance that the lens module needs to compensate according to the angle, and enables the lens to offset the jitter of the electronic device 100 through reverse movement to achieve anti-shake. The gyroscope sensor 180B can also be used for navigation and somatosensory game scenarios.

[0065] The acceleration sensor 180E can detect the magnitude of the acceleration of the electronic device 100 in various directions (generally three axes). When the electronic device 100 is stationary, the magnitude and direction of gravity can be detected. It can also be used to identify the posture of the electronic device and is applied to applications such as horizontal and vertical screen switching and pedometers.

[0066] The ambient light sensor 180L is used to sense the ambient light brightness. The electronic device 100 can adaptively adjust the brightness of the display screen 194 according to the sensed ambient light brightness. The ambient light sensor 180L can also be used to automatically adjust the white balance during photography. The ambient light sensor 180L can also cooperate with the proximity light sensor 180G to detect whether the electronic device 100 is in the pocket to prevent accidental touch.

[0067] The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can use the collected fingerprint characteristics to achieve fingerprint unlocking, access to application locks, fingerprint photography, fingerprint answering of incoming calls, etc.

[0068] The temperature sensor 180J is used to detect temperature. In some embodiments, the electronic device 100 utilizes the temperature detected by the temperature sensor 180J to execute a temperature processing strategy. For example, when the temperature reported by the temperature sensor 180J exceeds a threshold, the electronic device 100 reduces the performance of the processor near the temperature sensor 180J in order to reduce power consumption and implement thermal protection. In some other embodiments, when the temperature is lower than another threshold, the electronic device 100 heats the battery 142 to avoid abnormal shutdown of the electronic device 100 caused by low temperature. In some other embodiments, when the temperature is lower than yet another threshold, the electronic device 100 boosts the output voltage of the battery 142 to avoid abnormal shutdown caused by low temperature.

[0069] The touch sensor 180K, also known as the "touch panel". The touch sensor 180K can be disposed on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, also known as the "touch screen". The touch sensor 180K is used to detect touch operations acting thereon or nearby. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through the display screen 194. In some other embodiments, the touch sensor 180K can also be disposed on the surface of the electronic device 100, at a different position from that of the display screen 194.

[0070] Exemplarily, Figure 2 A software structure block diagram of the electronic device 100 is shown. The layered architecture divides the software into several layers, and each layer has a clear role and division of labor. Communication between layers is through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer. The application layer can include a series of application packages.

[0071] As Figure 2 shown, the application layer can include applications such as the camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, short message, etc.

[0072] The application framework layer provides application programming interfaces (APIs) and programming frameworks for the applications in the application layer. The application framework layer includes some predefined functions.

[0073] As Figure 2 shown, the application framework layer can include the window manager, content provider, view system, phone manager, resource manager, notification manager, etc.

[0074] The window manager is used to manage window programs. The window manager can obtain the display screen size, determine whether there is a status bar, lock the screen, capture the screen, etc.

[0075] The content provider is used to store and obtain data, and make this data accessible to application programs. The data can include videos, images, audio, incoming and outgoing calls, browsing history and bookmarks, phone books, etc.

[0076] The view system includes visual controls, such as controls for displaying text, controls for displaying pictures, etc. The view system can be used to build application programs. The display interface can be composed of one or more views. For example, a display interface including a text message notification icon can include a view for displaying text and a view for displaying pictures.

[0077] The phone manager is used to provide the communication function of the electronic device 100. For example, the management of call states (including answering, hanging up, etc.).

[0078] The resource manager provides various resources for application programs, such as localized strings, icons, pictures, layout files, video files, and so on.

[0079] The notification manager enables application programs to display notification information in the status bar. It can be used to convey notification-type messages, which can automatically disappear after a short stay without user interaction. For example, the notification manager is used to inform that the download is completed, message reminders, etc. The notification manager can also be a notification that appears in the system top status bar in the form of a chart or scroll bar text, such as the notification of a background-running application program, and can also be a notification that appears on the screen in the form of a dialogue window. For example, prompt text information in the status bar, emit a prompt tone, the electronic device vibrates, the indicator light flashes, etc.

[0080] Android Runtime includes core libraries and a virtual machine. Android runtime is responsible for the scheduling and management of the Android system.

[0081] The core libraries contain two parts: one part is the functional functions that need to be called by the Java language, and the other part is the core libraries of Android.

[0082] The application layer and the application framework layer run in the virtual machine. The virtual machine executes the Java files of the application layer and the application framework layer as binary files. The virtual machine is used to perform functions such as the management of object life cycles, stack management, thread management, security and exception management, and garbage collection.

[0083] The system library may include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing library (such as: OpenGL ES), 2D graphics engine (such as: SGL), etc.

[0084] The surface manager is used to manage the display subsystem and provides the fusion of 2D and 3D layers for multiple applications.

[0085] The media library supports the playback and recording of multiple common audio and video formats, as well as static image files, etc. The media library can support multiple audio and video coding formats, such as: MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc.

[0086] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, synthesis, and layer processing, etc.

[0087] The 2D graphics engine is a drawing engine for 2D drawing.

[0088] The kernel layer is the layer between hardware and software. The kernel layer at least includes a display driver, a camera driver, an audio driver, and a sensor driver.

[0089] The second part, the processor verification method and related devices disclosed in the embodiments of the present application are introduced as follows.

[0090] In the related art, System Verilog, as a mainstream hardware verification language, is also an essential part of chip verification. When verifying a chip by combining C and System Verilog, as Figure 3A shown, for the specific verification process, verification personnel can first write a C program, and then, compile the program into a hexadecimal format file through compilers such as GCC, and then load it into the on-chip SRAM of the SOC by means of backdoor writing, and the CPU then fetches instructions from the SRAM and executes the instructions. At the same time, the verification environment (SystemVerilog environment) is responsible for the start and end of the entire simulation platform, and directly controls hardware signals through the direct programming interface (DPI) of SystemVerilog, etc.

[0091] In specific implementation, since the C program is executed by the CPU inside the SOC and the SystemVerilog environment is executed by a real physical CPU, with different languages and different execution entities for both, how to perform co-simulation has become an inevitable problem to be solved in the verification process.

[0092] Based on this, a continuous SRAM address space on the chip can be used as a "bridge" for communication between C and SystemVerilog. As Figure 3B shown, each address in this address space represents a specific field. The two parties express their intentions by passing in different fields. The fields usually include: Command, WDATA (writedata), RDATA (readdata), EDATA (expectdata), Mask, Resp. Through the above fields, common functions such as synchronization, communication, printing, reading and writing, and comparison between C and SystemVerilog can be realized. The specific implementation principle is to abstract common functions such as synchronization, communication, and printing between C and SystemVerilog into commands represented by 1, 2, 3..., and pass them into the Figure 3B command field as shown, and pass other relevant data into other fields. For example, when the two parties communicate, it is agreed that when the Command field is 1, it means that C wants to "send a letter" to SystemVerilog, and the mailbox address and content of the letter are passed through the WDATA and RDATA fields.

[0093] For example, as Figure 3C shown, it is an example of C sending a letter. First, C calls the function MB_PUT(0x100, 0x123). Inside the function, 0x100 will be used as the mailbox address, 0x123 will be used as the mail content, and 0x1 represents the command of sending a letter, which are written into the corresponding fields respectively. Then, when SystemVerilog monitors the command field and detects 0x1, since it is agreed in advance that 0x1 means C has sent a letter, SystemVerilog will then parse the WDATA and RDATA fields to obtain the mailbox address and content of this letter, and finally write them into the mailbox queue of SystemVerilog. Then, SystemVerilog can obtain the mail content of 0x100 (mailbox address) at any time by executing MB_GET(0x100, message).

[0094] Similarly, the command can also be that SystemVerilog "sends a letter" to C, C "retrieves the letter" from the mailbox, and C requests SystemVerilog to print a string, etc.

[0095] The above-mentioned communication mode between System Verilog and C is similar to the traditional client-server mode. System Verilog acts as the server, constantly monitoring the Command field, and C acts as the client, responsible for sending commands and other valid data segments. When System Verilog detects a valid command, it will parse the command according to the pre-agreed rules, obtain the valid data segment corresponding to the command, and then perform the corresponding operations.

[0096] In the above-mentioned related technologies, although co-simulation between C and System Verilog can be achieved, there are also the following disadvantages:

[0097] 1. Since information needs to be transmitted by reading and writing 6 global shared fields, competition for shared resources is introduced. For example, when a command is being transmitted, if an external interrupt occurs at this time, causing the CPU to enter the interrupt service routine, the interrupt service routine usually also initiates some new commands. Since the previous command is still in an unfinished state, the reading and writing of the same field by the new command will damage the same field of the previous command. To prevent conflicts, generally an additional mutex mechanism such as interrupt masking will be adopted, or a FIFO queue will be implemented internally to save unfinished commands. No matter which technology is adopted, the code will become more complex, the execution efficiency will be lower, and the portability will also be poor.

[0098] 2. In the related technologies, there are many implemented commands. In addition to communication commands, there are also synchronization commands, string printing commands, 8 / 16 / 32 / 64-bit data reading and writing commands, comparison commands, etc. Each command uses different fields. For each command, there must be a corresponding function, resulting in complex code implementation and difficult maintenance.

[0099] 3. In the related technologies, the support for multi-core is slightly insufficient. To support multi-core, usually a separate dedicated address space is allocated for each core as the interaction space between C and System Verilog, so that the cores do not affect each other. This mechanism will require additional code to be added to each command implementation to determine the ID of the current core, and then select the corresponding address space, once again making the code more complex.

[0100] In short, due to the above reasons, the code implementation in the related technologies is often relatively complex. The implementation of each command is relatively independent, making it difficult to maintain uniformly. The addition or deletion of commands also requires more modification points in the source files, and the portability is poor.

[0101] Furthermore, aiming at the defects of the above-mentioned related technologies, based on Figure 1 or Figure 2 the structure andFigure 3A For the co-simulation system shown, the present application provides for reference Figure 4A , Figure 4A FIG. is a schematic flowchart of a processor verification method provided by an embodiment of the present application. As shown in the figure, the processor verification method includes:

[0102] 401. Use an emulated processor to obtain a target string in a first programming language, compile the target string to obtain a target file in N - base format, where N is a positive integer; load the target file into the storage space of a first hardware processor through a backdoor access mechanism, and pass the starting address of the storage space where the target string is located to a second hardware processor, where the first hardware processor includes the emulated processor, and the second hardware processor is another hardware processor different from the first hardware processor.

[0103] Among them, the first hardware processor may include at least one of the following: application processor AP, modem processor, GPU, ISP, controller, video codec, DSP, system on chip (SOC), baseband processor, field - programmable gate array (FPGA), NPU, etc. The emulated processor is used to simulate the functions of the first hardware processor. It can be a piece of program code, or it can also be understood as a software module. The first hardware processor includes the emulated processor, and the emulated processor can be a software module of the first hardware processor. This software module can implement the running process of the content that needs to be simulated, enabling co - simulation between the two hardware processors. The second hardware processor may include at least one of the following: application processor AP, modem processor, GPU, ISP, controller, video codec, DSP, SOC, baseband processor, FPGA, NPU, etc.

[0104] Among them, the first programming language can be a programming language that can run on the first hardware processor. Taking SOC as an example, the first programming language can be c or c++. The above N can be a positive integer. For example, N is 16, or N is 32.

[0105] Among them, the above storage space can be static random - access memory (SRAM) or dynamic random - access memory (DRAM).

[0106] In a specific implementation, the first hardware processor can be the processor to be used for testing. Since it emulates the actual functions of the first hardware processor through an emulation processor. Taking the first hardware processor as an SOC as an example, it can include an Interconnect Bus. The emulation processor is connected to a memory through the internal link bus, and the memory can include image.hex, which can be implemented in the C language. The first hardware processor includes an external interface, which is used to receive the string input in the C language. The second hardware processor can exist in the electronic device involved in the present application. The first hardware processor and the second hardware processor can also be integrated together.

[0107] In a specific implementation, the emulation processor can obtain the target string of the first programming language, compile the target string to obtain a target file in N - base format, where N is a positive integer, and the N - base format can be the ASCII code. It can also load the target file into the storage space of the first hardware processor through a backdoor access mechanism to pass the starting address of the storage space where the target string is located to the second hardware processor.

[0108] Optionally, step 401, obtaining the target string of the first programming language, can include the following steps:

[0109] 41. Obtain the target test content;

[0110] 42. Determine the target string corresponding to the target test content, and the first string is presented in the form of the first programming language.

[0111] Among them, the target test content can be set by the user himself or be the system default. For example, multiple virtual keys can be preset in advance, each virtual key corresponds to a test content, each test content can correspond to a string, and the target test content is the test content corresponding to one of the virtual keys. The mapping relationship between the preset test content and the string can be stored in advance. Furthermore, the target string corresponding to the target test content can be determined based on this mapping relationship. Different test contents can include different commands, and different commands are used to implement different functions.

[0112] Optionally, it can also include the following steps:

[0113] A1. The emulation processor passes the starting address of the target string as an actual parameter of a function to the stack address;

[0114] A2. Pass the stack address to the specified string stack address in the interaction space.

[0115] In a specific implementation, the target string can exist as a variable-argument function represented in a first programming language. Furthermore, based on the storage space, the simulation processor passes the starting address of the target string as an actual argument of the function to the stack address, and then passes the stack address to the specified string stack address in the interaction space. The specified string stack address can pre-specify a space.

[0116] In a specific implementation, for example, taking C language as an example, when writing a string in a C program, after compilation, the compiler generates a file in hexadecimal format. The string in the C program is compiled into the corresponding ASCII code and saved in this file. The environment automatically loads this file into the SRAM space of the SOC through the backdoor access mechanism. The C program only needs to pass the starting address of the SRAM where the string is located to System Verilog, and then System Verilog can obtain the string in the way of backdoor reading. As Figure 4B shown, in the embodiment of the present application, taking the example of C sending a letter to System Verilog again, assuming the name of the implemented variable-argument function is INFO, the C program first calls INFO("MB_PUT"). After being compiled by the compiler, the string MB_PUT is translated into the corresponding ASCII code, and then, through the backdoor method, it is loaded into the SRAM of the SOC. Furthermore, the string MB_PUT can be obtained through address indexing.

[0117] Furthermore, optionally, the following steps may further be included:

[0118] B1. The second processor monitors in real time whether there is a valid stack address in the interaction space;

[0119] B2. When it is monitored that there is the valid stack address in the interaction space, obtain the stack address from the specified string stack address through the valid stack address, and then obtain the starting address based on the stack address, and execute the step of obtaining the target string in the way of backdoor reading based on the starting address.

[0120] In the embodiment of the present application, the valid stack address refers to a stack address within a preset storage address range, and the preset storage address range can be pre-set or the system default. In order to enable System Verilog to obtain the target string, when the C program runs, it first passes the starting address of the target string as an actual argument of the function to the stack address, and then passes this stack address to the specified string stack address StringStackAddress field in the interaction space. As Figure 4CAs shown, at the same time, System Verilog can be regarded as a server, constantly monitoring whether there is a valid stack address in the interaction space. Once a valid address is monitored, the target string is obtained by reading the address through the back door, that is, the stack address is obtained from the specified string stack address through the valid stack address, and then the start address is obtained based on the stack address. Based on this start address, the target string is obtained, and the target string is parsed to obtain the request command of the client, that is, the command content of the target string.

[0121] Of course, for other commands, such as synchronization, etc., the same function can be called in a similar way. The same function can correspond to a call interface, achieving unified interfaces and simple maintenance. Only the input strings are different. In the embodiments of the present application, C and System Verilog can successfully transfer different commands through the StringStackAddress field and a function.

[0122] Optionally, the target string at least includes: the command content of one command.

[0123] Among them, the target string can at least include the command content of one command. For example, the command content can be any one of the following: synchronization, communication, printing, reading and writing, comparison.

[0124] Optionally, the target string further includes at least one of the following contents: target address, transfer content.

[0125] Among them, the target string can not only include the command content of one command, but also include the target address and transfer content. For example, the C program first calls INFO(“MB_PUT”, 0x10, 0x123). At this time, there are three actual parameters of the function. MB_PUT indicates that the command is to send a letter, 0x10 represents the mailbox address (target address) of sending the letter, and 0x123 represents the content of sending the letter (transfer content).

[0126] 402. The second hardware processor obtains the target string based on the start address by reading through the back door.

[0127] Among them, the second hardware processor can obtain the target string based on the start address by reading through the back door. Furthermore, the target string can be parsed based on the second programming language, that is, the System Verilog language.

[0128] Optionally, after step 402, the following steps may further be included:

[0129] The second hardware processor parses the target string through the second programming language to obtain a target parsing command; and performs an operation corresponding to the target parsing command.

[0130] Among them, the second programming language can be System Verilog. The second hardware processor can parse the target string through the second programming language to obtain a target parsing command, and then execute an operation corresponding to the target parsing command. In this way, cooperative simulation of the two processors can be achieved, that is, the verification process of the processor is realized.

[0131] In the embodiment of the present application, commands may no longer be transmitted based on the command field, so the command field is omitted. Taking C language as an example, the implementation mechanism adopted in the embodiment of the present application is that C uses a variable argument function for transmitting a string (that is, except for the first parameter of the function, the number and type of other parameters are variable) to send a segment of string to SystemVerilog. Different strings represent different commands, and System Verilog obtains the current command by parsing the string.

[0132] In addition, in the embodiment of the present application, all data related to commands are transmitted based on the stack space, so global shared fields such as WDATA, RDATA, and EDATA can be omitted. This reduces the code complexity and can also improve the running efficiency. When C or System Verilog transmits data to the other party, the data is transmitted by operating on the stack address where the data is located. Specifically, when a C function is called, the values of the actual parameters are sequentially passed into the stack space in the order from right to left, and the data is pushed onto the stack in an increasing manner downward. When the stack address where the first parameter, that is, the leftmost parameter, is located is told to the other party, the other party can obtain the stack addresses of other relevant data, and thus obtain all the data.

[0133] The embodiment of the present application can also continue to take the example of C sending a letter to System Verilog, as Figure 4D shown. For example, when running INFO(“MB_PUT”, 0x10, 0x123), it can include the mailbox address and content of sending a letter. The C program first calls INFO(“MB_PUT”, 0x10, 0x123). The actual parameters of this function are three. MB_PUT indicates that the command is to send a letter, 0x10 represents the mailbox address of sending a letter, and 0x123 represents the content of sending a letter. Then, according to the actual parameters and the stack pushing characteristics, when the stack address where the first parameter, that is, the starting address of the string, is located is passed into the StringStackAddress field, System Verilog can first obtain the string and parse it. According to the result, it determines the number and type of other relevant data, and then increments the stack address multiple times to finally obtain all the data related to this command.

[0134] Of course, by the same token, the same applies to other commands. Since the number and type of other data corresponding to each command are pre-agreed, when System Verilog parses a command, it can also obtain the number and type of data related to that command.

[0135] In the embodiments of the present application, since commands are transmitted based on a specific string, the command field can be reduced and replaced with the StringStackAddress field; data is transmitted based on the stack space, reducing global fields such as WDATA, RDATA, EDATA, MASK, and RESP. In addition, all commands and related data can be implemented based on one field (StringStackAddress), that is, a variable-parameter function and a non-fixed stack address space.

[0136] In this way, the benefits of having only one field and using the stack space are that it avoids competition for shared resources and enhances support for multi-core. First, since the stack address space has the property of first input first output (FIFO) by itself, there is no need to worry about competition for shared resources caused by interrupts; second, for multi-core, the environment does not need to allocate a dedicated address space for each core separately, and all cores share the StringStackAddress field. Because even if multiple cores access this field simultaneously, since each write operation is atomic in hardware, no competition or command loss will occur, and using the independence of the stack address space of each core, the mechanism of transmitting data based on the stack space ensures that data related to commands will not be lost.

[0137] In addition, the benefit of having only one variable-parameter function is that it greatly reduces the code complexity of the entire environment, improves the unity and maintainability of the underlying code, and the addition or deletion of commands has little impact on the source file, so it also has good portability. Using the stack space also has a benefit for a multi-core environment in that the ID of the core corresponding to the current command can be obtained in real time. Since the stack space of each core is independent, System Verilog can calculate the corresponding ID while obtaining the stack address, thus providing more debug information to verification personnel.

[0138] It can be seen that in the processor verification method described in the embodiment of the present application, the simulation processor obtains the target string of the first programming language, compiles the target string, and obtains a target file in N-binary format, where N is a positive integer; the target file is loaded into the storage space of the first hardware processor through the backdoor access mechanism, and the first address of the storage space where the target string is located is passed to the second hardware processor, the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor; the second hardware processor obtains the target string based on the first address in a backdoor reading manner, and can pass commands in the form of strings during the processor verification process, thereby establishing a "bridge" between the two hardware processors, and thereby realizing collaborative simulation of two different languages.

[0139] In accordance with the above embodiment, please refer to Figure 5 , Figure 5 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. As shown in the figure, the electronic device includes a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, the processor is an analog processor in the first hardware processor or a second hardware processor. In the embodiment of the present application, the program includes instructions for executing the following steps:

[0140] Acquire a target character string of a first programming language by using a simulation processor, and compile the target character string to obtain a target file in an N-base format, where N is a positive integer;

[0141] Loading the target file into a storage space of a first hardware processor through a backdoor access mechanism, and passing the first address of the storage space where the target string is located to a second hardware processor, wherein the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor;

[0142] The second hardware processor obtains the target character string based on the first address in a back-door read manner.

[0143] Optionally, the program further includes instructions for executing the following steps:

[0144] The simulation processor passes the first address of the target string to the stack address as the actual parameter of the function; and passes the stack address to the designated string stack address of the interactive space.

[0145] Optionally, the program further includes instructions for executing the following steps:

[0146] The second hardware processor monitors in real time whether there is a valid stack address in the interactive space; when monitoring the existence of the valid stack address in the interactive space, the stack address is obtained from the specified string stack address through the valid stack address, and then the first address is obtained based on the stack address, and the step of obtaining the target string based on the first address in a back-door reading manner is executed.

[0147] Optionally, the target character string includes at least: command content of a command.

[0148] Optionally, the target character string further includes at least one of the following contents: a target address and a transfer content.

[0149] Optionally, the program further includes instructions for executing the following steps:

[0150] The second hardware processor parses the target character string using a second programming language to obtain a target parsing command; and executes an operation corresponding to the target parsing command.

[0151] Optionally, in the step of obtaining the target character string in the first programming language, the program includes instructions for executing the following steps:

[0152] Get the target test content;

[0153] The target character string corresponding to the target test content is determined, the first character string being presented in the form of the first programming language.

[0154] It can be seen that the electronic device described in the embodiment of the present application includes a processor, which is an analog processor in the first hardware processor or a second hardware processor. The analog processor obtains a target string in a first programming language, compiles the target string, and obtains a target file in an N-binary format, where N is a positive integer; the target file is loaded into the storage space of the first hardware processor through a backdoor access mechanism, and the first address of the storage space where the target string is located is passed to the second hardware processor. The first hardware processor includes the analog processor, and the second hardware processor is another hardware processor different from the first hardware processor; the second hardware processor obtains the target string based on the first address in a backdoor reading manner, and can pass commands in the form of strings during the processor verification process to establish a "bridge" between the two hardware processors, thereby realizing collaborative simulation of two different languages.

[0155] In accordance with the above embodiment, please refer to Figure 6 , Figure 6 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. As shown in the figure, the electronic device includes a first hardware processor and a second hardware processor, wherein:

[0156] The first hardware processor is configured to load the target file into the storage space through the backdoor access mechanism, and pass the first address of the storage space where the target string is located to the second hardware processor;

[0157] The second hardware processor is configured to obtain the target character string based on the first address in a back-door reading manner;

[0158] The target file is obtained by acquiring a target string of a first programming language by using a simulation processor and compiling the target string; the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor.

[0159] It can be seen that the electronic device described in the embodiment of the present application includes a first hardware processor and a second hardware processor, the simulation processor obtains a target string of a first programming language, compiles the target string, and obtains a target file in N-binary format, where N is a positive integer; the target file is loaded into the storage space of the first hardware processor through a backdoor access mechanism, and the first address of the storage space where the target string is located is passed to the second hardware processor, the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor; the second hardware processor obtains the target string based on the first address in a backdoor reading manner, and can pass commands in the form of strings during the processor verification process, thereby establishing a "bridge" between the two hardware processors, and thereby realizing collaborative simulation of two different languages.

[0160] The above mainly introduces the scheme of the embodiment of the present application from the perspective of the execution process on the method side. It is understandable that, in order to realize the above functions, the electronic device includes a hardware structure and / or software module corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments provided herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0161] The embodiment of the present application can divide the electronic device into functional units according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0162] Figure 7 700 is a functional unit block diagram of a processor verification device 700 involved in an embodiment of the present application. The processor verification device 700 includes a transmission unit 701 and an acquisition unit 702, wherein:

[0163] The transmission unit 701 is configured as follows:

[0164] Acquire a target character string of a first programming language by simulating a processor, and compile the target character string to obtain a target file in an N-base format, where N is a positive integer;

[0165] Loading the target file into a storage space of a first hardware processor through a backdoor access mechanism, and passing the first address of the storage space where the target string is located to a second hardware processor, wherein the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor;

[0166] The acquisition unit 702 is configured to:

[0167] The target character string is acquired based on the first address in a back-door reading manner by the second hardware processor.

[0168] Optionally, the device 700 is further specifically used for:

[0169] The simulation processor transfers the first address of the target string to the stack address as the actual parameter of the function; and the stack address is transferred to the designated string stack address of the interactive space.

[0170] Optionally, the device 700 is further specifically used for:

[0171] The second hardware processor is used to monitor in real time whether there is a valid stack address in the interactive space; when the valid stack address is monitored to exist in the interactive space, the stack address is obtained from the specified string stack address through the valid stack address, and then the first address is obtained based on the stack address, and the step of obtaining the target string based on the first address in a back-door reading manner is executed.

[0172] Optionally, the target character string includes at least: command content of a command.

[0173] Optionally, the target character string further includes at least one of the following contents: a target address and a transfer content.

[0174] Optionally, the device 700 is further specifically used for:

[0175] The target character string is parsed by the second hardware processor in a second programming language to obtain a target parsing command; and an operation corresponding to the target parsing command is executed.

[0176] Optionally, in the aspect of acquiring the target character string in the first programming language, the transmitting unit 701 is specifically used for:

[0177] Get the target test content;

[0178] The target character string corresponding to the target test content is determined, the first character string being presented in the form of the first programming language.

[0179] It can be seen that in the processor verification device described in the embodiment of the present application, the simulation processor obtains the target string of the first programming language, compiles the target string, and obtains a target file in N-binary format, where N is a positive integer; the target file is loaded into the storage space of the first hardware processor through the backdoor access mechanism to pass the first address of the storage space where the target string is located to the second hardware processor, the first hardware processor includes the simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor; the second hardware processor obtains the target string based on the first address in a backdoor reading manner, and can pass commands in the form of strings during the processor verification process, thereby establishing a "bridge" between the two hardware processors, and thereby realizing collaborative simulation of two different languages.

[0180] Among them, the transmission unit 701 can be a first hardware processor or a simulation processor in the first hardware processor, and the acquisition unit 702 can be a second hardware processor. Based on the above unit modules, the functions or steps of any of the above methods can be implemented.

[0181] This embodiment also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the above-mentioned computer program enables a computer to execute the embodiments of the present application to implement any method in the above-mentioned embodiments.

[0182] This embodiment further provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the above-mentioned related steps to implement any method in the above-mentioned embodiments.

[0183] In addition, an embodiment of the present application further provides a processor verification device, which may specifically be a chip, component or module. The device may include a processor and a memory connected to each other. The memory is used to store computer execution instructions. When the device runs, the processor may execute the computer execution instructions stored in the memory to enable the chip to execute any one of the above method embodiments.

[0184] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be elaborated here.

[0185] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0186] In several embodiments provided in the present application, it should be understood that the disclosed device and method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, and the indirect coupling or communication connection of the device or unit may be in electrical, mechanical or other forms.

[0187] The unit described as a separated component may or may not be physically separated, and the component displayed as a unit may be a physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0188] In addition, each functional unit in each embodiment of the present application may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0189] When an integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0190] The above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A processor verification method, characterized in that, Applied to an electronic device, the electronic device includes a first hardware processor and a second hardware processor; the first hardware processor includes a simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor; the simulation processor is a software module of the first hardware processor, and the software module is used to implement the running process of the content to be simulated, so that the first hardware processor and the second hardware processor can achieve collaborative simulation; the method includes: Using the simulation processor to obtain a target character string of a first programming language, and compiling the target character string to obtain a target file in an N-base format, where N is a positive integer; Loading the target file into the storage space of the first hardware processor through a backdoor access mechanism, and passing the first address of the storage space where the target string is located to the second hardware processor; The second hardware processor obtains the target character string based on the first address in a back-door read manner.

2. The method according to claim 1, characterized in that The method further comprises: The simulation processor passes the first address of the target string to the stack address as an actual parameter of the function; and The stack address is passed into the specified string stack address of the interactive space.

3. The method according to claim 2, wherein The method further comprises: The second hardware processor monitors in real time whether there is a valid stack address in the interactive space; when monitoring the existence of the valid stack address in the interactive space, the stack address is obtained from the specified string stack address through the valid stack address, and then the first address is obtained based on the stack address, and the step of obtaining the target string based on the first address in a back-door reading manner is executed.

4. The method according to any one of claims 1-3, characterized in that, The target character string includes at least: a command content of a command.

5. The method according to claim 4, characterized in that, The target character string also includes at least one of the following contents: a target address and a transfer content.

6. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: The second hardware processor parses the target character string using a second programming language to obtain a target parsing command; and executes an operation corresponding to the target parsing command.

7. The method according to any one of claims 1 to 3, characterized in that, The step of obtaining a target character string in the first programming language includes: Get the target test content; The target character string corresponding to the target test content is determined, where the target character string is presented in the form of the first programming language.

8. A processor verification device, characterized in that, Applied to an electronic device, the electronic device comprises a first hardware processor and a second hardware processor; the first hardware processor comprises a simulation processor, and the second hardware processor is another hardware processor different from the first hardware processor; the simulation processor is a software module of the first hardware processor, and the software module is used to implement the running process of the content to be simulated, so that the first hardware processor and the second hardware processor can achieve collaborative simulation; the device comprises: a transmission unit and an acquisition unit, wherein, The transmission unit is configured as follows: Acquire a target character string of a first programming language through the simulation processor, and compile the target character string to obtain a target file in an N-base format, where N is a positive integer; Load the target file into the storage space of the first hardware processor through a backdoor access mechanism, and pass the starting address of the storage space where the target string is located to the second hardware processor; The obtaining unit is configured to: Obtain the target string based on the starting address in a backdoor read manner through the second hardware processor.

9. An electronic device, characterized in that, The electronic device includes a first hardware processor and a second hardware processor. The first hardware processor includes an analog processor, and the second hardware processor is another hardware processor different from the first hardware processor; the analog processor is a software module of the first hardware processor, and this software module is used to implement the running process of the content that needs to be simulated, so that collaborative simulation can be achieved between the first hardware processor and the second hardware processor; wherein, The first hardware processor is configured to load a target file into the storage space through a backdoor access mechanism, and pass the starting address of the storage space where the target string is located to the second hardware processor; The second hardware processor is configured to obtain the target string based on the starting address in a backdoor read manner; Wherein, the target file is obtained by the analog processor obtaining the target string of the first programming language and compiling the target string.

10. An electronic device, characterized in that, The electronic device includes a processor and a memory. The memory is used to store one or more programs and is configured to be executed by the processor. The programs include instructions for performing the steps in the method according to any one of claims 1-7.

11. A computer-readable storage medium, characterized in that, A computer program for electronic data exchange is stored, wherein the computer program causes a computer to execute the method according to any one of claims 1-7.

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