Non-volatile memory device performing bidirectional channel pre-charge and programming method thereof

Abstract

A non-volatile memory device is provided that performs bidirectional channel pre-charge during programming. A programming operation of the non-volatile memory device performs a first pre-charge in a bit line direction and a second pre-charge in a source line direction simultaneously to channels of a plurality of strings of cells to initialize the channels prior to programming selected memory cells. The first pre-charge operation pre-charges the channels of the plurality of strings of cells using a first pre-charge voltage applied to the bit lines through first and second string selection transistors, while the second pre-charge operation pre-charges the channels of the plurality of strings of cells using a second pre-charge voltage applied to the source lines through first and second ground selection transistors.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0095521, filed on July 30, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor memory device, and more specifically, to a non-volatile memory device and a programming method thereof that performs bidirectional channel pre-charging during programming. Background Technology

[0004] Semiconductor memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. As examples of non-volatile memory devices, flash memory devices are used in Universal Serial Bus (USB) memory, digital cameras, mobile phones, smartphones, tablets, memory cards, and solid-state drives (SSDs). To improve the storage capacity and integration of memory, non-volatile memory devices with storage cells stacked in a three-dimensional (3D) structure have been investigated, such as 3D NAND flash memory.

[0005] In 3D NAND flash memory, multiple programming cycles can be executed until programming is complete according to incremental step pulse programming (hereinafter referred to as "ISPP"). As the programming cycle increases, the programming voltage of the selected memory cell gradually increases. To reduce programming interference, the programming operation can have a programming sequence where the memory cells at the top of the cell string are programmed first. Before executing the programming cycle on the selected memory cell, initialization or precharge (hereinafter referred to as unselect string initial precharge (USIP)) operations can be performed on the channels of multiple cell strings. However, when the memory cells at the top of the cell string are in a programming state, the USIP operation on the cell string may not be possible because some channels corresponding to the programmed memory cell may be negatively boosted, and the programmed memory cell has a high threshold voltage. Programming interference problems and / or hot carrier injection problems may exist, which severely affect the memory cells arranged in the cell string.

[0006] According to a tendency of a large capacity of a memory block, it is not easy to provide a performance suitable for the increased capacity using an existing control technique or algorithm. Accordingly, a memory controller can manage a memory block as a plurality of small sub-blocks by dividing the memory block in units of word lines. For example, the memory controller can not erase the memory block in units of the memory block, but can erase the memory block in units of sub-blocks. Also, a programming order of cell strings can be set in units of sub-blocks.

[0007] Even if the cell strings are programmed in units of sub-blocks by using the block management method of the memory controller, it can be beneficial to improve the programming performance if the USIP operation is performed on the cell strings regardless of the programmed memory cells, and if such a function is possible. SUMMARY

[0008] The present disclosure provides a nonvolatile memory device capable of improving programming performance by performing bidirectional channel pre-charge during programming and a programming method thereof.

[0009] According to an aspect of the present inventive concept, there is provided a programming method of a nonvolatile memory device including a plurality of cell strings connected between a plurality of bit lines and a source line, each of the plurality of cell strings including a first string selection transistor, a second string selection transistor, a plurality of memory cells, a second ground selection transistor, and a first ground selection transistor arranged in series between one of the plurality of bit lines and the source line, the programming method including initializing a channel for the plurality of cell strings, and performing a programming operation on selected memory cells among the plurality of memory cells. The initializing of the channel includes performing first pre-charge of the channel of the plurality of cell strings through the first string selection transistor and the second string selection transistor using a first pre-charge voltage applied to the plurality of bit lines, performing second pre-charge of the channel of the plurality of cell strings through the first ground selection transistor and the second ground selection transistor using a second pre-charge voltage applied to the source line, applying a ground voltage or a first negative voltage lower than the ground voltage to a first string selection line connected to the first string selection transistor, applying the ground voltage to a second string selection line connected to the second string selection transistor, applying the ground voltage to a second ground selection line connected to the second ground selection transistor, and applying the ground voltage or a second negative voltage lower than the ground voltage to a first ground selection line connected to the first ground selection transistor. The first pre-charge and the second pre-charge are performed simultaneously.

[0010] According to another aspect of the present inventive concepts, a programming method of a non-volatile memory device including a plurality of cell strings connected between a plurality of bit lines and a source line, each of the plurality of cell strings including a first string selection transistor, a second string selection transistor, a plurality of memory cells, a second ground selection transistor, and a first ground selection transistor arranged in series between one of the plurality of bit lines and the source line, includes initializing channels for the plurality of cell strings, and performing a program operation on selected memory cells among the plurality of memory cells. The initializing of the channels includes applying a word line voltage having a power supply voltage applied to the non-volatile memory device to one or more word lines of programmed memory cells among the plurality of memory cells, performing a first pre-charge on the channels of the plurality of cell strings through the first string selection transistor and the second string selection transistor using a first pre-charge voltage applied to the bit line, and performing a second pre-charge on the channels of the plurality of cell strings through the first ground selection transistor and the second ground selection transistor using a second pre-charge voltage applied to the source line. The first pre-charge and the second pre-charge are performed simultaneously. The power supply voltage is greater than a ground voltage, and the first pre-charge voltage and the second pre-charge voltage are greater than the power supply voltage.

[0011] According to another aspect of the present inventive concepts, a non-volatile memory device includes a memory cell array including a plurality of cell strings connected between a plurality of bit lines and a source line, each of the plurality of cell strings including a first string selection transistor, a second string selection transistor, a plurality of memory cells, a second ground selection transistor, and a first ground selection transistor arranged in series between one of the plurality of bit lines and the source line, and a control circuit configured to perform an operation of initializing channels for the plurality of cell strings and a program operation on selected memory cells among the plurality of memory cells. The control circuit is further configured to, in the operation of initializing the channels, perform a first pre-charge on the channels of the plurality of cell strings through the first string selection transistor and the second string selection transistor using a first pre-charge voltage applied to the bit line, and perform a second pre-charge on the channels of the plurality of cell strings through the first ground selection transistor and the second ground selection transistor using a second pre-charge voltage applied to the source line simultaneously with the first pre-charge. The first pre-charge voltage and the second pre-charge voltage are greater than a power supply voltage applied to the non-volatile memory device. The power supply voltage is greater than a ground voltage. BRIEF DESCRIPTION OF DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating a storage system according to an example embodiment;

[0014] Figure 2 is a block diagram illustrating a memory device according to an example embodiment; Figure 1

[0015] Figure 3 is a cross-sectional view illustrating a memory device according to an example embodiment; Figure 2

[0016] Figure 4 is an equivalent circuit diagram of a memory block according to an example embodiment; Figure 2

[0017] Figure 5 is a diagram illustrating exemplary programming bias conditions of a memory block according to an example embodiment; Figure 4

[0018] Figure 6 is a diagram illustrating a programming method of a memory device according to an example embodiment;

[0019] Figure 7A and Figure 7B is a timing diagram illustrating a programming method of a memory device according to an example embodiment;

[0020] Figure 8A and Figure 8B is a diagram illustrating operation periods included in a programming cycle of a memory device according to an example embodiment;

[0021] Figures 9-16 is a timing diagram illustrating bias conditions of a channel pre-charge period, a bit line set period, and a string select line set period included in a programming cycle of a memory device according to an example embodiment;

[0022] Figure 17 is a flowchart illustrating a programming method of a memory device according to an example embodiment;

[0023] Figures 18A-18C is a diagram illustrating a state of a sub-block in a memory block during a programming operation of a memory device according to an example embodiment;

[0024] Figure 19A and Figure 19B are diagrams conceptually illustrating a relationship between a programming operation and a read recovery operation of a memory device according to an example embodiment; and

[0025] Figure 20 ​​​​is a block diagram illustrating a solid state drive or solid state disk (SSD) that performs a programming method of a memory device according to an example embodiment. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram illustrating a storage system 100 according to an example embodiment.

[0027] REFERENCE Figure 1 The storage system 100 can include a memory controller 110 and at least one memory device 120. Figure 1 The memory device 120 illustrated can be a non-volatile memory device such as a flash memory device, and the storage system 100 can include a data storage medium such as a universal serial bus (USB) memory, a memory card, and a solid state disk (SSD).

[0028] The memory device 120 can perform an erase, program, or read operation under the control of the memory controller 110. The memory device 120 can receive a command CMD and an address ADDR from the memory controller 110 through an input / output line, transmit and receive data DATA for a program operation or a read operation with the memory controller 110. Also, the memory device 120 can receive a control signal CTRL through a control line. The memory device 120 can include a storage unit array 122 and a control circuit 124.

[0029] The storage unit array 122 can include a plurality of storage blocks, and each of the plurality of storage blocks can include a plurality of storage units. For example, the plurality of storage units can be flash memory units. Hereinafter, embodiments of the disclosure will be described in detail with the case where the plurality of storage units are NAND flash memory units. The storage unit array 122 can include a 3D storage unit array including a plurality of cell strings, which will be described in detail with reference to Figure 3 and Figure 4 will be described in detail.

[0030] 3D memory cell array is monolithically formed on at least one physical level of a memory cell array having active regions disposed on a silicon substrate and circuits related to operation of memory cells and formed on or in the substrate. The term "monolithically" means that layers of each level constituting the array are directly stacked on layers of each next level of the array. In embodiments according to the inventive concept, the 3D memory cell array includes strings of cells arranged in a vertical direction so that at least one memory cell is located on another memory cell. The at least one memory cell can include a charge trapping layer. U.S. Patent 7,679,133 B2, U.S. Patent 8,553,466 B2, U.S. Patent 8,654,587 B2, U.S. Patent 8,559,235 B2 and U.S. Patent Application 2011 / 0233648 Al describe suitable configurations of 3D memory cell arrays constituting multiple levels and sharing word lines and / or bit lines between the levels, and the above-mentioned applications are incorporated herein by reference.

[0031] The memory controller 110 can divide one memory block in the memory cell array 122 of the memory device 120 in units of word lines and manage the memory block as a plurality of small sub-blocks. The division of the memory block into the sub-blocks will be described in detail with reference to Figure 18A and Figure 18C The sub-blocks of the memory block are described in detail.

[0032] The control circuit 124 can initialize channels with respect to a plurality of strings of cells in the memory cell array 122 and can perform a program operation on selected memory cells among the plurality of memory cells.

[0033] Figure 2 is a block diagram of the memory device 120 according to an example embodiment. Figure 1

[0034] Referring to Figure 2 , the memory device 120 (e.g., a non-volatile memory device) can include a memory cell array 122, a row decoder 394, a control circuit 124, a page buffer 393, an input / output (I / O) circuit 126, and a voltage generator 127. Although not shown, the memory device 120 can further include an input / output interface.

[0035] The memory cell array 122 can be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. The memory cell array 122 can be connected to the row decoder 394 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL, and can be connected to the page buffer 393 through the bit lines BL. The memory cell array 122 can include a plurality of memory blocks BLK1 to BLKn.

[0036] ​The storage blocks BLK1 to BLKn can each include a plurality of storage cells and a plurality of selection transistors. The storage cells can be connected to the word lines WL, and the selection transistors can be connected to the string selection lines SSL or the ground selection lines GSL. The storage cells of each of the storage blocks BLK1 to BLKn can include single-level cells that store 1-bit data or multi-level cells that store M-bit data (M is an integer equal to or greater than 2).

[0037] The row decoder 394 can select one of the plurality of storage blocks BLK1 to BLKn of the storage cell array 122, select one of the word lines WL of the selected storage block, and can select one of the string selection lines SSL.

[0038] The control circuit 124 can output various internal control signals for performing programming, reading, and erasing operations on the storage cell array 122 based on the command CMD, the address ADDR, and the control signal CTRL transmitted from the memory controller 110. The control circuit 124 can provide the row address R_ADDR to the row decoder 394, can provide the column address C_ADDR to the I / O circuit 126, and can provide the voltage control signal CTRL_VOL to the voltage generator 127.

[0039] The control circuit 124 can first pre-charge the channels of the plurality of cell strings with a first pre-charge voltage of the bit line BL through the first string selection transistor and the second string selection transistor, second pre-charge the channels of the plurality of cell strings with a second pre-charge voltage of the source line through the first ground selection transistor and the second ground selection transistor, and simultaneously perform the first pre-charge and the second pre-charge before programming the selected storage cell.

[0040] The page buffer 393 can function as a write driver or a sense amplifier according to a page buffer control signal PBC. During a read operation, the page buffer 393 can sense the bit line BL of the selected storage cell under the control of the control circuit 124. The sensed data can be stored in a latch in the page buffer 393 setting. The page buffer 393 can dump the data stored in the latch to the I / O circuit 126 through the data line DL under the control of the control circuit 124.

[0041] The I / O circuit 126 can temporarily store the command CMD, the address ADDR, and the data DATA provided from the outside of the memory device 120 through the input / output line I / O. The I / O circuit 126 can temporarily store the read data from the storage cell array 122 and output the data to the outside of the memory device 120 through the input / output line (I / O) at a designated time.

[0042] The voltage generator 127 can generate various types of voltages used for performing programming, reading, and erasing operations on the memory cell array 122 based on the voltage control signal CTRL VOL. Specifically, the voltage generator 127 can generate a word line voltage VWL, e.g., a program voltage, a verify read voltage, a read voltage, a pass voltage, an erase voltage, an erase verify voltage, etc. Also, the voltage generator 127 can generate a first pre-charge voltage VPC1, a second pre-charge voltage VPC2, and a third pre-charge voltage VPC3 based on the voltage control signal CTRL VOL. GIDL BL GIDL CSL

[0043] Figure 3 is a cross-sectional view illustrating a memory device 120 according to an example embodiment. Figure 2

[0044] Referring to Figure 3 , the memory device 120 can have a chip-to-chip (C2C) structure. The C2C structure can refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, a bonding process can include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip to a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metal can include copper (Cu), a Cu-to-Cu bonding can be used. However, example embodiments can not be limited thereto. For example, the bonding metal can also be formed of aluminum (Al) or tungsten (W).

[0045] The peripheral circuit region PERI and the cell region CELL of the memory device 120 can each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0046] The peripheral circuit region PERI can include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, respectively, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. The circuit elements 220a, 220b, and 220c can each include one or more transistors. In an example embodiment, the first metal layers 230a, 230b, and 230c can be formed of tungsten having a relatively high resistivity, and the second metal layers 240a, 240b, and 240c can be formed of copper having a relatively low resistivity.

[0047] In​​​Figure 3 In the example embodiment illustrated, although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are illustrated and described, the present application is not limited thereto, and one or more other metal layers can also be formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more other metal layers formed on the second metal layers 240a, 240b, and 240c can be formed of aluminum or the like having a lower electrical resistivity than that of copper forming the second metal layers 240a, 240b, and 240c.

[0048] The interlayer insulating layer 215 can be disposed on the first substrate 210 and cover the plurality of circuit elements 220a, 220b, and 220c, the first metal layers 230a, 230b, and 230c, and the second metal layers 240a, 240b, and 240c. The interlayer insulating layer 215 can include an insulating material such as silicon oxide, silicon nitride, or the like.

[0049] The lower bonding metals 271b and 272b can be formed on the second metal layers 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b in the peripheral circuit region PERI can be electrically bonded to the upper bonding metals 371b and 372b of the cell region CELL. The lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b can be formed of aluminum, copper, tungsten, or the like.

[0050] In addition, the upper bonding metals 371b and 372b in the cell region CELL can be referred to as first metal pads, and the lower bonding metals 271b and 272b in the peripheral circuit region PERI can be referred to as second metal pads.

[0051] The cell region CELL can include at least one memory block. The cell region CELL can include a second substrate 310 and a common source line 320. On the second substrate 310, a plurality of word lines 331 to 338 (i.e., 330) can be stacked in a direction (Z-axis direction) perpendicular to an upper surface of the second substrate 310. At least one string selection line and at least one ground selection line can be arranged above and below the plurality of word lines 330, respectively, and the plurality of word lines 330 can be disposed between the at least one string selection line and the at least one ground selection line.

[0052] In the bit line bonding region BLBA, the channel structure CHS can extend in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction) and pass through the plurality of word lines 330, at least one string selection line, and at least one ground selection line. The channel structure CHS can include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c can be a bit line contact, and the second metal layer 360c can be a bit line. In an example embodiment, the bit line 360c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0053] In Figure 3 In the example embodiment illustrated, a region in which the channel structure CHS, the bit line 360c, etc., are provided can be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 360c can be electrically connected to the circuit element 220c that provides the page buffer 393 in the peripheral circuit region PERI. The bit line 360c can be connected to the upper bonding metals 371c and 372c in the cell region CELL, and the upper bonding metals 371c and 372c can be connected to the lower bonding metals 271c and 272c connected to the circuit element 220c of the page buffer 393.

[0054] In the word line bonding region WLBA, the plurality of word lines 330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and perpendicular to the first direction, and can be connected to the plurality of cell contact plugs 341 to 347 (i.e., 340). The plurality of word lines 330 and the plurality of cell contact plugs 340 can be connected to each other in pads provided by at least a portion of the plurality of word lines 330 extending in the second direction at different lengths. The first metal layer 350b and the second metal layer 360b can be sequentially connected to the upper portions of the plurality of cell contact plugs 340 connected to the plurality of word lines 330. The plurality of cell contact plugs 340 can be connected to the peripheral circuit region PERI in the word line bonding region WLBA through the upper bonding metals 371b and 372b of the cell region CELL and the lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0055] The plurality of cell contact plugs 340 can be electrically connected to the circuit element 220b that forms the row decoder 394 in the peripheral circuit region PERI. In an example embodiment, the operating voltage of the circuit element 220b of the row decoder 394 can be different from the operating voltage of the circuit element 220c forming the page buffer 393. For example, the operating voltage of the circuit element 220c forming the page buffer 393 can be greater than the operating voltage of the circuit element 220b forming the row decoder 394.

[0056] The common source line contact plug 380 can be disposed in the external pad bonding area PA. The common source line contact plug 380 can be formed of an electrically conductive material such as a metal, a metal compound, polysilicon, etc., and can be electrically connected to the common source line 320. The first metal layer 350a and the second metal layer 360a can be sequentially stacked on an upper portion of the common source line contact plug 380. For example, a region in which the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed can be defined as the external pad bonding area PA.

[0057] The input / output pads 205 and 305 can be disposed in the external pad bonding area PA. Referring to Figure 3 , a lower insulating film 201 covering a lower surface of the first substrate 210 can be formed under the first substrate 210, and the first input / output pad 205 can be formed on the lower insulating film 201. The first input / output pad 205 can be connected to at least one of the plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit area PERI through the first input / output contact plug 203, and can be separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film can be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically separate the first input / output contact plug 203 and the first substrate 210.

[0058] Referring to Figure 3 , an upper insulating film 301 covering an upper surface of the second substrate 310 can be formed on the second substrate 310, and the second input / output pad 305 can be disposed on the upper insulating layer 301. The second input / output pad 305 can be connected to at least one of the plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit area PERI through the second input / output contact plug 303. In an example embodiment, the second input / output pad 305 is electrically connected to the circuit element 220a.

[0059] According to an example embodiment, the second substrate 310 and the common source line 320 can not be disposed in a region in which the second input / output contact plug 303 is disposed. Also, the second input / output pad 305 can not overlap the word line 330 in the third direction (Z-axis direction). Referring to Figure 3 , the second input / output contact plug 303 can be separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and can pass through the interlayer insulating layer 315 of the cell area CELL to be connected to the second input / output pad 305.

[0060] According to example embodiments, the first input / output pad 205 and the second input / output pad 305 can be selectively formed. For example, the memory device 120 can include only the first input / output pad 205 disposed on the first substrate 210 or the second input / output pad 305 disposed on the second substrate 310. Alternatively, the memory device 120 can include both the first input / output pad 205 and the second input / output pad 305.

[0061] In each of the external pad bonding region PA and the bit line bonding region BLBA included in the cell region CELL and the peripheral circuit region PERI, respectively, a metal pattern disposed on the uppermost metal layer can be disposed as a dummy pattern, or the uppermost metal layer can not be disposed.

[0062] In the external pad bonding region PA, the memory device 120 can include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit region PERI, which corresponds to an upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL and has the same cross-sectional shape as the upper metal pattern 372a of the cell region CELL so as to be connected to each other. In the peripheral circuit region PERI, the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI can not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern 372a can be formed in the uppermost metal layer of the cell region CELL, which corresponds to a lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern 273a of the peripheral circuit region PERI.

[0063] The lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b of the cell region CELL by Cu-to-Cu bonding.

[0064] Further, in the bit line bonding region BLBA, an upper metal pattern 392 can be formed in the uppermost metal layer of the cell region CELL, which corresponds to a lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit region PERI and has the same cross-sectional shape as the lower metal pattern 252 of the peripheral circuit region PERI. A contact can not be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL.

[0065] In an example embodiment, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern formed in the uppermost metal layer of either the cell region (CELL) or the peripheral circuit region (PERI) can be formed in the uppermost metal layer of the other. Contacts may not be formed on the reinforcing metal pattern.

[0066] In the example embodiment, the storage cell region CELL can correspond to Figure 1 The memory cell array 122 in the example embodiment. In the example embodiment, the peripheral circuit region PERI may correspond to... Figure 2 The components include a row decoder 394, a voltage generator 127, a control circuit 124, a page buffer 393, and an I / O circuit 126.

[0067] Figure 4 According to the example embodiment Figure 2 The equivalent circuit diagram of the storage block. Figure 4 The storage block shown is a reference. Figure 2 An example of one of a plurality of memory blocks BLK1 to BLKn is described, and a first memory block BLK1 is shown. The first memory block BLK1 represents a 3D memory block formed in a 3D structure on a substrate. A plurality of memory cell strings included in the first memory block BLK1 may be formed in a direction D1 perpendicular to the substrate.

[0068] Reference Figure 4 The first memory block BLK1 may include cell strings NS11 to NS13, NS21 to NS23, and NS31 to NS33, word lines WL1 to WL6, bit lines BL1 to BL3, first ground select lines GIDL_GSL1 to GIDL_GSL3, second ground select lines GSL1 to GSL3, first string select lines GIDL_SSL1 to GIDL_SSL3, second string select lines SSL1 to SSL3, and source line CSL. Figure 4 In the present invention, each of the cell strings NS11 to NS13, NS21 to NS23 and NS31 to NS33 includes six memory cells MC respectively connected to six word lines WL1 to WL6, but the present invention is not limited thereto.

[0069] Each cell string (e.g., NS11) can include a first string selection transistor GIDL SST, a second string selection transistor SST, a plurality of memory cells MC, a first ground selection transistor GIDL GST, and a second ground selection transistor GST. The first string selection transistor GIDL SST can be connected to a first string selection line GIDL SSL1 corresponding thereto, and the second string selection transistor SST can be connected to a second string selection line SSL1 corresponding thereto. The plurality of memory cells MC can be connected to word lines WL1 to WL6 corresponding thereto, respectively. The first ground selection transistor GIDL GST can be connected to a first ground selection line GIDL GSL1 corresponding thereto, and the second ground selection transistor GST can be connected to a second ground selection line GSL1 corresponding thereto. The first string selection transistor GIDL SST can be connected to a corresponding bit line BL1 corresponding thereto, and the first ground selection transistor GIDL GST can be connected to a source line CSL.

[0070] Word lines (e.g., WL1) having the same height in the cell strings NS11 to NS13, NS21 to NS23, and NS31 to NS33 can be commonly connected, and the first ground selection lines GIDL GSL1, GIDL GSL2, and GIDL GSL3, the second ground selection lines GSL1, GSL2, and GSL3, the first string selection lines GIDL SSL1, GIDL SSL2, and GIDL SSL3, and the second string selection lines SSL1, SSL2, and SSL3 can be separated. The cell strings NS11 to NS13, NS21 to NS23, and NS31 to NS33 can include a plurality of memory cells MC, a first string selection transistor GIDL SST, a second string selection transistor SST, a first ground selection transistor GIDL GST, and a second ground selection transistor GST, as will be described later. Figures 18A-18C The word line corresponding to the middle switch line among the plurality of word lines shown. The middle switch line can serve as a reference for dividing one memory block into a plurality of sub-blocks.

[0071] Figure 5 is a diagram illustrating an exemplary program bias condition of a memory block according to an example embodiment. Figure 4 For convenience, Figure 5 The cell strings NS11 and NS21 connected to the first bit line BL1 and the cell strings NS12 and NS22 connected to the second bit line BL2 among the cell strings NS11 to NS13, NS21 to NS23, and NS31 to NS33 of the first memory block BLK1 are shown.

[0072] Referring to Figure 5 , the first bit line BL1 is a program enable bit line to which a relatively low program enable voltage VPER Figure 7A and Figure 7B (e.g., a ground voltage VSS) is applied, and the second bit line BL2 is a program inhibit bit line to which a relatively high program inhibit voltage VINH (e.g., a high voltage VDD) is applied.Figure 7A and Figure 7B The program enable bit lines can correspond to selected strings of cells, and the program inhibit bit lines can correspond to unselected strings of cells.

[0073] Assuming that during the program operation PROGRAM( Figure 7A and Figure 7B ), the cell string NS21 is selected from among the cell strings NS11 and NS21 connected to the first bit line BL1, an off voltage having a ground voltage VSS level can be applied to the first string selection line GIDL_SSL1 and the second string selection line SSL1 connected to the cell string NS11, and an on voltage VSSL1 Figure 7A and Figure 7B ) (e.g., a power supply voltage VDD) can be applied to the first string selection line GIDL_SSL2 and the second string selection line SSL2 connected to the cell string NS21.

[0074] An off voltage having a ground voltage VSS level is applied to the first ground selection lines GIDL_GSL1 and GIDL_GSL2 and the second ground selection lines GSL1 and GSL2. A third precharge voltage VPC Figure 7A and Figure 7B ) higher than the ground voltage VSS and lower than the power supply voltage VDD can be applied to the source line CSL. A program voltage VPGM Figure 7A and Figure 7B ) (e.g., 18 V) is applied to a selected word line (e.g., WL3), and a program pass voltage VPASS1 Figure 7A and Figure 7B ) is applied to unselected word lines (e.g., WL2 and WL4).

[0075] Under this program bias condition, for example, 18 V is applied to the gate of the storage cell A, and the channel voltage is 0 V. Because a strong electric field is formed between the gate and the channel of the storage cell A, the storage cell A can be programmed. Because the channel voltage of the storage cell B is the power supply voltage VDD, and a weak electric field is formed between the gate and the channel of the storage cell B, the storage cell B can not be programmed. Because the channels of the storage cells C and D are in a floating state, the channel voltage rises to a boosted level by the program pass voltage VPASS1, and the storage cells C and D can not be programmed.

[0076] Figure 7A is a diagram showing a program method of a memory device according to an example embodiment. Figure 7BA plurality of programming loops LOOP(1), LOOP(2), LOOP(3),..., and LOOP(N+3) for incremental step pulse programming (ISPP) are shown.

[0077] Referring to Figure 6 , the plurality of programming loops LOOP(1), LOOP(2), LOOP(3),..., and LOOP(N+3) can be sequentially executed until programming is completed according to ISPP. As the programming loops are repeated, the programming voltages VPGM1, VPGM2, VPGM3,..., and VPMGN+3 can be gradually increased.

[0078] Each programming loop (LOOP(i), i is a natural number) can include a program period PROGRAM and a verify period VERIFY, in which a program voltage VPGMi, i is a natural number, is applied to a selected word line WLs Figure 6 and Figure 6 ) to program a selected memory cell, and a verify read voltage VRD is applied to the selected word line WLs to verify whether the programming is successful in the verify period VERIFY.

[0079] In Figure 7A , an Nth programming voltage VPMGN applied in an Nth programming loop LOOP(N) among the programming loops LOOP(i) can be used as a criterion for identifying an operation for initializing channels of a plurality of cell strings in the memory cell array 122. The Nth programming voltage VPGMN can be selected or made to be a relatively high voltage level. For the Nth programming voltage VPGMN, the programming operation can be made to include a first channel pre-charge period E-USIP in the program period PROGRAM of each of the programming loops from the first programming loop LOOP(1) to the N-1th programming loop LOOP(N-1), and a second channel pre-charge period GIDL-USIP in the program period of each of the programming loops starting from the Nth programming loop LOOP(N).

[0080] Figure 7B and Figure 6 are timing diagrams showing a programming method of a memory device according to an example embodiment. Figure 7A Operation periods included in the first programming loop LOOP(1) of Figure 7B are shown, and Figure 7A operation periods included in the Nth programming loop LOOP(N) are shown. It should be noted that the timing diagrams described in the present disclosure are not necessarily drawn to scale.

[0081] Referring to Figure 6 , Figure 7B and Figure 5The first program loop LOOP(1) can include a program period PROGRAM, in which a program voltage VPGM is applied to the selected word lines WLs to program the selected memory cells, and a verify period VERIFY, in which a verify read voltage VRD is applied to the selected word lines WLs to verify whether the programming is successful. The program period PROGRAM can include a first channel pre-charge period E-USIP, a bit line set period PBLS, a string select line set period PSSLS, a program execute period PEXE, and a program recovery period PRVC. The verify period VERIFY can include a verify read period RD and a read recovery period RRCV.

[0082] Prior to the string select line set period PSSLS, the channels of the plurality of cell strings can be initialized or pre-charged (USIP) during the first channel pre-charge period E-USIP and the bit line set period PBLS. Both the bit line BL and the source line CSL can be used to initialize the plurality of cell strings using the supply voltage VDD.

[0083] For the USIP on the bit line BL side, the supply voltage VDD as the program inhibit voltage VINH can be applied to the program inhibit bit line, and the ground voltage VSS as the program enable voltage level can be applied to the program enable bit line. The on voltage VSSL1 can be applied to the selected first string select line GIDL_SSL and the selected second string select line SSL, and the off voltage (i.e., the ground voltage VSS) can be applied to the unselected first string select line GIDL_SSL and the unselected second string select line SSL. Thus, the channels of the selected cell strings among the plurality of cell strings can be initialized through the selected first string select transistor GIDL_SST and the selected second string select transistor SST.

[0084] For the USIP on the source line CSL side, the supply voltage VDD can be applied to the source line CSL, and the on voltage VGSL can be applied to the first ground select line GIDL_GSL and the second ground select line GSL. The supply voltage VDD can be referred to as a fourth pre-charge voltage VCSL. The channels of the plurality of cell strings can be initialized through the first ground select transistor GIDL_GST and the second ground select transistor GST.

[0085] At a time point ta of the first channel pre-charge period E-USIP and the bit line set period PBLS, a program inhibit voltage VINH or a program enable voltage VPER can be maintained in the bit line BL according to the value of the write data. An on voltage VSSL1 can be maintained in the selected first string select line GIDL_SSL and the selected second string select line SSL, and an off voltage can be maintained in the unselected first string select line GIDL_SSL and the unselected second string select line SSL. A power supply voltage VDD can be maintained in the source line CSL, and an on voltage VGSL can be maintained in the first ground select line GIDL_GSL and the second ground select line GSL.

[0086] At a completion time point tb of the bit line set period PBLS (i.e., a start time point tb of the string select line set period PSSLS), an off voltage (i.e., a ground voltage VSS) can be applied to the source line CSL, the first ground select line GIDL_GSL and the second ground select line GSL.

[0087] At a start time point tc of the program execution period PEXE, a program pass voltage VPASS1 can be applied to the selected word line WLs and the unselected word line WLu, and after a certain period of time, a program voltage VPGM can be applied to the selected word line WLs. During the program execution period PEXE, the selected first string select line GIDL_SSL and the selected second string select line SSL are maintained at the on voltage VSSL1, and the unselected first string select line GIDL_SSL and the unselected second string select line SSL are maintained at the ground voltage VSS.

[0088] The program pass voltage VPASS1 applied to the unselected word line WLu can be maintained until a completion time point td of the program execution period PEXE, and at this time point, the channel voltage increases according to a self-boosting effect in the cell string connected to the unselected word line WLu.

[0089] The storage cells connected to the selected word line WLs can be programmed according to the program voltage VPGM applied to the selected word line WLs of the selected cell string, depending on the set voltage of the bit line BL. When the program voltage VPGM is applied to the selected word line WLs, the unselected cell string remains in a boosted state, and programming of the storage cells connected to the selected word line WLs of the unselected cell string is prevented.

[0090] At the completion time point td of the program execution period PEXE (i.e., a start time point td of the program recovery period PRCV), the bit line BL, the first string select line GIDL_SSL and the second string select line SSL, the selected word line WLs and the unselected word line WLu are recovered to the ground voltage VSS.

[0091] At a start time point te of the verify read period RD, an on voltage VSSL2 can be applied to the selected first string select line GIDL_SSL and the selected second string select line SSL, and a ground voltage VSS can be maintained in the unselected first string select line GIDL_SSL and the unselected second string select line SSL. The voltage level of the on voltage VSSL2 of the verify read period RD can be higher than the voltage level of the on voltage VSSL1 of the program execution period PEXE.

[0092] During the verify read period RD, a read pass voltage VPASS2 can be applied to the unselected word line WL u, and a verify read voltage VRD can be applied to the selected word line WLs. The read pass voltage VPASS2 has a voltage level that always turns on the storage unit regardless of the program state of the storage unit. The verify read voltage VRD has a voltage level for determining the threshold voltage level of the selected storage unit.

[0093] During the verify read period RD, an on voltage VGSL equal to or higher than the threshold voltage Vth of each of the first ground select transistor GIDL_GST and the second ground select transistor GST can be applied to the selected first ground select line GIDL_GSL and the selected second ground select line GSL, and a ground voltage VSS can be applied to the unselected first ground select line GIDL_GSL and the unselected second ground select line GSL. The first ground select transistor GIDL_GST and the second ground select transistor GST driven by the selected first ground select line GIDL_GSL and the selected second ground select line GSL are turned on, and the first ground select transistor GIDL_GST and the second ground select transistor GST driven by the unselected first ground select line GIDL_GSL and the unselected second ground select line GSL are turned off.

[0094] During the verify read period RD, the voltage of the bit line BL is formed according to the threshold voltage state of the selected storage unit to correspond to a data “1” or a data “0”. The voltage of the bit line BL can be sensed to determine the value of the data stored in the selected storage unit. Prior to the start of the verify read period RD, a bit line pre-charge period can be included in which the voltage level of all bit lines is pre-charged to the same voltage level (e.g., a power supply voltage VDD level).

[0095] At a completion time point tf of the verify read period RD (i.e., a read recovery time point tf), an off voltage (e.g., a ground voltage VSS) can be applied to the selected first ground select line GIDL_GSL, the selected second ground select line GSL, the selected first string select line GIDL_SSL, and the selected second string select line SSL to cause the selected first ground select line GIDL_GSL, the selected second ground select line GSL, the selected first string select line GIDL_SSL, and the selected second string select line SSL to recover to the ground voltage VSS.

[0096] For example, the second channel pre-charge period GIDL-USIP is not needed in the first programming loop LOOP(1) to the N-1th programming loop LOOP(N-1). Because the voltage level of the programming voltage VPGM in the first programming loop LOOP(1) to the N-1th programming loop LOOP(N-1) is low, programming disturbance does not occur in the first programming loop LOOP(1) to the N-1th programming loop LOOP(N-1).

[0097] Figure 6 The operation periods included in the Nth programming loop LOOP(N) among the plurality of programming loops are shown. The timing diagrams of the Figure 7A In contrast, the timing diagram from the second channel pre-charge period GIDL-USIP to the bit line set period PBLS is different, while the timing diagrams of the remaining periods are the same. In the following, the differences from Figure 7B will be described.

[0098] Referring to Figure 7A , Figure 7A and Figure 5 , the Nth programming loop LOOP(N) can include a program period PROGRAM and a verify period VERIFY, in which a program voltage VPGM is applied to the selected word line WLs to program the selected memory cell in the program period PROGRAM, and a verify read voltage VRD is applied to the selected word line WLs to verify whether the programming is successful in the verify period VERIFY. The program period PROGRAM can include a second channel pre-charge period GIDL-USIP, a bit line set period PBLS, a string select line set period PSSLS, a program execution period PEXE, and a program recovery period PRVC. The verify period VERIFY can include a verify read period RD and a read recovery period RRCV.

[0099] Before the bit line set period PBLS, the channels of the plurality of cell strings can be initialized or pre-charged (USIP) during the second channel pre-charge period GIDL-USIP. A first pre-charge voltage V GIDL BL and a second pre-charge voltage V GIDL CSLBoth the first pre-charge voltage V GIDL BL and the second pre-charge voltage V GIDL CSL can be set to a voltage level significantly higher than the power supply voltage VDD.

[0100] For USIP on the bit line BL side, the first pre-charge voltage V GIDL BL can be applied to the bit line BL, the first negative voltage V GIDL SSL or ground voltage VSS can be applied to the first string select line GIDL_SSL, and the ground voltage VSS can be applied to the second string select line SSL. The first negative voltage V GIDL SSL can be set to a voltage level lower than the ground voltage VSS. A high voltage (the first pre-charge voltage V GIDL BL ) is applied to the drain of the first string select transistor GIDL_SST (i.e., the bit line BL), while a low voltage (the first negative voltage V GIDL SSL or ground voltage VSS) is applied to its gate. Such a large gate-drain voltage difference causes a GIDL current on the drain side of the first string select transistor GIDL_SST. The GIDL current can include electron-hole pairs, where the electrons are swept to the bit line and the holes migrate to the channel to charge the channel. At this time, 0V is applied to all the word lines WLs and WLu. When the storage cell on the bit line BL side has been programmed, the threshold voltage Vth of the programmed storage cell can be, for example, about 1 to 3V, and the channel potential can be negatively boosted to 0V or less. The large gate-drain voltage difference of the first string select transistor GIDL_SST increases the GIDL current and causes the generation of electron-hole pairs to help the generated holes to charge the channel. Thus, the channels of the plurality of cell strings can be initialized using the GIDL phenomenon in which a current is caused by the first string select transistor GIDL_SST and the second string select transistor SST.

[0101] For USIP on the source line CSL side, the second pre-charge voltage V GIDL CSL can be applied to the source line CSL, the second negative voltage V GIDL GSL or ground voltage VSS can be applied to the first ground select line GIDL_GSL, and the ground voltage VSS as an off voltage can be applied to the second ground select line GSL. The second negative voltage V GIDL GSL can be set to a voltage level lower than the ground voltage VSS. A high voltage (the second pre-charge voltage V GIDL CSL ) is applied to the drain of the first ground select transistor GIDL_GST (i.e., the source line CSL), while a low voltage (the second negative voltage V GIDL GSLor a ground voltage VSS). This large gate-drain voltage difference can cause a GIDL current at the drain side of the first ground selection transistor GIDL_GST. The large gate-drain voltage difference of the first ground selection transistor GIDL_GST increases the GIDL current and causes generation of electron-hole pairs to help charge the channel with the generated holes. Thus, the channels of the plurality of cell strings can be initialized according to a GIDL phenomenon in which a current is caused by the first ground selection transistor GIDL_GST and the second ground selection transistor GST.

[0102] At a start time point Ta of the bit line setting period PBLS and the string selection line setting period PSSLS, a program inhibit voltage VINH or a program enable voltage VPER can be applied to the bit line BL according to the value of the write data. The program inhibit voltage VINH can be at a power supply voltage VDD level, and the program enable voltage VPER can be at a ground voltage VSS level. An on voltage VSSL1 equal to or higher than a threshold voltage Vth of each of the first string selection transistor GIDL_SST and the second string selection transistor SST can be applied to the selected first string selection line GIDL_SSL and the selected second string selection line SSL, and an off voltage (i.e., a ground voltage VSS) can be applied to the unselected first string selection line GIDL_SSL and the unselected second string selection line SSL.

[0103] The ground voltage VSS can be applied to the first ground selection line GIDL_GSL and the second ground selection line GSL, and a third precharge voltage VPC can be applied to the source line CSL. The third precharge voltage VPC level can be set to be lower than the second precharge voltage V GIDL CSL level, lower than the power supply voltage VDD level and higher than the ground voltage VSS level.

[0104] At a completion time point Tb of the bit line setting period PBLS, the on voltage VSSL1 of the selected first string selection line GIDL_SSL and the selected second string selection line SSL can be maintained, and the off voltage of the unselected first string selection line GIDL_SSL and the unselected second string selection line SSL can be maintained.

[0105] Thereafter, the operations from the program execution period PEXE to the verify read period RD can be performed in the same manner as Figure 6

[0106] Figure 7B and Figure 7A are diagrams showing operation periods included in a program cycle of a memory device according to an example embodiment.

[0107] Referring to Figure 8A , in the Nth program cycle LOOP(N), as​Figure 8B The program period PROGRAM can include a second channel pre-charge period GIDL-USIP, a bit line set period PBLS, a string select line set period PSSLS, a program execution period PEXE, and a program recovery period PRVC, and the verify period VERIFY can include a verify read period RD and a read recovery period RRCV. The bit line set period PBLS and the string select line set period PSSLS can be simultaneously performed in the program period PROGRAM.

[0108] Referring to Figure 8A In the Nth program loop LOOP(N), the second channel pre-charge period GIDL-USIP operation and the bit line set period PBLS operation can be simultaneously performed in the program period PROGRAM. After the overlapping second channel pre-charge period GIDL-USIP and bit line set period PBLS, the program period PROGRAM can include the string select line set period PSSLS, the program execution period PEXE, and the program recovery period PRVC, and the verify period VERIFY can include the verify read period RD and the read recovery period RRCV.

[0109] Referring to Figure 7B A detailed description will be given of various program bias conditions for performing a channel pre-charge operation on a cell string, regardless of a storage cell programmed in a program method of a memory device according to an example embodiment of the present inventive concept.

[0110] Figure 8B is a timing diagram illustrating bias conditions of a second channel pre-charge period GIDL-USIP, a bit line set period PBLS, and a string select line set period PSSLS included in a program loop of a memory device according to an example embodiment. Hereinafter, a subscript attached to a reference numeral (e.g., 1 in Ta1 and 2 in Ta2) is used to distinguish a plurality of times having the same function. For convenience of explanation, a channel pre-charge operation performed on a bit line BL side according to a GIDL phenomenon caused by a first string select transistor GIDL_SST is referred to as a first pre-charge operation "USIP1", a channel pre-charge operation performed on a source line CSL side according to a GIDL phenomenon caused by a first ground select transistor GIDL_GST is referred to as a second pre-charge operation "USIP2", a channel pre-charge operation performed on the source line CSL side through the first ground select transistor GIDL_GST and a second ground select transistor GST is referred to as a third pre-charge operation "USIP3", and a channel pre-charge operation performed on the bit line BL side through the first string select transistor GIDL_SST and a second string select transistor SST is referred to as a fourth pre-charge operation "USIP4".

[0111] In conjunction with Figures 9-16 andFigures 9-16 Referring to Figure 7B The second channel pre-charge period GIDL-USIP and the bit line set period PBLS overlap in the program cycle PROGRAM, followed by the string select line set period PSSLS.

[0112] At the start time point Tal of the second channel pre-charge period GIDL-USIP and the bit line set period PBLS, the bit line voltage V BL may be applied to the bit line BL, the bit line voltage V BL having the power supply voltage VDD level as the program inhibit voltage level can be applied to the program inhibit bit line, and the ground voltage VSS as the program enable voltage level can be applied to the program enable bit line.

[0113] During the second channel pre-charge period GIDL-USIP and the bit line set period PBLS, the on voltage VSSL1 can be applied to the selected first string select line GIDL_SSL and the selected second string select line SSL, and the ground voltage VSS as the off voltage can be applied to the unselected first string select line GIDL_SSL and the unselected second string select line SSL. The second pre-charge voltage V GIDL CSL may be applied to the first ground select line GIDL_GSL, the ground voltage VSS can be applied to the second ground select line GSL, and the USIP2 can be performed on the channels of the plurality of cell strings from the source line CSL side according to the GIDL phenomenon occurring in the first ground select transistor GIDL_GST. GIDL GSL

[0114] At the completion time point Tb1 of the second channel pre-charge period GIDL-USIP and the bit line set period PBLS (i.e., the start time point Tb1 of the string select line set period PSSLS), the bit line voltage V BL having the power supply voltage VDD level of the program inhibit bit line, the bit line voltage V BL having the ground voltage VSS level of the program enable bit line, and the on voltage VSSL1 of the selected first string select line GIDL_SSL and the selected second string select line SSL can be maintained, and the off voltage of the unselected first string select line GIDL_SSL and the unselected second string select line SSL can be maintained. The ground voltage VSS can be applied to the first ground select line GIDL_GSL, the ground voltage VSS of the second ground select line GSL can be maintained, and the third pre-charge voltage VPC can be applied to the source line CSL.

[0115] In Figure 8B ​USIP2 is performed on the source line CSL side under the condition that the bit line BL is fixed to the power supply voltage VDD level of the program inhibit bit line or the ground voltage VSS level of the program enable bit line, that is, under the 1-step bit line voltage condition. For example, a channel precharge operation can be performed on the cell string regardless of the programmed memory cell.

[0116] In conjunction with Figure 9 and Figure 9 Referring to Figure 7B , the second channel precharge period GIDL-USIP and the bit line setting period PBLS overlap in the programming cycle PROGRAM, followed by the string selection line setting period PSSLS.

[0117] At the start time point Ta2 of the second channel precharge period GIDL-USIP and the bit line setting period PBLS, a first precharge voltage V GIDL BL higher than the power supply voltage VDD can be applied to the program inhibit bit line, and the ground voltage VSS as the program enable voltage level can be applied to the program enable bit line.

[0118] During the second channel precharge period GIDL-USIP and the bit line setting period PBLS, a first negative voltage V GIDL SSL or the ground voltage VSS can be applied to the selected first string selection line GIDL_SSL, and the ground voltage VSS as the off voltage can be applied to the selected second string selection line SSL. A second precharge voltage V GIDL CSL can be applied to the source line CSL, a second negative voltage V GIDL GSL or the ground voltage VSS can be applied to the first ground selection line GIDL_GSL, and the ground voltage VSS can be applied to the second ground selection line GSL. The channel precharge operation of the plurality of cell strings can be USIP1 from the bit line BL side according to the GIDL phenomenon occurring in the first string selection transistor GIDL_SST, or USIP2 from the source line CSL side according to the GIDL phenomenon occurring in the first ground selection transistor GIDL_GST.

[0119] At the completion time point Tb2 of the second channel precharge period GIDL-USIP and the bit line setting period PBLS, that is, the start time point Tb2 of the string selection line setting period PSSLS, the program inhibit bit line can be switched from the first precharge voltage V GIDL BLThe level of the bit line BL changes to the power supply voltage VDD level, and the ground voltage VSS level of the program enable bit line can be maintained. The on voltage VSSL1 can be applied to the selected first string selection line GIDL_SSL, and the on voltage VSSL1 can be applied to the selected second string selection line SSL. The ground voltage VSS can be applied to the unselected first string selection line GIDL_SSL, and the ground voltage VSS of the unselected second string selection line SSL can be maintained. The ground voltage VSS can be applied to the first ground selection line GIDL_GSL, the ground voltage VSS of the second ground selection line GSL can be maintained, and the third pre-charge voltage VPC can be applied to the source line CSL.

[0120] In the programming cycle of Figure 8B , the voltage of the bit line BL changes at the start point Tb2 of the string selection line setting period PSSLS. In the bit line BL, the ground voltage VSS level of the program enable bit line is maintained, and the program inhibit bit line changes from the first pre-charge voltage V GIDL BL DD level. The time point at which the voltage of the bit line BL changes can vary depending on the number of programming cycles and / or the region of the selected word line. The time point at which the on voltage VSSL1 is applied to the selected first string selection line GIDL_SSL and the selected second string selection line SSL can also vary depending on the time point at which the voltage of the bit line BL changes. According to an embodiment, during the string selection line setting period PSSLS, the time point at which the voltage of the bit line BL changes can be set to be different from the time point at which the voltage of the source line CSL changes, to prevent conduction between the bit line BL and the source line CSL during the USIP2 operation of the source line CSL.

[0121] In the programming cycle of Figure 10 , the voltage of the bit line BL is the first pre-charge voltage V GIDL BL DD level or the ground voltage VSS level of the program enable bit line (i.e., the 1-step bit line voltage condition), USIP1 and USIP2 are performed in both directions of the bit line BL and the source line CSL. For example, a channel pre-charge operation can be performed on the cell string regardless of the programmed memory cell.

[0122] In conjunction with Figure 10 and Figure 10 Referring to Figure 7B , the bit line setting period PBLS follows the second channel pre-charge period GIDL-USIP in the programming cycle PROGRAM.

[0123] At the start time Tu3 of the second channel pre-charge period GIDL-USIP, the first pre-charge voltage V GIDL BL DD higher than the power supply voltage VDD can be applied to the bit line BL.

[0124] During the second channel pre-charge period GIDL-USIP, a first negative voltage V can be applied to the first string select line GIDL_SSL. GIDL SSL Alternatively, a ground voltage VSS can be applied, and a ground voltage VSS as a turn-off voltage can be applied to the second string select line SSL. A second pre-charge voltage V can be applied to the source line CSL. GIDL CSL A second negative voltage V can be applied to the first ground selection line GIDL_GSL. GIDL GSL Alternatively, a ground voltage VSS can be applied, and a ground voltage VSS can be applied to the second ground selection line GSL. The channel precharge operation of multiple cell strings can be USIP1 from the bit line BL side based on the GIDL phenomenon occurring in the first string selection transistor GIDL_SST, or USIP2 from the source line CSL side based on the GIDL phenomenon occurring in the first ground selection transistor GIDL_GST.

[0125] At the completion time Ta3 of the second channel precharge period GIDL-USIP (i.e., the start time Ta3 of the bit line setup period PBLS and the string select line setup period PSSLS), in bit line BL, a power supply voltage VDD can be applied to the programming disable bit line, and a ground voltage VSS can be applied to the programming enable bit line. An on-state voltage VSSL1 can be applied to the selected first string select line GIDL_SSL and the selected second string select line SSL. A ground voltage VSS can be applied to the unselected first string select line GIDL_SSL, and the ground voltage VSS of the unselected second string select line SSL can be maintained. A ground voltage VSS can be applied to the first ground select line GIDL_GSL, the ground voltage VSS of the second ground select line GSL can be maintained, and a third precharge voltage VPC can be applied to the source line CSL.

[0126] exist Figure 8A In the programming loop, the programming disable bit line is activated from the first precharge voltage V. GIDL BL The level changes to the supply voltage VDD level and programming allows the bit line to switch from the first precharge voltage VDD. GIDL BL Under the condition that the voltage level changes to ground voltage VSS (i.e., the 2-step bit line voltage condition), USIP1 and USIP2 are performed in both directions of the bit line BL and the source line CSL. For example, channel precharge operations can be performed on the cell string regardless of the memory cell being programmed.

[0127] Combination Figure 11 and Figure 11 Reference Figure 7B In the programming loop PROGRAM, the second channel precharge period GIDL-USIP and the bit line setup period PBLS overlap, followed by the serial select line setup period PSSLS.

[0128] At the start time Ta4 of the second channel precharge period GIDL-USIP and the bit line setup period PBLS, in the bit line BL, a first precharge voltage V higher than the supply voltage VDD can be applied to the programmable disable bit line. GIDL BL Furthermore, a ground voltage VSS, which serves as the programming enable voltage level, can be applied to the programming enable bit line.

[0129] During the second channel precharge period GIDL-USIP and the bit line setup period PBLS, a first negative voltage V can be applied to the selected first string select line GIDL_SSL. GIDL SSL Alternatively, a ground voltage VSS can be applied, and a ground voltage VSS as a turn-off voltage can be applied to a selected second string select line SSL. A word line voltage V with a power supply voltage VDD level can be applied to one or more word lines WLps of the programmed memory cell within the memory cell. WL The power supply voltage VDD level can be supplied to one or more word lines WLps of the programmed memory cell through USIP1 on the bit line BL side and USIP3 on the source line CSL side to prevent conduction between the bit line BL and the source line CSL.

[0130] A word line voltage V with a supply voltage level VDD is applied. WL The location and number of one or more word lines (WLps) of the programmed memory cell may vary. Taking into account the gate length of the memory cells in the cell string, a word line voltage V is applied to the programmed memory cell. WL The memory cell may change. For example, as the gate length of the programmed memory cell decreases, the bit line BL and source line CSL may conduct to each other due to short-channel effects, and therefore this can be addressed by changing the applied word line voltage V. WL The location and number of one or more word lines (WLps) of the programmed memory cell are used to prevent conduction.

[0131] During the second channel precharge period GIDL-USIP and the bit line setup period PBLS, a fourth precharge voltage VCSL can be applied to the source line CSL, and an on-state voltage VGSL can be applied to the first ground select line GIDL_GSL and the second ground select line GSL. The channel precharge operation of multiple cell strings can be USIP1 from the bit line BL side based on the GIDL phenomenon occurring in the first string select transistor GIDL_SST, or USIP3 from the source line CSL side through the first ground select transistor GIDL_GST and the second ground select transistor GST.

[0132] At the completion time Tb4 of the second channel precharge period GIDL-USIP and the bit line setup period PBLS (i.e., the start time Tb4 of the serial select line setup period PSSLS), programming prevents the bit line from being activated from the first precharge voltage V. GIDL BL The voltage level changes to the supply voltage VDD level, and the ground voltage VSS level of the programming enable bit line can be maintained. An on-state voltage VSSL1 can be applied to the selected first select line GIDL_SSL and the selected second select line SSL. A ground voltage VSS can be applied to the unselected first select line GIDL_SSL, and the ground voltage VSS of the unselected second select line SSL can be maintained. A ground voltage VSS can be applied to one or more word lines WLps of the programmed memory cell. A ground voltage VSS as a turn-off voltage can be applied to the first ground select line GIDL_GSL and the second ground select line GSL, and a third precharge voltage VPC can be applied to the source line CSL.

[0133] exist Figure 8B During the programming loop, the voltage of bit line BL changes at the start time Tb4 of the serial select line setting period PSSLS. In bit line BL, the ground voltage VSS level for programming-enabled bit lines is maintained, while the bit line for programming-disable bit lines is maintained at the first pre-charge voltage V. GIDL BL The voltage level changes to the supply voltage VDD level. The timing of the voltage change on bit line BL can vary depending on the number of programming cycles and / or the region of the selected word line. The timing of applying the on-state voltage VSSL1 to the selected first string select line GIDL_SSL and the selected second string select line SSL can also vary depending on the timing of the voltage change on bit line BL. According to an embodiment, during the string select line setting period PSSLS, the timing of the voltage change on bit line BL can be set to be different from the timing of the voltage change on source line CSL to prevent conduction between bit line BL and source line CSL during the USIP3 operation of source line CSL.

[0134] exist Figure 12 In the programming loop, the bit line BL voltage has a pre-charge voltage V. GIDL BL Under the condition (i.e., the 1-step bit line voltage condition), USIP1 and the third precharge are performed in both directions of the bit line BL and the source line CSL. For example, channel precharge operations can be performed on the cell string regardless of the programmed memory cell.

[0135] Combination Figure 12 and Figure 12 Reference Figure 7B In the programming loop PROGRAM, the bit line setup period PBLS follows the second channel precharge period GIDL-USIP.

[0136] At the start time Tu5 of the second channel pre-charge period GIDL-USIP, a first pre-charge voltage V higher than the supply voltage VDD can be applied to the bit line BL. GIDL BL .

[0137] During the second channel pre-charge period GIDL-USIP, a first negative voltage V can be applied to the first string select line GIDL_SSL. GIDL SSL Alternatively, a ground voltage VSS can be applied, and a ground voltage VSS as a turn-off voltage can be applied to the second string select line SSL. A word line voltage V with a power supply voltage VDD level can be applied to one or more word lines WLps of the programmed memory cell within the memory cell. WL A word line voltage V with a supply voltage VDD level was applied. WL The location and number of one or more word lines (WLps) of the programmed memory cell can vary.

[0138] During the second channel precharge period GIDL-USIP, a fourth precharge voltage VCSL can be applied to the source line CSL, and a turn-on voltage VGSL can be applied to the first ground select line GIDL_GSL and the second ground select line GSL. The channel precharge operation of multiple cell strings can be USIP1 from the bit line BL side based on the GIDL phenomenon occurring in the first string select transistor GIDL_SST, or USIP3 from the source line CSL side through the first ground select transistor GIDL_GST and the second ground select transistor GST.

[0139] At the completion time Ta5 of the second channel precharge period GIDL-USIP (i.e., the start time Ta5 of the bit line setup period PBLS and the string select line setup period PSSLS), in the bit line BL, a power supply voltage VDD can be applied to the programming disable bit line, and a ground voltage VSS can be applied to the programming enable bit line. An on-state voltage VSSL1 can be applied to the selected first string select line GIDL_SSL and the selected second string select line SSL. A ground voltage VSS can be applied to the unselected first string select line GIDL_SSL, and the ground voltage VSS of the unselected second string select line SSL can be maintained. A ground voltage VSS can be applied to one or more word lines WLps of the programmed memory cell. A ground voltage VSS as a turn-off voltage can be applied to the first ground select line GIDL_GSL and the second ground select line GSL, and a third precharge voltage VPC can be applied to the source line CSL.

[0140] exist Figure 8A In the programming loop, the programming disable bit line is activated from the first precharge voltage V. GIDL BLThe level changes to the supply voltage VDD level and programming allows the bit line to switch from the first precharge voltage VDD. GIDL BL Under the condition that the voltage level changes to ground voltage VSS (i.e., the 2-step bit line voltage condition), USIP1 and USIP3 are performed in both directions of the bit line BL and the source line CSL. For example, channel precharge operations can be performed on the cell string regardless of the memory cell being programmed.

[0141] Combination Figure 13 and Figure 13 Reference Figure 7B In the programming loop PROGRAM, the second channel precharge period GIDL-USIP overlaps with the bit line setup period PBLS until the intermediate time point Ta_b (i.e., the start time point of the string select line setup period PSSLS).

[0142] At the start time Ta6 of the second channel pre-charge period GIDL-USIP and the bit line setup period PBLS, the bit line voltage V can be applied to the bit line BL. BL A bit line voltage V, having a power supply voltage VDD level as the programming disable voltage level, can be applied to the programming disable bit line. BL Furthermore, a ground voltage VSS, which serves as the programming enable voltage level, can be applied to the programming enable bit line.

[0143] At the start time Ta6 of the second channel precharge period GIDL-USIP and the bit line setup period PBLS, an on-state voltage VSSL1 can be applied to the first string select line GIDL_SSL and the second string select line SSL. A word line voltage V with a power supply voltage VDD level can be applied to one or more word lines WLps of the programmed memory cell within the memory cell. WL A word line voltage V with a supply voltage VDD level was applied. WL The location and number of one or more word lines (WLps) of the programmed memory cell can be varied. A second precharge voltage (V) can be applied to the source line (CSL). GIDL CSL A second negative voltage V can be applied to the first ground selection line GIDL_GSL. GIDL GSL Alternatively, a ground voltage VSS can be applied to the second ground select line GSL. The channel precharge operation of multiple cell strings can be USIP4 from the bit line BL side via the first string select transistor GIDL_SST and the second string select transistor SST, or it can be USIP2 from the source line CSL side based on the GIDL phenomenon that occurs in the first ground select transistor GIDL_GST.

[0144] At the midpoint Ta_b between the second channel precharge period GIDL-USIP and the serial select line setting period PSSLS, the on-state voltage VSSL1 of the selected first serial select line GIDL_SSL and the selected second serial select line SSL can be maintained, and a ground voltage VSS can be applied to the unselected first serial select line GIDL_SSL and the unselected second serial select line SSL. A ground voltage VSS can be applied to one or more word lines WLps of the programmed memory cell. A ground voltage VSS can be applied to the first ground select line GIDL_GSL, the ground voltage VSS of the second ground select line GSL can be maintained, and a third precharge voltage VPC can be applied to the source line CSL.

[0145] exist Figure 8B During the programming loop, USIP4 and USIP2 are executed in both directions of the bit line BL and the source line CSL, provided that the bit line BL is fixed to the power supply voltage VDD level of the programming disabled bit line or the ground voltage VSS level of the programming enabled bit line (i.e., the 1-step bit line voltage condition). For example, channel precharge operations can be performed on the cell string regardless of the memory cell being programmed.

[0146] Combination Figure 14 and Figure 14 Reference Figure 7B In the programming loop PROGRAM, the bit line setup period PBLS follows the second channel precharge period GIDL-USIP.

[0147] At the start time Tu7 of the second channel pre-charge period GIDL-USIP, the power supply voltage VDD can be applied to the bit line BL.

[0148] During the second channel precharge period GIDL-USIP, an on-state voltage VSSL1 can be applied to the first select line GIDL_SSL and the second select line SSL. A word line voltage V with a power supply voltage VDD level can be applied to one or more word lines WLps of the programmed memory cell within the memory cell. WL A word line voltage V with a supply voltage VDD level was applied. WL The location and number of one or more word lines (WLps) of the programmed memory cell can be varied. A second precharge voltage (V) can be applied to the source line (CSL). GIDL CSL A second negative voltage V can be applied to the first ground selection line GIDL_GSL. GIDL GSLAlternatively, a ground voltage VSS can be applied to the second ground select line GSL. The channel precharge operation of multiple cell strings can be USIP4 from the bit line BL side via the first string select transistor GIDL_SST and the second string select transistor SST, or it can be USIP2 from the source line CSL side based on the GIDL phenomenon that occurs in the first ground select transistor GIDL_GST.

[0149] At the completion time Ta7 of the second channel precharge period GIDL-USIP (i.e., the start time Ta7 of the bit line setup period PBLS and the string select line setup period PSSLS), in the bit line BL, a power supply voltage VDD can be applied to the programming disable bit line, and a ground voltage VSS can be applied to the programming enable bit line. The on-state voltage VSSL1 of the selected first string select line GIDL_SSL and the selected second string select line SSL can be maintained, and a ground voltage VSS can be applied to the unselected first string select line GIDL_SSL and the unselected second string select line SSL. A ground voltage VSS can be applied to one or more word lines WLps of the programmed memory cell. A ground voltage VSS can be applied to the first ground select line GIDL_GSL, the ground voltage VSS of the second ground select line GSL can be maintained, and a third precharge voltage VPC can be applied to the source line CSL.

[0150] exist Figure 8A In the programming loop, USIP4 and USIP2 are executed in both directions of the bit line BL and the source line CSL under the conditions that the bit line is programmed to disable the bit line from maintaining the power supply voltage VDD level and to allow the bit line to change from the power supply voltage VDD level to the ground voltage VSS (i.e., the 2-step bit line voltage condition). For example, channel precharge operation can be performed on the cell string regardless of the memory cell being programmed.

[0151] Combination Figure 15 and Figure 15 Reference Figure 7B In the programming loop PROGRAM, the bit line setup period PBLS follows the second channel precharge period GIDL-USIP.

[0152] At the start time Tu8 of the second channel pre-charge period GIDL-USIP, a first pre-charge voltage V higher than the supply voltage VDD can be applied to the bit line BL. GIDL BL .

[0153] During the second channel pre-charge period GIDL-USIP, a first negative voltage V can be applied to the first string select line GIDL_SSL. GIDL SSLAlternatively, a ground voltage VSS can be applied, and a ground voltage VSS as a turn-off voltage can be applied to the second string select line SSL. A third pre-charge voltage VPC can be applied to the source line CSL. The level of the third pre-charge voltage VPC can be set lower than the second pre-charge voltage V. GIDL CSL A ground voltage VSS can be applied to the first ground select line GIDL_GSL, and a ground voltage VSS can be applied to the second ground select line GSL. The channel precharge operation of multiple cell strings can be USIP1 from the bit line BL side based on the GIDL phenomenon that occurs in the first string select transistor GIDL_SST.

[0154] At the completion time Ta8 of the second channel precharge period GIDL-USIP (i.e., the start time Ta8 of the bit line setup period PBLS and the string select line setup period PSSLS), in bit line BL, a power supply voltage VDD can be applied to the programmable disable bit line, and a ground voltage VSS can be applied to the programmable enable bit line. An on-state voltage VSSL1 can be applied to the selected first string select line GIDL_SSL and the selected second string select line SSL. A ground voltage VSS can be applied to the unselected first string select line GIDL_SSL, and the ground voltage VSS of the unselected second string select line SSL can be maintained. The ground voltage VSS of the first ground select line GIDL_GSL and the second ground select line GSL can be maintained, and the third precharge voltage VPC of the source line CSL can be maintained.

[0155] exist Figure 8A In the programming loop, the programming disable bit line is activated from the first precharge voltage V. GIDL BL The level changes to the supply voltage VDD level and programming allows the bit line to switch from the first precharge voltage VDD. GIDL BL Under the condition that the voltage level changes to ground voltage VSS (i.e., the 2-step bit line voltage condition), USIP1 is executed in the direction of bit line BL. For example, regardless of the memory cell being programmed, a channel precharge operation can be performed on the cell string.

[0156] Figure 16 This is a flowchart illustrating a programming method for a storage device according to an example embodiment.

[0157] Reference Figure 16 In the programming method for the memory device, a first precharge operation USIP1 and a second precharge operation USIP2 can be executed simultaneously, followed by the programming operation PROGRAM. In the first precharge operation USIP1, the first string select transistor GIDL_SST and the second string select transistor SST are used to apply the first precharge voltage V to bit line BL. GIDL BL The channels of multiple cell strings are pre-charged (S1701). The first pre-charge voltage V GIDL BLThe voltage level is higher than the supply voltage VDD. Based on the GIDL phenomenon that occurs in the first string select transistor GIDL_SST, the channels of multiple cell strings can be initialized on the bit line BL side.

[0158] In the first precharge operation USIP1, the first precharge of multiple cell strings can be performed during the second channel precharge period GIDL-USIP or the bit line setup period PBLS under the following bias conditions: In the bit line BL, a first precharge voltage V is applied to the programming disable bit line. GIDL BL Apply a programming enable voltage VPER to the programming enable bit line and apply a first negative voltage V to the first string select line GIDL_SSL. GIDL SSL Or ground voltage VSS, and apply ground voltage VSS to the second string select line SSL ( Figure 17 and Figure 17 ).

[0159] In the first precharge operation USIP1, the first precharge of multiple cell strings can be performed during the second channel precharge period GIDL-USIP or the bit line setup period PBLS under the following bias conditions: a first precharge voltage V is applied to the bit line BL. GIDL BL Apply a second negative voltage V to the first ground selection line GIDL_GSL GIDL GSL Or ground voltage VSS, and apply ground voltage VSS to the second ground selection line GSL ( Figure 10 , Figure 12 and Figure 11 ).

[0160] In the second precharge operation USIP2, a second precharge of multiple cell strings can be performed during the second channel precharge period GIDL-USIP or the bit line setup period PBLS under the following bias conditions: In the bit line BL, a programming disable voltage VINH is applied to the programming disable bit line, a programming enable voltage VPER is applied to the programming enable bit line, and an on-state voltage VSSL1 is applied to the first string select line GIDL_SSL and the second string select line SSL. Figure 13 ).

[0161] In the second precharge operation USIP2, a second precharge of multiple cell strings can be performed during the second channel precharge period GIDL-USIP or the bit line setup period PBLS under the following bias conditions: a programming disable voltage VINH level is applied to the bit line BL, and an on-state voltage VSSL1 is applied to the first string select line GIDL_SSL and the second string select line SSL. Figure 16 ).

[0162] In the second precharge operation USIP2, the second precharge voltage V of the source line CSL is applied through the first ground selection transistor GIDL_GST and the second ground selection transistor GST. GIDL CSL Alternatively, a third pre-charge voltage VPC can be used to perform a second pre-charge on the channels of multiple cell strings (S1702). The second pre-charge voltage VPC... GIDL CSL The voltage level is higher than the supply voltage VDD. The channels of multiple cell strings can be initialized on the source line CSL side based on the GIDL phenomenon occurring in the first ground selection transistor GIDL_GST. Figure 14 , Figure 15 , Figure 9 , Figure 10 and Figure 11 ).

[0163] In the second precharge operation USIP2, the second precharge of multiple cell strings can be performed under the following bias condition: a second precharge voltage V is applied to the source line CSL. GIDL CSL Apply a second negative voltage V to the first ground selection line GIDL_GSL GIDL GSL Or ground voltage VSS, and apply ground voltage VSS to the second ground selection line GSL ( Figure 14 , Figure 15 , Figure 9 , Figure 10 and Figure 11 ).

[0164] In the third precharge operation USIP3, the third precharge of multiple cell strings can be performed under the following bias conditions: a second precharge voltage V is applied to the source line CSL. GIDL CSL And apply a turn-on voltage VGSL to the first ground selection line GIDL_GSL and the second ground selection line GSL. Figure 14 and Figure 15 ).

[0165] In programming operations of PROGRAM, such as Figure 12 As described in the programming execution phase PEXE, memory cells connected to selected word lines WLs in a selected cell string can be programmed under the following bias conditions based on the setting voltage of bit line BL: setting bit line BL to programming disable voltage VINH or programming enable voltage VPER according to the value of the written data; applying programming pass voltage VPASS1 to selected word lines WLs and unselected word lines Wlu; after a certain period of time, applying programming voltage VPGM to selected word lines WLs; applying conduction voltage VSSL1 to selected first string select line GIDL_SSL and selected second string select line SSL; and applying ground voltage VSS to unselected first string select line GIDL_SSL and unselected second string select line SSL.

[0166] Figure 13 This is a diagram illustrating the state of a sub-block within a storage block during programming operations of a storage device according to an example embodiment.

[0167] Reference Figure 7B A memory block BLK can be divided into, for example, two sub-blocks SB1 and SB2. The sub-block division criterion can be an intermediate switching line MSL on the boundary layer BND. The boundary layer BND can correspond to a stop layer for progressively forming the first sub-channel via 1801 and the second sub-channel via 1802 that constitute the cell string NS. Because the cells of the stop layer are not suitable for storing data, the stop layer can be used as the boundary layer BND for forming intermediate switching transistors. One or more gate line layers that are vertically adjacent to each other can be formed on the boundary layer BND, and these gate lines can be referred to as intermediate switching lines MSL.

[0168] The programming order of sub-blocks SB1 and SB2 can be: ① from bit line BL to intermediate switch line MSL, then from intermediate switch line MSL to source line CSL; ② from source line CSL to intermediate switch line MSL, then from intermediate switch line MSL to bit line BL; ③ from intermediate switch line MSL to bit line BL and source line CSL; or ④ from bit line BL and source line CSL to intermediate switch line MSL.

[0169] Reference Figures 18A-18C In the unit string NS, assuming according to Figure 18A The programming sequence programmed the memory cells corresponding to the first sub-block SB1, from the memory cells adjacent to the bit line BL to the memory cells connected to any word line WLp, and programmed all memory cells corresponding to the second sub-block SB2. Some channels corresponding to the programmed memory cells on the bit line BL side of the first sub-block SB1 may be negatively boosted, and due to the high threshold voltage of the programmed memory cells, USIP operation on the cell string NS may not be possible. Additionally, some channels corresponding to the programmed memory cells on the source line CSL side of the second sub-block SB2 may be negatively boosted, and due to the high threshold voltage of the programmed memory cells, USIP operation on the cell string NS may not be possible.

[0170] To address the issue of incomplete channel initialization occurring during programming operations on sub-block cells within a memory block, the programming method disclosed herein can be implemented by simultaneously executing... Figure 18B The first pre-charge operation of USIP1 is the pre-charge operation of the channel on the BL side of the alignment line and through Figure 18AThe second precharge operation, USIP2, precharges the channel on the source line CSL side to initialize the channel of the cell string NS. The first precharge operation, USIP1, on the bit line BL side can be performed on the channel corresponding to any word line WLp of the programmed memory cell that has been supplied with a power supply voltage VDD, thereby preventing conduction between the bit line BL and the source line CSL.

[0171] Reference Figure 17 In the cell string NS, assume that all memory cells corresponding to the second sub-block SB2 are programmed, and that memory cells corresponding to the first sub-block SB1, from those adjacent to the intermediate switch line MSL to those connected to any word line WLp, are also programmed. In this case, it can be achieved by simultaneously executing... Figure 17 The first pre-charge operation of USIP1 is the pre-charge operation of the channel on the BL side of the alignment line and through Figure 18C The second precharge operation, USIP2, precharges the channel on the source line CSL side to initialize the channel of the cell string. USIP2 can be performed on any word line WLp from the source line CSL side to the programmed memory cell, corresponding to a word line WLp with an applied power supply voltage VDD, thereby preventing conduction between the bit line BL and the source line CSL.

[0172] Figure 17 and Figure 17 This is a diagram that conceptually illustrates the relationship between programming operations and read reclaim operations of a storage device according to an example embodiment. Figure 19A Showing no application Figure 19B The programming method of reading and recycling, and Figure 19A The application is shown. Figure 17 The programming method of reading and recycling.

[0173] Reference Figure 19B and Figure 17 The memory controller 110 determines whether an error exists in the data read during a read operation of the storage device 120 (S1901). When an error exists in a storage block including the target area (e.g., the target storage block), error correction is performed using error correction codes (ECC). However, there may be situations where error correction cannot be performed using ECC. In such cases, read recycling can be performed to overcome the impossibility of error correction. Read recycling can be performed based on degradation information. Degradation information can include program / erase (P / E) cycles, erase counts, program counts, read counts, wear level counts, elapsed time, operating temperature, etc.

[0174] The memory controller 110 can copy the convex data corresponding to the target memory block and write the convex data to another memory block (S1902). The memory controller 110 can erase the target memory block (S1903).

[0175] Reference Figure 1 When the memory controller 110 determines an error regarding data read from the target memory block (S2001), the memory controller 110 can copy the ECC-processed data to the corresponding target memory block (S2002). In this case, the storage device 120 can use a reference... Figure 19A , Figure 19B , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figures 9-16 The described programming method for the second-channel precharge interval GIDL-USIP performs copying to the target memory block. For example, the memory controller 110 can copy data to the corresponding target memory block during read reclamation. Therefore, the memory controller 110 can ensure the availability of memory block resources.

[0176] Figure 17 This is a block diagram illustrating a solid-state drive or solid-state hard disk (SSD) 1000 that performs a programming method for an execution storage device according to an example embodiment.

[0177] Reference Figures 18A-18C Figure 20 Figure 20 The SSD 1000 includes multiple non-volatile memory devices 1100 and an SSD controller 1200. The non-volatile memory devices 1100 can be implemented as the aforementioned memory devices 120. The non-volatile memory devices 1100 can perform channel initialization operations on multiple cell strings and can perform programming operations on selected memory cells among the multiple memory cells. The channel initialization operation can perform a first precharge on the bit line side, a second precharge on the source line side, and simultaneously perform both the first and second precharges.

[0178] SSD controller 1200 is connected to non-volatile storage device 1100 via multiple channels CH1 to CH4. SSD controller 1200 includes at least one processor 1210, buffer memory 1220, ECC circuitry 1230, host interface 1250, and non-volatile memory interface 1260. Buffer memory 1220 can temporarily store data required to drive SSD controller 1200. Furthermore, buffer memory 1220 can buffer data to be used for programming operations based on write requests. ECC circuitry 1230 calculates error correction code values ​​for data to be programmed during write operations, corrects data read during read operations based on the error correction code values, and corrects non-volatile storage device 1100 during read-and-reclaim operations.

[0179] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the invention as described in the appended claims.

Claims

1. A programming method for a non-volatile memory device, the non-volatile memory device comprising a plurality of cell strings connected between a plurality of bit lines and a source line, each of the plurality of cell strings comprising a first string select transistor, a second string select transistor, a plurality of memory cells, a second ground select transistor, and a first ground select transistor arranged in series between one of the plurality of bit lines and the source line, the programming method comprising: Initialize the channel for the plurality of unit strings; as well as Perform programming operations on selected memory cells among the plurality of memory cells. The initialization of the channel includes: The first precharge is performed on the channels of the plurality of cell strings using the first precharge voltage applied to the plurality of bit lines through the first string select transistor and the second string select transistor; A second precharge is performed on the channel of the plurality of cell strings using a second precharge voltage applied to the source line through the first ground selection transistor and the second ground selection transistor; A first negative voltage lower than the ground voltage is applied to the first string select line connected to the first string select transistor; The ground voltage is applied to the second string select line connected to the second string select transistor; Apply the ground voltage to the second ground selection line connected to the second ground selection transistor; and A second negative voltage lower than the ground voltage is applied to the first ground selection line connected to the first ground selection transistor. The first pre-charge and the second pre-charge are performed simultaneously.

2. The programming method according to claim 1, further comprising: Before performing the programming operation, the bit line is set by the following operation: A programming disable voltage is applied to one of the programming disable bit lines, which are bit lines used for unselected memory cells among the plurality of memory cells. A programming enable voltage is applied to one of the programming enable bit lines, which is the bit line used for the selected memory cell. Wherein, the programming disable voltage is the power supply voltage applied to the non-volatile memory device, and the programming enable voltage is the ground voltage. Wherein, the power supply voltage is greater than the grounding voltage.

3. The programming method according to claim 2, wherein, The channel is initialized before the bit lines are set, and the programming method further includes: Apply an on-state voltage to a selected first string of select lines of the selected memory cell; and The on-state voltage is applied to the selected second select line of the selected memory cell. Wherein, the conduction voltage is greater than the grounding voltage.

4. The programming method according to claim 3, further comprising: The voltage applied to the first ground selection line is changed from the second negative voltage to the ground voltage; as well as The voltage applied to the source line is changed from the second precharge voltage to a third precharge voltage that is lower than the second precharge voltage.

5. The programming method according to claim 2, wherein, The channel is initialized before the bit lines are set. The initialization of the channel includes: The first precharge voltage is applied to the programming disable bit line and the programming enable bit line, the first precharge voltage being higher than the programming disable voltage; and A second precharge voltage, higher than the power supply voltage applied to the source line, is applied to the source line, and The bit line configuration includes: Change the first precharge voltage to the programming disable voltage and the programming enable voltage; and The programming disable voltage is applied to the programming disable bit line, and the programming enable voltage is applied to the programming enable bit line. Wherein, the power supply voltage is greater than the grounding voltage.

6. The programming method according to claim 5, wherein, The timing of the voltage change of the programmable disable bit line varies according to the number of programming cycles of the selected word line connected to the selected memory cell. At the timing of the voltage change, the voltage applied to the programmable disable bit line changes from the first precharge voltage to the programmable disable voltage.

7. The programming method according to claim 5, further comprising: At the moment when the voltage of the programming disable bit line changes, a conduction voltage is applied to the selected first string select line and the selected second string select line of the selected memory cell. Wherein, the conduction voltage is greater than the grounding voltage.

8. The programming method according to claim 5, further comprising: The voltage applied to the first ground selection line is changed from the second negative voltage to the ground voltage; as well as The voltage applied to the source line is changed from the second pre-charge voltage to a third pre-charge voltage that is lower than the second pre-charge voltage. Specifically, the voltage change time of the source line is set to be different from the voltage change time of the programming disable bit line.

9. The programming method according to claim 2, wherein, The bit line settings are performed after the channel is initialized, and The initialization of the channel includes: Apply a first precharge voltage, higher than the power supply voltage applied to the non-volatile memory device, to the programming disable bit line and the programming enable bit line; and A second pre-charge voltage higher than the power supply voltage is applied to the source line. Wherein, the power supply voltage is greater than the grounding voltage.

10. The programming method according to claim 9, wherein, The bit line configuration includes: The voltage applied to the selected first string of select lines of the selected memory cell is changed from the first negative voltage or the ground voltage to the on-state voltage; The voltage applied to the selected second string select line of the selected memory cell is changed from the ground voltage to the on-state voltage; Change the voltage applied to the first ground selection line from the second negative voltage to the ground voltage; and The voltage applied to the source line is changed from the second pre-charge voltage to a third pre-charge voltage that is lower than the second pre-charge voltage. Wherein, the conduction voltage is greater than the grounding voltage.

11. The programming method according to claim 2, wherein, The bit line settings are performed after the channel is initialized, and The initialization of the channel includes: Apply the first precharge voltage to the programming disable bit line and the programming enable bit line; and A third precharge voltage lower than the second precharge voltage is applied to the source line.

12. The programming method according to claim 11, wherein, The bit line configuration includes: The voltage applied to the selected first string select line of the selected memory cell is changed from the first negative voltage or the ground voltage to the on-state voltage; and The voltage applied to the selected second string select line of the selected memory cell is changed from the ground voltage to the on-state voltage. Wherein, the conduction voltage is greater than the grounding voltage.

13. The programming method according to claim 1, wherein, The first pre-charge voltage and the second pre-charge voltage are higher than the power supply voltage applied to the non-volatile memory device, and Wherein, the power supply voltage is greater than the grounding voltage.

14. A programming method for a non-volatile memory device, the non-volatile memory device comprising a plurality of cell strings connected between a plurality of bit lines and a source line, each of the plurality of cell strings comprising a first string select transistor, a second string select transistor, a plurality of memory cells, a second ground select transistor, and a first ground select transistor arranged in series between one of the plurality of bit lines and the source line, the programming method comprising: Initialize the channel for the plurality of unit strings; as well as Perform programming operations on selected memory cells among the plurality of memory cells. The initialization of the channel includes: Apply a word line voltage having a power supply voltage applied to the nonvolatile memory device to one or more word lines of the programmed memory cells among the plurality of memory cells; A first precharge is performed on the channels of the plurality of cell strings using a first precharge voltage applied to the plurality of bit lines through the first string select transistor and the second string select transistor; and A second precharge is performed on the channel of the plurality of cell strings using a second precharge voltage applied to the source line via the first ground selection transistor and the second ground selection transistor. The first pre-charge and the second pre-charge are performed simultaneously. Wherein, the power supply voltage is greater than the ground voltage, and the first pre-charge voltage and the second pre-charge voltage are greater than the power supply voltage, and The first pre-charge is performed under the following conditions: a first negative voltage lower than the ground voltage is applied to the first string select line connected to the first string select transistor, and the ground voltage is applied to the second string select line connected to the second string select transistor.

15. The programming method according to claim 14, wherein, The position and number of word lines of the programmed memory cell vary based on the length of the initialized channel.

16. A non-volatile storage device, comprising: A memory cell array, the memory cell array comprising multiple cell strings connected between multiple bit lines and source lines, each of the multiple cell strings comprising a first string select transistor, a second string select transistor, multiple memory cells, a second ground select transistor, and a first ground select transistor arranged in series between one of the multiple bit lines and the source line; as well as A control circuit configured to perform channel initialization operations for the plurality of cell strings and programming operations for selected memory cells among the plurality of memory cells. The control circuit is further configured to, during the initialization of the channel: A first precharge is performed on the channels of the plurality of cell strings using a first precharge voltage applied to the plurality of bit lines through the first string select transistor and the second string select transistor; and A second precharge is performed on the channels of the plurality of cell strings simultaneously with the first precharge, using a second precharge voltage applied to the source line via the first ground selection transistor and the second ground selection transistor. Wherein, the first pre-charge voltage and the second pre-charge voltage are greater than the power supply voltage applied to the non-volatile memory device. Wherein, the power supply voltage is greater than the grounding voltage, and The control circuit is further configured to perform the first precharge under the following bias conditions: a first negative voltage lower than the ground voltage is applied to the first string select line connected to the first string select transistor, and the ground voltage is applied to the second string select line connected to the second string select transistor.

17. The non-volatile storage device according to claim 16, wherein, The control circuit is further configured to apply a word line voltage having the power supply voltage to one or more word lines of the programmed memory cells among the plurality of memory cells during the operation of initializing the channel.

18. The non-volatile storage device according to claim 16, wherein, The memory cell array includes multiple memory blocks, each memory block comprising the multiple cell strings formed in a direction perpendicular to the substrate, and The control circuit is further configured to divide the memory block into multiple sub-blocks, perform the first pre-charge on the bit line side of the sub-blocks, and perform the second pre-charge on the source line side of the sub-blocks.

19. The non-volatile storage device according to claim 16, wherein, The memory cell array includes multiple memory blocks, each memory block comprising the multiple cell strings formed in a direction perpendicular to the substrate, and The control circuit is further configured to correct errors in data read from a target storage block among the plurality of storage blocks, and to copy the corrected data to the target storage block.

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