Method for preparing semiconductor structure

Abstract

The present invention relates to a method for preparing a semiconductor structure, comprising: providing a target material layer; forming a first mask layer and a second mask layer on the upper surface of the target material layer, wherein the first mask layer and the second mask layer are sequentially stacked on the target material layer; etching the second mask layer based on the first mask layer to form a second opening pattern, wherein the sidewall of the second opening pattern is an inclined sidewall; etching the target material layer based on the second mask layer and the second opening pattern. In the process of etching the target material layer based on the second mask layer, the inclined sidewall of the second opening pattern will gradually retreat, so that the target material layer under the second mask layer is gradually exposed and etched, so that the etching degree of each part of the target material layer is inconsistent, and the morphology of the target material layer formed by etching under such inconsistency presents a certain inclined angle.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] With the improvement of semiconductor device performance, different morphologies need to be etched in the process of semiconductor device manufacturing. For example, for the formation of a gently sloping microstructure, the existing technology is to increase the polymer content during the etching process, thereby protecting the side wall with a large amount of polymer gas, so that the side wall gradually tilts during etching, and finally forms a gently sloping microstructure.

[0003] However, the inclination angle of the dielectric layer formed by this method is limited, and too much polymer will cause the problem of etching stopping during the etching process. Similarly, too much polymer gas will affect the atmosphere in the etching chamber and increase the PM cycle of the machine, thereby greatly increasing the industrial cost investment. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure in order to solve the above technical problems, which has the advantage of being able to form a gentle slope structure by etching on a target material layer in a mass-produced manner at a low cost.

[0005] A method for preparing a semiconductor structure, comprising:

[0006] providing a target material layer;

[0007] Forming a first mask layer and a second mask layer on the upper surface of the target material layer, wherein the second mask layer is located on the upper surface of the target material layer, the first mask layer is located on the upper surface of the second mask layer, and a first opening pattern is formed in the first mask layer;

[0008] Patterning the second mask layer based on the first mask layer to form a second opening pattern in the second mask layer, wherein the sidewalls of the second opening pattern are inclined sidewalls, and the bottom width of the second opening pattern is smaller than the top width of the second opening pattern;

[0009] The target material layer is etched based on the patterned second mask layer to form a groove in the target material layer.

[0010] Through the above method steps, in the production process, the second mask layer is etched through the first mask layer to form a second opening pattern on the second mask layer. Since the sidewall of the second opening pattern is an inclined sidewall, in the process of etching the target material layer based on the second mask layer, the inclined sidewall of the second opening pattern will gradually retreat, so that the target material layer under the second mask layer is gradually exposed and etched, so that the etching degree of each part of the target material layer is inconsistent. Under this inconsistency, the morphology of the target material layer formed by etching presents a certain inclination angle. By controlling the inclination angle of the inclined sidewall of the second mask layer, the morphology of the target material layer with controllable angle is realized. The process steps are simple and can be completed without special machine support. The cost is low and it is conducive to the needs of industrial mass production. At the same time, this method for preparing a semiconductor structure can meet the needs of a variety of target material layers with gentle slope structure morphology. By changing the inclination of the sidewall of the second opening pattern and the width of the second opening pattern, it can meet the needs of a variety of semiconductor processes and has a wider application prospect.

[0011] In one embodiment, the target material layer is etched based on the second mask layer and the second opening pattern to form a trench, and the bottom width of the second opening pattern formed in the previous step is smaller than the top width of the trench.

[0012] In one embodiment, the second mask layer includes a polysilicon layer.

[0013] In one embodiment, the target material layer includes a dielectric layer; the target material layer is formed on an upper surface of a substrate.

[0014] In one embodiment, the dielectric layer includes at least one type of grown silicon dioxide layer or at least one type of grown silicon nitride layer.

[0015] In one embodiment, the groove at least penetrates the target material layer along the thickness direction.

[0016] In one embodiment, the target material layer is etched using a dry etching process.

[0017] In one embodiment, the thickness of the target material layer is greater than the thickness of the second mask layer.

[0018] In one embodiment, after etching the second mask layer based on the first mask layer to form a second opening pattern and before etching the target material layer based on the patterned second mask layer, the step of removing the first mask layer is further included;

[0019] After etching the target material layer based on the patterned second mask layer, the method further includes removing the second mask layer.

[0020] In one embodiment, the inclination angle of the side wall of the second opening pattern is 40° to 90°;

[0021] The etching gas for the second mask layer includes oxygen and chlorine. The flow rate of the oxygen is adjusted within a range of 5 to 10 sccm, and the flow rate of the chlorine is adjusted within a range of 90 to 140 sccm. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A flow chart showing a method for preparing a semiconductor structure according to an embodiment of the present invention;

[0023] Figure 2 A flow chart showing a method for preparing a semiconductor structure according to another embodiment of the present invention;

[0024] Figure 3 A flowchart showing a method for preparing a semiconductor structure according to another embodiment of the present invention;

[0025] Figure 4 It is a schematic diagram of the cross-sectional structure of a semiconductor structure after a first mask layer is formed in one embodiment of the present invention;

[0026] Figure 5 A schematic diagram of a cross-sectional structure of a semiconductor structure after a second opening pattern is formed in one embodiment of the present invention;

[0027] Figure 6 It is a schematic diagram of the cross-sectional structure of the semiconductor structure after the first mask layer is removed in one embodiment of the present invention;

[0028] Figure 7 It is a schematic diagram of the cross-sectional structure of a semiconductor structure after trenches are formed in one embodiment of the present invention;

[0029] Figure 8 It is a schematic diagram of the cross-sectional structure of the semiconductor structure after the second mask layer is removed in one embodiment of the present invention.

[0030] Reference numerals: 10, target material layer; 101, dielectric layer; 11, first mask layer; 12, second mask layer; 13, second opening pattern; 14, groove; 15, substrate. DETAILED DESCRIPTION

[0031] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0033] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the method or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0034] With the improvement of semiconductor device performance, different morphologies need to be etched in the process of semiconductor device manufacturing. For example, for the formation of a gently sloping microstructure, the existing technology is to increase the polymer content during the etching process, thereby protecting the side wall with a large amount of polymer gas, so that the side wall gradually tilts during etching, and finally forms a gently sloping microstructure.

[0035] However, the inclination angle of the dielectric layer formed by this method is limited, and too much polymer will cause the problem of etching stopping during the etching process. Similarly, too much polymer gas will affect the atmosphere in the etching chamber and increase the PM cycle of the machine, thereby greatly increasing the industrial cost investment.

[0036] In order to be able to etch and form a gentle slope structure on the target material layer 10 at a low cost and in a mass-producible manner, such as Figure 1 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0037] Step S10: providing a target material layer 10;

[0038] Step S20: forming a first mask layer 11 and a second mask layer 12 on the upper surface of the target material layer 10, wherein the second mask layer 12 is located on the upper surface of the target material layer 10, the first mask layer 11 is located on the upper surface of the second mask layer 12, and a first opening pattern is formed in the first mask layer 11, such as Figure 4 As shown;

[0039] Step S30: Patterning the second mask layer 12 based on the first mask layer 11 to form a second opening pattern 13 in the second mask layer 12, wherein the sidewalls of the second opening pattern 13 are inclined sidewalls, and the bottom width of the second opening pattern 13 is smaller than the top width of the second opening pattern 13, such as Figure 5 As shown;

[0040] Step S40: etching the target material layer 10 based on the patterned second mask layer 12 to form a groove 14 in the target material layer 10, such as Figure 7 shown.

[0041] Through the above-mentioned method steps, during the production process, the second mask layer 12 is etched through the first mask layer 11 to form a second opening pattern 13 on the second mask layer 12. Since the sidewalls of the second opening pattern 13 are inclined sidewalls, during the process of etching the target material layer 10 based on the second mask layer 12, the inclined sidewalls of the second opening pattern 13 will gradually retreat, so that the target material layer 10 under the second mask layer 12 is gradually exposed and etched, so that the etching degree of each part of the target material layer 10 is inconsistent. Under this inconsistency, the morphology of the target material layer 10 formed by etching presents a certain tilt angle. By controlling the inclination angle of the inclined side wall of the second mask layer 12, the angle-controllable morphology of the target material layer 10 is achieved. The process steps are simple and can be completed without the support of special machines. The cost is low and it is conducive to the needs of industrial mass production. At the same time, this method for preparing a semiconductor structure can meet the needs of a variety of target material layers 10 with a gentle slope structure. By changing the side wall inclination of the second opening pattern 13 and the aperture size of the second opening pattern 13, it can meet the needs of a variety of semiconductor processes and has a broader application prospect.

[0042] In an optional embodiment, if Figure 6 and Figure 7As shown, the target material layer 10 is etched based on the second mask layer 12 and the second opening pattern 13 to form a groove 14, and the bottom width of the second opening pattern 13 formed in the previous step is smaller than the top width of the groove 14. In the process of etching the target material layer 10 based on the second mask layer 12 and the second opening pattern 13, the inclined sidewall of the second opening pattern 13 will gradually retreat, gradually exposing the target material layer 10 under the second mask layer 12. Therefore, after the etching of the groove 14 is completed, the aperture size of the top of the groove 14 is larger than the size of the bottom width of the second opening pattern 13 in the previous step; that is, in the process of etching the target material layer 10 based on the second opening pattern 13, the aperture size of the second opening pattern 13 is gradually increased. In an optional embodiment, the inclination angle of the sidewall of the second opening pattern 13 is 40° to 90°, and the sidewall angle of the second opening pattern 13 can be precisely controlled at 40° to 90°, thereby realizing the morphology of the target material layer 10 with controllable angle. Furthermore, the inclination angle of the side wall of the second opening pattern 13 can be 40° to 50°, such as 40°, 45° or 50°, but the above values ​​are only examples, and the inclination angle of the side wall of the second opening pattern 13 in the actual production process is not limited to the above data.

[0043] In an optional embodiment, the first mask layer 11 may be a photoresist layer, or a composite structure consisting of a photoresist layer, an anti-reflection layer, and a hard mask layer. When the first mask layer 11 is a photoresist layer, the first mask material layer is evenly distributed on the upper surface of the second mask layer 12 by a spin coating process, and the first mask material layer is patterned after being exposed and developed, thereby forming the first mask layer 11.

[0044] In an optional embodiment, the second mask layer 12 includes a polysilicon layer. Specifically, a polysilicon layer can be formed on the upper surface of the target material layer 10 through a deposition process, and can be a doped polysilicon layer or a poly-polysilicon layer. For etching the second mask layer 12, an inductively coupled plasma reactor can be used, using a gas combination of chlorine (Cl2) and oxygen (O2). During the etching process, the gas flow rate of chlorine is adjusted in the range of 90 to 140 sccm, which can be 90 sccm, 120 sccm or 140 sccm; the gas flow rate of oxygen is adjusted in the range of 5 to 10 sccm, which can be 5 sccm, 7 sccm or 10 sccm; during the etching process, the process pressure in the etching chamber is adjusted in the range of 10 to 20 mT, which can be 10 mT, 15 mT or 20 mT; the upper RF source power is adjusted in the range of 300 to 600 W, which can be 300 W, 450 W or 600 W; the lower RF source power is adjusted in the range of 140 to 200 W, which can be 140 W, 170 W or 200 W. The above data are for reference only, and the data in the actual implementation process are not limited by the above examples.

[0045] In an optional embodiment, the target material layer 10 includes a dielectric layer 101; the target material layer 10 is formed on the upper surface of the substrate 15, and the second mask layer 12 is formed on the upper surface of the dielectric layer 101. The material of the substrate 15 may include semiconductor elements, such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, or a mixed semiconductor structure, such as silicon carbide, indium antimonide, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or other combinations, or silicon on insulator. In addition, the substrate 15 structure may be a multi-layer structure of an epitaxial layer or a mask layer.

[0046] In an optional embodiment, the dielectric layer 101 is formed on the upper surface of the substrate 15, and the dielectric layer 101 includes at least one form of insulating silicon dioxide material grown or at least one form of silicon nitride layer grown. The dielectric layer 101 may include insulating silicon dioxide materials grown in various forms, such as BPSG, PSG, FSG, USG, TEOS, thermally oxidized silicon dioxide, wet oxidized silicon dioxide, or a combination of multi-layer films thereof; or may include silicon nitride layers grown in various forms.

[0047] In an optional embodiment, etching the target material layer 10 based on the second mask layer 12 and the second opening pattern 13 specifically includes: etching the dielectric layer 101 based on the second mask layer 12 and the second opening pattern 13 until the substrate 15 is exposed. The dielectric layer 101 can be etched by a dry etching process, and the etching of the dielectric layer 101 can specifically be carried out by using one of the gas combinations of CF4 / CHF3 / AR, CF4 / CHF3 / AR / O2, C4F8 / O2 / AR, C4F8 / O2 / CO / AR, C4F6 / O2 / AR, C4F6 / O2 / CO / AR, C5F8 / O2 / AR, C5F8 / O2 / CO / AR, etc. The trench 14 formed by etching completely penetrates the dielectric layer 101, and the bottom of the trench 14 exposes the substrate 15. In one optional embodiment, the thickness of the dielectric layer 101 is greater than the thickness of the second mask layer 12.

[0048] In an optional embodiment, after etching the second mask layer 12 based on the first mask layer 11 to form the second opening pattern 13, and before etching the target material layer 10 based on the second mask layer 12 and the second opening pattern 13, step S31 is further included, as shown below:

[0049] Step S10: providing a target material layer 10;

[0050] Step S20: forming a first mask layer 11 and a second mask layer 12 on the upper surface of the target material layer 10, wherein the second mask layer 12 is located on the upper surface of the target material layer 10, the first mask layer 11 is located on the upper surface of the second mask layer 12, and a first opening pattern is formed in the first mask layer 11, such as Figure 4 As shown;

[0051] Step S30: Patterning the second mask layer 12 based on the first mask layer 11 to form a second opening pattern 13 in the second mask layer 12, wherein the sidewalls of the second opening pattern 13 are inclined sidewalls, and the bottom width of the second opening pattern 13 is smaller than the top width of the second opening pattern 13, such as Figure 5 As shown;

[0052] Step S31: removing the first mask layer 11, such as Figure 6 As shown;

[0053] Step S40: etching the target material layer 10 based on the patterned second mask layer 12 to form a groove 14 in the target material layer 10, such as Figure 7 shown.

[0054] Specifically, removing the first mask layer 11 through a wet cleaning process helps to improve the etching accuracy in the subsequent etching process. In other optional embodiments, the first mask layer 11 can also be removed through an ashing process.

[0055] In an optional embodiment, after etching the target material layer 10 based on the second mask layer 12 and the second opening pattern 13, step S50 is further included, as shown below:

[0056] Step S10: providing a target material layer 10;

[0057] Step S20: forming a first mask layer 11 and a second mask layer 12 on the upper surface of the target material layer 10, wherein the second mask layer 12 is located on the upper surface of the target material layer 10, the first mask layer 11 is located on the upper surface of the second mask layer 12, and a first opening pattern is formed in the first mask layer 11, such as Figure 4 As shown;

[0058] Step S30: Patterning the second mask layer 12 based on the first mask layer 11 to form a second opening pattern 13 in the second mask layer 12, wherein the sidewalls of the second opening pattern 13 are inclined sidewalls, and the bottom width of the second opening pattern 13 is smaller than the top width of the second opening pattern 13, such as Figure 5 As shown;

[0059] Step S31: removing the first mask layer 11, such as Figure 6 As shown;

[0060] Step S40: etching the target material layer 10 based on the patterned second mask layer 12 to form a groove 14 in the target material layer 10, such as Figure 7 shown.

[0061] Step S50: removing the second mask layer 12, such as Figure 8 shown.

[0062] Specifically, the second mask layer 12 can be removed by a chemical mechanical masking process, that is, firstly, the surface material of the second mask layer 12 is chemically reacted with the oxidant, catalyst, etc. in the polishing liquid to generate a soft layer that is relatively easy to remove, and then the soft layer is removed under the mechanical action of the abrasive and the polishing pad in the polishing liquid, and the above steps are repeated repeatedly until the second mask layer 12 is removed.

[0063] Through the above technical solution, during the production process, the second mask layer 12 is etched through the first mask layer 11 to form a second opening pattern 13 on the second mask layer 12. Since the sidewalls of the second opening pattern 13 are inclined sidewalls, during the process of etching the target material layer 10 based on the second mask layer 12, the inclined sidewalls of the second opening pattern 13 will gradually retreat, so that the target material layer 10 under the second mask layer 12 is gradually exposed and etched, so that the etching degree of each part of the target material layer 10 is inconsistent. Under such inconsistency, the morphology of the target material layer 10 formed by etching presents a certain tilt angle. By controlling the inclination angle of the inclined side wall of the second mask layer 12, the angle-controllable morphology of the target material layer 10 is achieved. The process steps are simple and can be completed without the support of special machines. The cost is low and it is conducive to the needs of industrial mass production. At the same time, this method for preparing a semiconductor structure can meet the needs of a variety of target material layers 10 with a gentle slope structure. By changing the side wall inclination of the second opening pattern 13 and the aperture size of the second opening pattern 13, it can meet the needs of a variety of semiconductor processes and has a broader application prospect.

[0064] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a target material layer; Forming a first mask layer and a second mask layer on the upper surface of the target material layer, wherein the second mask layer is located on the upper surface of the target material layer, the first mask layer is located on the upper surface of the second mask layer, and a first opening pattern is formed in the first mask layer; Patterning the second mask layer based on the first mask layer to form a second opening pattern in the second mask layer, wherein the sidewalls of the second opening pattern are inclined sidewalls, and the bottom width of the second opening pattern is smaller than the top width of the second opening pattern; etching the target material layer based on the patterned second mask layer to form a groove in the target material layer; etching the target material layer based on the second mask layer and the second opening pattern to form a groove, wherein the bottom width of the second opening pattern formed in the previous step is smaller than the top width of the groove; The second mask layer includes a polysilicon layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The target material layer includes a dielectric layer; the target material layer is formed on the upper surface of the substrate.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The dielectric layer includes at least one type of grown silicon dioxide layer or at least one type of grown silicon nitride layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The groove at least penetrates the target material layer along a thickness direction.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that: The target material layer is etched using a dry etching process.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that: The thickness of the target material layer is greater than the thickness of the second mask layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: After etching the second mask layer based on the first mask layer to form a second opening pattern and before etching the target material layer based on the patterned second mask layer, the method further includes removing the first mask layer; After etching the target material layer based on the patterned second mask layer, the method further includes a step of removing the second mask layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The inclination angle of the side wall of the second opening pattern is 40° to 90°; The etching gas for the second mask layer includes oxygen and chlorine. The flow rate of the oxygen is adjusted within a range of 5 to 10 sccm, and the flow rate of the chlorine is adjusted within a range of 90 to 140 sccm.

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