Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure comprises providing a substrate; forming a dielectric layer on the substrate, the dielectric layer having a first opening and a second opening; forming an initial gate dielectric layer within the first opening and the second opening; forming a first initial work function layer on the surface of the initial gate dielectric layer within the first opening and the second opening; removing the first initial work function layer and a portion of the initial gate dielectric layer within the first opening to form a first gate dielectric layer; forming a second initial work function layer within the first opening and the second opening; and removing the first initial work function layer, the second initial work function layer, and a portion of the initial gate dielectric layer within the second opening to form a second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer are formed separately through different process steps, so that the heights of the first gate dielectric layer and the second gate dielectric layer can be adjusted and controlled separately, thereby ensuring that the heights of the first gate dielectric layer and the second gate dielectric layer formed are consistent, thereby improving the performance of the semiconductor structure formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] MOS (metal-oxide-semiconductor) transistors are one of the most important components in modern integrated circuits. Their basic structure consists of a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, which includes a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and doped source and drain regions located in the semiconductor substrate on both sides of the gate structure. MOS transistors include PMOS and NMOS transistors.

[0003] In order to meet the switching speed requirements of different transistors in integrated circuit design, it is necessary to form transistors with multiple threshold voltages.

[0004] To reduce and adjust the threshold voltages of PMOS and NMOS transistors, corresponding work function layers are formed on the gate dielectric surfaces of these transistors. The work function layers of PMOS transistors are required to have a higher work function, while those of NMOS transistors are required to have a lower work function. The work function layers of PMOS and NMOS transistors are made of different materials to meet the respective work function adjustment requirements.

[0005] However, the performance of the multi-threshold voltage FinFET formed in the prior art still needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed multi-threshold voltage fin field effect transistor.

[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric layer on the substrate, the dielectric layer having a first opening and a second opening; forming an initial gate dielectric layer in the first opening and the second opening, respectively; forming a first initial work function layer on the surface of the initial gate dielectric layer in the first opening and the second opening, respectively; removing the first initial work function layer and a portion of the initial gate dielectric layer located in the first opening to form a first gate dielectric layer, the top surface of the first gate dielectric layer being lower than the top surface of the dielectric layer; forming a second initial work function layer in the first opening and the second opening, respectively, the second initial work function layer being located on the surface of the first gate dielectric layer in the first opening, and the second initial work function layer being located on the surface of the first initial work function layer in the second opening; removing the first initial work function layer, the second initial work function layer and a portion of the initial gate dielectric layer located in the second opening to form a second gate dielectric layer, the top surface of the second gate dielectric being lower than the top surface of the dielectric layer.

[0008] Optionally, the material of the first gate dielectric layer includes a high-K dielectric material.

[0009] Optionally, the material of the second gate dielectric layer includes a high-K dielectric material.

[0010] Optionally, the dielectric layer further has a third opening and a fourth opening.

[0011] Optionally, the process of forming the initial gate dielectric layer in the first opening and the second opening further includes: forming the initial gate dielectric layer in the third opening and the fourth opening respectively.

[0012] Optionally, the process of forming the first initial work function layer in the first opening and the second opening further includes: forming the first initial work function layer on the surface of the initial gate dielectric layer in the third opening and the fourth opening, respectively.

[0013] Optionally, the method for removing the first initial work function layer and part of the initial gate dielectric layer located in the first opening includes: forming a first initial sacrificial layer in the first opening; removing part of the first initial sacrificial layer located in the first opening to form a first sacrificial layer, the top surface of the first sacrificial layer being lower than the top surface of the dielectric layer; etching the first initial work function layer and the initial gate dielectric layer using the first sacrificial layer as a mask to form a first gate dielectric layer and a first work function layer; after forming the first gate dielectric layer, removing the first sacrificial layer and the first work function layer.

[0014] Optionally, the material of the first sacrificial layer includes anti-reflective material.

[0015] Optionally, the process of forming the second initial work function layer in the first opening and the second opening further includes: forming the second initial work function layer on the surface of the initial first work function layer in the third opening and the fourth opening respectively.

[0016] Optionally, the method for removing the first initial work function layer, the second initial work function layer and part of the initial gate dielectric layer located in the second opening includes: forming a second initial sacrificial layer in the second opening; removing part of the second initial sacrificial layer located in the second opening to form a second sacrificial layer, the top surface of the second sacrificial layer being lower than the top surface of the dielectric layer; etching the second initial work function layer, the first initial work function layer and the initial gate dielectric layer using the second sacrificial layer as a mask to form a second gate dielectric layer, a second work function layer and a first work function layer; after forming the second gate dielectric layer, removing the second sacrificial layer, the second work function layer and the first work function layer.

[0017] Optionally, the material of the second sacrificial layer includes anti-reflective material.

[0018] Optionally, after forming the second gate dielectric layer, it also includes: forming a third initial work function layer in the first opening, the second opening, the third opening and the fourth opening, respectively, in the first opening, the third initial work function layer is located on the surface of the second initial work function layer, in the second opening, the third initial work function layer is located on the surface of the second gate dielectric, in the third opening, the third initial work function layer is located on the surface of the second initial work function layer, and in the fourth opening, the third initial work function layer is located on the surface of the second initial work function layer.

[0019] Optionally, after forming the third initial work function layer, it also includes: removing the first initial work function layer, the second initial work function layer, the third initial work function layer and part of the initial gate dielectric layer located in the third opening to form a third gate dielectric layer, and the top surface of the third gate dielectric is lower than the top surface of the dielectric layer.

[0020] Optionally, the material of the third gate dielectric layer includes a high-K dielectric material.

[0021] Optionally, the method for removing the first initial work function layer, the second initial work function layer, the third initial work function layer and part of the initial gate dielectric layer located in the third opening includes: forming a third initial sacrificial layer in the third opening; removing part of the third initial sacrificial layer located in the third opening to form a third sacrificial layer, the top surface of the third sacrificial layer being lower than the top surface of the dielectric layer; etching the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer using the third sacrificial layer as a mask to form a third gate dielectric layer, a first work function layer, a second work function layer and a third work function layer; after forming the third gate dielectric layer, removing the third sacrificial layer, the first work function layer, the second work function layer and the third work function layer.

[0022] Optionally, the material of the third sacrificial layer includes anti-reflective material.

[0023] Optionally, after forming the third gate dielectric layer, it also includes: removing part of the first initial work function layer, part of the second initial work function layer, part of the third initial work function layer and part of the initial gate dielectric layer located in the fourth opening to form a fourth gate dielectric layer, a first work function layer, a second work function layer and a third work function layer, and the top surfaces of the fourth gate dielectric layer, the first work function layer, the second work function layer and the third work function layer are lower than the top surface of the dielectric layer.

[0024] Optionally, the material of the fourth gate dielectric layer includes a high-K dielectric material.

[0025] Optionally, the method for removing part of the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer located in the fourth opening includes: forming a fourth initial sacrificial layer in the fourth opening; removing part of the fourth initial sacrificial layer located in the fourth opening to form a fourth sacrificial layer, the top surface of the fourth sacrificial layer being lower than the top surface of the dielectric layer; etching the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer using the fourth sacrificial layer as a mask to form the fourth gate dielectric layer, the first work function layer, the second work function layer and the third work function layer; after forming the fourth gate dielectric layer, removing the fourth sacrificial layer.

[0026] Optionally, the material of the fourth sacrificial layer includes anti-reflective material.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the formation method of the technical solution of the present invention, the first initial work function layer and a portion of the initial gate dielectric layer located in the first opening are removed to form a first gate dielectric layer; and the first initial work function layer, the second initial work function layer, and a portion of the initial gate dielectric layer located in the second opening are removed to form a second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer are formed separately through different process steps, so that the heights of the first gate dielectric layer and the second gate dielectric layer can be adjusted and controlled separately, thereby ensuring that the heights of the first gate dielectric layer and the second gate dielectric layer are consistent, thereby improving the performance of the final semiconductor structure.

[0029] Furthermore, it also includes: using different process steps to form the third gate dielectric layer and the fourth gate dielectric layer, so that the heights of the third gate dielectric layer and the fourth gate dielectric layer can be adjusted and controlled separately, thereby ensuring that the heights of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer finally formed are consistent, thereby improving the performance of the finally formed semiconductor structure.

[0030] Furthermore, the method for removing the first initial work function layer, the second initial work function layer, the third initial work function layer and part of the initial gate dielectric layer located in the third opening includes: forming a third initial sacrificial layer in the third opening; removing part of the third initial sacrificial layer located in the third opening to form a third sacrificial layer, the top surface of the third sacrificial layer being lower than the top surface of the dielectric layer; etching the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer using the third sacrificial layer as a mask to form a third gate dielectric layer, a first work function layer, a second work function layer and a third work function layer; after forming the third gate dielectric layer, removing the third sacrificial layer, the first work function layer, the second work function layer and the third work function layer.

[0031] By first removing part of the third initial sacrificial layer and then etching the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer using the third sacrificial layer as a mask, the aspect ratio of the opening is reduced in the subsequent process of removing the third sacrificial layer, ensuring that the third sacrificial layer can be completely removed and avoiding the residue of the third sacrificial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 6 It is a structural diagram of a semiconductor structure;

[0033] Figures 7 to 29 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the performance of the multi-threshold voltage FinFET formed in the prior art still needs to be improved, which will be described in detail below with reference to the accompanying drawings.

[0035] Please refer to Figure 1 and Figure 2 , Figure 1 It is a top view of the semiconductor structure with the dielectric layer omitted. Figure 2 It is along Figure 1 A cross-sectional schematic diagram taken along line AA shows a substrate 100; a dielectric layer 101 is formed on the substrate 100, wherein the dielectric layer 101 has a first opening 102, a second opening 103, a third opening 104, and a fourth opening 105; an initial gate dielectric layer 106 and a first work function layer 107 located on the surface of the initial gate dielectric layer 106 are formed in the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105, respectively, wherein the top surface of the first work function layer 107 is lower than the top surfaces of the dielectric layer 101 and the initial gate dielectric layer 106.

[0036] Please refer to Figure 3 , Figure 3 and Figure 2 The viewing direction is consistent with that of the embodiment, and the first work function layer 107 located in the first opening is removed; a second initial work function layer 108 is formed in the first opening 102, the second opening 103, the third opening 104 and the fourth opening 105 respectively, in which the second initial work function layer 108 is located on the surface of the initial gate dielectric layer 106 in the first opening, the second initial work function layer 108 is located on the surface of the first work function layer 107 and the initial gate dielectric layer 106 in the second opening 103, the second initial work function layer 108 is located on the surface of the first work function layer 107 and the initial gate dielectric layer 106 in the third opening 104, the second initial work function layer 108 is located on the surface of the first work function layer 107 and the initial gate dielectric layer 106, and in the fourth opening 105, the second initial work function layer 108 is located on the surface of the first work function layer 107 and the initial gate dielectric layer 106.

[0037] Please refer to Figure 4, remove the second initial work function layer 108 and the first work function layer 107 located in the second opening 103; form a third initial work function layer 109 in the first opening 102, the second opening 103, the third opening 104 and the fourth opening 105 respectively, in which the third initial work function layer 109 is located on the surface of the initial gate dielectric layer 106 in the second opening 103, the third initial work function layer 109 is located on the surface of the second initial work function layer 108 in the first opening, the third initial work function layer 109 is located on the surface of the second initial work function layer 108 in the third opening 104, and the third initial work function layer 109 is located on the surface of the second initial work function layer 108 in the fourth opening 105.

[0038] Please refer to Figure 5 , removing the third initial work function layer 109, the second initial work function layer 108 and the first work function layer 107 located in the third opening 104; forming an initial sacrificial layer (not shown) in the first opening 102, the second opening 103, the third opening 104 and the fourth opening 105, and on the top surface of the dielectric layer 101; etching back the initial sacrificial layer to form a sacrificial layer 110 in the first opening 102, the second opening 103, the third opening 104 and the fourth opening 105, respectively, and the top surface of the sacrificial layer 110 is lower than the top surface of the dielectric layer 101.

[0039] Please refer to Figure 6 In the first opening 102, the second initial work function layer 108, the third initial work function layer 109 and the initial gate dielectric layer 106 are etched with the sacrificial layer 110 as a mask to form a second work function layer 111, a third work function layer 112 and a first gate dielectric layer 113; in the second opening 103, the third initial work function layer 109 and the initial gate dielectric layer 106 are etched with the sacrificial layer 110 as a mask to form a third work function layer 112 and a second gate dielectric layer 114; in the third opening 104, the sacrificial layer 110 is used as a mask to form a The initial gate dielectric layer 106 is etched using the sacrificial layer 110 as a mask to form a third gate dielectric layer 115; in the fourth opening 105, the second initial work function layer 108, the third initial work function layer 109 and the initial gate dielectric layer 106 are etched using the sacrificial layer 110 as a mask to form a second work function layer 111, a third work function layer 112 and a fourth gate dielectric layer 116; after forming the first gate dielectric layer 113, the second gate dielectric layer 114, the third gate dielectric layer 115 and the fourth gate dielectric layer 116, the sacrificial layer 110 is removed.

[0040] In this embodiment, work function layers with different numbers of stacked layers are formed in the first opening 102 , the second opening 103 , the third opening 104 and the fourth opening 105 , so as to adjust the threshold voltage of each transistor. However, when forming the first gate dielectric layer 113, the second gate dielectric layer 114, the third gate dielectric layer 115 and the fourth gate dielectric layer 116, the initial sacrificial layer is etched back and the sacrificial layer 110 is formed at the same time. Since the number of work function layers formed in the first opening 102, the second opening 103, the third opening 104 and the fourth opening 105 is different, the aspect ratios of the first opening 102, the second opening 103, the third opening 104 and the fourth opening 105 are different, resulting in a smaller amount of the initial sacrificial layer etched in the openings with larger aspect ratios, thereby causing the heights of the sacrificial layer 110 formed in the first opening 102, the second opening 103, the third opening 104 and the fourth opening 105 to be different. The heights of the first gate dielectric layer 113, the second gate dielectric layer 114, the third gate dielectric layer 115 and the fourth gate dielectric layer 116 subsequently formed by etching using the sacrificial layer 110 as a mask are also different, which will result in significant differences in the electrical performance of different device structures, affecting the performance of the semiconductor structure finally formed.

[0041] Based on this, the present invention provides a method for forming a semiconductor structure, comprising removing the first initial work function layer and a portion of the initial gate dielectric layer located in the first opening to form a first gate dielectric layer; and removing the first initial work function layer, the second initial work function layer, and a portion of the initial gate dielectric layer located in the second opening to form a second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer are formed separately through different process steps, so that the heights of the first gate dielectric layer and the second gate dielectric layer can be adjusted and controlled separately, thereby ensuring that the heights of the first gate dielectric layer and the second gate dielectric layer are consistent, thereby improving the performance of the final semiconductor structure.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 7 to 29 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 7 and Figure 8 , Figure 7 It is a top view of the semiconductor structure. Figure 8 It is along Figure 7 Schematic diagram of the cross section along the midline BB, providing the base.

[0045] In this embodiment, the base includes a substrate 200 and a plurality of separate fins 201 located on the substrate 200 .

[0046] In other embodiments, the fin may further include a plurality of channel layers arranged at a certain distance along the normal direction of the substrate surface; in other embodiments, the substrate may not have a fin.

[0047] In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial base (not shown), wherein the initial base has a mask layer (not shown), and the mask layer exposes a portion of the top surface of the initial base; etching the initial base using the mask layer as a mask to form the substrate 200 and the fin 201 located on the substrate 200.

[0048] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0049] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0050] In this embodiment, the substrate includes a first region I, a second region II, a third region III and a fourth region IV, and the first region I, the second region II, the third region III and the fourth region IV are used to form transistor structures with different threshold voltages.

[0051] In other embodiments, the substrate may be divided into more than or less than four regions.

[0052] Please refer to Figure 9 , Figure 9 and Figure 8 In the same viewing direction, an isolation layer 202 is formed on the substrate 200 , the isolation layer 202 covers a portion of the sidewall of the fin 201 , and the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0053] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200 ; etching and removing a portion of the initial isolation layer to form the isolation layer 202 , wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0054] The isolation layer 202 is made of an insulating material, which includes silicon oxide or silicon oxynitride. In this embodiment, the isolation layer 202 is made of silicon oxide.

[0055] After forming the isolation layer 202, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer has a first opening and a second opening; and the dielectric layer also has a third opening and a fourth opening. For the specific formation process of the first opening, the second opening, the third opening and the fourth opening, please refer to Figures 10 to 13 .

[0056] Please refer to Figure 10 , a first dummy gate structure 203, a second dummy gate structure 204, a third dummy gate structure 205 and a fourth dummy gate structure 206 are formed on the substrate 200 across the fin 201, the first dummy gate structure 203 is located on the first region I, the second dummy gate structure 204 is located on the second region II, the third dummy gate structure 205 is located on the third region III, and the fourth dummy gate structure 206 is located on the fourth region IV.

[0057] It should be noted that, for the sake of clarity in the description, only one dummy gate structure is formed on each region in the drawings. However, in the actual production process, there may be multiple dummy gate structures formed on each region.

[0058] In this embodiment, the first dummy gate structure 203, the second dummy gate structure 204, the third dummy gate structure 205 and the fourth dummy gate structure 206 respectively include: a dummy gate dielectric layer, a dummy gate layer located on the dummy gate dielectric layer, and sidewalls (not marked) located on the sidewalls of the dummy gate dielectric layer and the dummy gate layer.

[0059] In this embodiment, the material of the dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also be silicon oxynitride.

[0060] In this embodiment, the material of the dummy gate layer is silicon.

[0061] In this embodiment, the first dummy gate structure 203 , the second dummy gate structure 204 , the third dummy gate structure 205 and the fourth dummy gate structure 206 are formed simultaneously, which can effectively improve production efficiency.

[0062] Please refer to Figure 11 After forming the first dummy gate structure 203, the second dummy gate structure 204, the third dummy gate structure 205 and the fourth dummy gate structure 206, the fin 201 is etched using the first dummy gate structure 203, the second dummy gate structure 204, the third dummy gate structure 205 and the fourth dummy gate structure 206 as masks to form a plurality of source and drain openings (not shown) in the fin 201; and the source and drain doping layer 207 is formed in the source and drain openings.

[0063] In this embodiment, the method for forming the source-drain doped layer 207 includes: forming an epitaxial layer in the source-drain opening using an epitaxial growth process; in-situ doping the epitaxial layer during the epitaxial growth process, and doping source-drain ions into the epitaxial layer to form the source-drain doped layer 207.

[0064] The source and drain ions include P-type ions or N-type ions. In this embodiment, the source and drain ion types of the source and drain doped layers 207 formed in the first region I, the second region II, the third region III, and the fourth region IV are different; in other embodiments, the source and drain ion types of the source and drain doped layers formed in the first region, the second region, and the third region may also be the same.

[0065] Please refer to Figure 12 After forming the source / drain doping layer 207 , a dielectric layer 208 is formed on the substrate 200 , and the dielectric layer 208 covers the sidewalls of the first dummy gate structure 203 , the second dummy gate structure 204 , the third dummy gate structure 205 and the fourth dummy gate structure 206 .

[0066] In this embodiment, the material of the dielectric layer 208 is silicon oxide; in other embodiments, the material of the dielectric layer can also be low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

[0067] Please refer to Figure 13 After forming the dielectric layer 208, the first dummy gate structure 203 is removed to form a first opening 209 in the dielectric layer 208, and the first opening 209 is located on the first region I; the second dummy gate structure 204 is removed to form a second opening 210 in the dielectric layer 208, and the second opening 210 is located on the second region II; the third dummy gate structure 205 is removed to form a third opening 211 in the dielectric layer 208, and the third opening 211 is located on the third region III; the fourth dummy gate structure 206 is removed to form a fourth opening 212 in the dielectric layer 208, and the fourth opening 212 is located on the fourth region IV.

[0068] In this embodiment, the dummy gate dielectric layer and the dummy gate layer of the first dummy gate structure 203 , the second dummy gate structure 204 , the third dummy gate structure 205 and the fourth dummy gate structure 206 are specifically removed.

[0069] Please refer to Figure 14 , an initial gate dielectric layer 213 is formed in the first opening 209 and the second opening 210 respectively.

[0070] In this embodiment, the process of forming the initial gate dielectric layer 213 in the first opening 209 and the second opening 210 further includes forming the initial gate dielectric layer 213 in the third opening 211 and the fourth opening 212 , respectively.

[0071] Please continue to refer to Figure 14 After forming the initial gate dielectric layer 213 , the method further includes forming an initial stop layer 214 on the initial gate dielectric layer 213 of the first opening 209 , the second opening 210 , the third opening 211 and the fourth opening 212 .

[0072] The function of the initial stop layer 214 is to stop the etching process of removing the work function layer on the corresponding stop layer during the subsequent removal of the work function layer, thereby preventing the etching process from damaging the gate dielectric layer.

[0073] In this embodiment, the initial gate dielectric layer 213 and the initial stop layer 214 located in the first opening 209 , the second opening 210 , the third opening 211 and the fourth opening 212 are formed simultaneously through a global process, which effectively improves production efficiency.

[0074] In this embodiment, the material of the initial stop layer 214 is tantalum nitride.

[0075] Please refer to Figure 15 A first initial work function layer 215 is formed on the surface of the initial gate dielectric layer 213 in the first opening 209 and the second opening 210 , respectively.

[0076] In this embodiment, the process of forming the first initial work function layer 215 in the first opening 209 and the second opening 210 further includes forming the first initial work function layer 215 on the surface of the initial gate dielectric layer 213 in the third opening 211 and the fourth opening 212 respectively.

[0077] In this embodiment, the first initial work function layer 215 located in the first opening 209 , the second opening 210 , the third opening 211 and the fourth opening 212 are simultaneously formed through a global process, which effectively improves production efficiency.

[0078] In this embodiment, the material of the initial first work function layer 215 is titanium nitride.

[0079] After forming the initial gate dielectric layer 213, the process further includes: removing the first initial work function layer 215 and a portion of the initial gate dielectric layer 213 located in the first opening 209 to form a first gate dielectric layer, wherein the top surface of the first gate dielectric layer is lower than the top surface of the dielectric layer 208. For a detailed process of forming the first gate dielectric layer, please refer to Figures 16 to 18 .

[0080] Please refer to Figure 16 , a first initial sacrificial layer 216 is formed in the first opening 209 .

[0081] In this embodiment, the process of forming the first initial sacrificial layer 216 in the first opening 209 further includes forming the first initial sacrificial layer 216 in the second opening 210 , the third opening 211 , and the fourth opening 212 .

[0082] Please refer to Figure 17 , removing a portion of the first initial sacrificial layer 216 located in the first opening 209 to form a first sacrificial layer 217 , wherein a top surface of the first sacrificial layer 217 is lower than a top surface of the dielectric layer 208 .

[0083] In this embodiment, the method for removing a portion of the first initial sacrificial layer 216 located in the first opening 209 includes: forming a first patterned layer (not shown) on the first initial sacrificial layer 216 to expose a portion of the top surface of the first initial sacrificial layer 216; etching the first initial sacrificial layer 216 using the first patterned layer as a mask to form the first sacrificial layer 217 in the first opening 209; and after forming the first sacrificial layer 217, removing the first patterned layer.

[0084] In this embodiment, the first sacrificial layer 217 is made of a BARC material.

[0085] Please refer to Figure 18 , using the first sacrificial layer 217 as a mask, the first initial work function layer 215 and the initial gate dielectric layer 213 are etched to form a first gate dielectric layer 218 and a first work function layer (not shown); after forming the first gate dielectric layer 218, the first sacrificial layer 217 and the first work function layer are removed.

[0086] In this embodiment, the process of etching the first initial work function layer 215 and the initial gate dielectric layer 213 further includes etching the initial stop layer 214 to form a first stop layer 219 in the first opening 209 .

[0087] In this embodiment, the etching process for removing the first sacrificial layer 217 and the first work function layer stops at the surface of the first stop layer 219 .

[0088] In this embodiment, the first gate dielectric layer 218 is made of a high-K dielectric material (with a dielectric constant greater than 3.9).

[0089] Please refer to Figure 19A second initial work function layer 220 is formed in the first opening 209 and the second opening 210 respectively. In the first opening 209, the second initial work function layer 220 is located on the surface of the first gate dielectric layer 218. In the second opening 210, the second initial work function layer 220 is located on the surface of the first initial work function layer 215.

[0090] In this embodiment, the process of forming the second initial work function layer 220 in the first opening 209 and the second opening 210 further includes forming the second initial work function layer 220 on the surface of the initial first work function layer 215 in the third opening 211 and the fourth opening 212 respectively.

[0091] In this embodiment, the second initial work function layer 220 located in the first opening 209 , the second opening 210 , the third opening 211 and the fourth opening 212 are formed simultaneously through a global process, which effectively improves production efficiency.

[0092] In this embodiment, the second initial work function layer 220 is made of titanium nitride.

[0093] After forming the second initial work function layer 220, the process further includes: removing the first initial work function layer 215, the second initial work function layer 220 and a portion of the initial gate dielectric layer 213 located in the second opening 210 to form a second gate dielectric layer, wherein the top surface of the second gate dielectric layer is lower than the top surface of the dielectric layer 208. For the specific formation process of the second gate dielectric layer, please refer to Figures 20 to 22 .

[0094] Please refer to Figure 20 , a second initial sacrificial layer 221 is formed in the second opening 210 .

[0095] In this embodiment, the process of forming the second initial sacrificial layer 221 in the second opening 210 further includes forming the second initial sacrificial layer 221 in the first opening 209 , the third opening 211 , and the fourth opening 212 .

[0096] Please refer to Figure 21 , a portion of the second initial sacrificial layer 221 located in the second opening 210 is removed to form a second sacrificial layer 222 , wherein a top surface of the second sacrificial layer 222 is lower than a top surface of the dielectric layer 208 .

[0097] In this embodiment, the method for removing a portion of the second initial sacrificial layer 221 located in the second opening 210 includes: forming a second patterned layer (not shown) on the second initial sacrificial layer 221 to expose a portion of the top surface of the second initial sacrificial layer 221; etching the second initial sacrificial layer 221 using the second patterned layer as a mask to form the second sacrificial layer 222 in the second opening 210; and after forming the second sacrificial layer 222, removing the second patterned layer.

[0098] In this embodiment, the second sacrificial layer 222 is made of a BARC material.

[0099] Please refer to Figure 22 , using the second sacrificial layer 222 as a mask, the second initial work function layer 220, the first initial work function layer 215 and the initial gate dielectric layer 213 are etched to form a second gate dielectric layer 223, a second work function layer and a first work function layer (not shown); after the second gate dielectric layer 223 is formed, the second sacrificial layer 222, the second work function layer and the first work function layer are removed.

[0100] In this embodiment, the process of etching the second initial work function layer 220 , the first initial work function layer 215 and the initial gate dielectric layer 213 further includes etching the initial stop layer 214 to form a second stop layer 224 in the second opening 210 .

[0101] In this embodiment, the etching process for removing the second sacrificial layer 222 , the second work function layer, and the first work function layer stops at the surface of the second stop layer 224 .

[0102] In this embodiment, the second gate dielectric layer 223 is made of a high-K dielectric material (with a dielectric constant greater than 3.9).

[0103] Please refer to Figure 23 After forming the second gate dielectric layer 223, a third initial work function layer 225 is formed in the first opening 209, the second opening 210, the third opening 211 and the fourth opening 212 respectively. In the first opening 209, the third initial work function layer 225 is located on the surface of the second initial work function layer 220. In the second opening 210, the third initial work function layer 225 is located on the surface of the second gate dielectric layer 223. In the third opening 211, the third initial work function layer 225 is located on the surface of the second initial work function layer 220. In the fourth opening 212, the third initial work function layer 225 is located on the surface of the second initial work function layer 220.

[0104] In this embodiment, the third initial work function layer 225 located in the first opening 209 , the second opening 210 , the third opening 211 and the fourth opening 212 are simultaneously formed through a global process, which effectively improves production efficiency.

[0105] In this embodiment, the third initial work function layer 225 is made of titanium nitride.

[0106] After forming the third initial work function layer 225, the process further includes: removing the first initial work function layer 215, the second initial work function layer 220, the third initial work function layer 225 and a portion of the initial gate dielectric layer 213 located within the third opening 211 to form a third gate dielectric layer, wherein the top surface of the third gate dielectric layer is lower than the top surface of the dielectric layer 208. For a detailed process of forming the third gate dielectric layer, please refer to Figures 24 to 26 .

[0107] Please refer to Figure 24 , forming a third initial sacrificial layer 226 in the third opening 211 .

[0108] In this embodiment, the process of forming the third initial sacrificial layer 226 in the third opening 211 further includes forming the third initial sacrificial layer 226 in the first opening 209 , the second opening 210 , and the fourth opening 212 .

[0109] Please refer to Figure 25 , a portion of the third initial sacrificial layer 226 located in the third opening 211 is removed to form a third sacrificial layer 227 , wherein a top surface of the third sacrificial layer 227 is lower than a top surface of the dielectric layer 208 .

[0110] In this embodiment, the method for removing a portion of the third initial sacrificial layer 226 located in the third opening 211 includes: forming a third patterned layer (not shown) on the third initial sacrificial layer 226 to expose a portion of the top surface of the third initial sacrificial layer 226; etching the third initial sacrificial layer 226 using the third patterned layer as a mask to form the third sacrificial layer 227 in the third opening 211; and after forming the third sacrificial layer 227, removing the third patterned layer.

[0111] In this embodiment, the third sacrificial layer 227 is made of a BARC material.

[0112] Please refer to Figure 26, using the third sacrificial layer 227 as a mask, the first initial work function layer 215, the second initial work function layer 220, the third initial work function layer 225 and the initial gate dielectric layer 213 are etched to form a third gate dielectric layer 228, a first work function layer, a second work function layer and a third work function layer (not shown); after forming the third gate dielectric layer 228, the third sacrificial layer 227, the first work function layer, the second work function layer and the third work function layer are removed.

[0113] By first removing a portion of the third initial sacrificial layer 226, and then etching the first initial work function layer 215, the second initial work function layer 220, the third initial work function layer 225 and the initial gate dielectric layer 213 using the third sacrificial layer 227 as a mask, in the subsequent process of removing the third sacrificial layer 227, the aspect ratio of the opening is reduced, ensuring that the third sacrificial layer 227 can be completely removed, and avoiding the residue of the third sacrificial layer 227.

[0114] In this embodiment, the process of etching the third initial work function layer 225 , the second initial work function layer 220 , the first initial work function layer 215 and the initial gate dielectric layer 213 further includes: etching the initial stop layer 214 to form a third stop layer 229 in the third opening 211 .

[0115] In this embodiment, the etching process for removing the third sacrificial layer 227 , the first work function layer, the second work function layer, and the third work function layer stops at the surface of the third stop layer 229 .

[0116] In this embodiment, the third gate dielectric layer 228 is made of a high-K dielectric material (with a dielectric constant greater than 3.9).

[0117] After forming the third gate dielectric layer 228, the process further includes: removing a portion of the first initial work function layer 215, a portion of the second initial work function layer 220, a portion of the third initial work function layer 225, and a portion of the initial gate dielectric layer 213 located within the fourth opening 212 to form a fourth gate dielectric layer, a first work function layer, a second work function layer, and a third work function layer, wherein the top surfaces of the fourth gate dielectric layer, the first work function layer, the second work function layer, and the third work function layer are lower than the top surface of the dielectric layer 208. For a detailed process of forming the fourth gate dielectric layer, the first work function layer, the second work function layer, and the third work function layer, please refer to Figures 27 to 29 .

[0118] Please refer to Figure 27 , forming a fourth initial sacrificial layer 230 in the fourth opening 212 .

[0119] In this embodiment, the process of forming the fourth initial sacrificial layer 230 in the fourth opening 212 further includes: forming the fourth initial sacrificial layer 230 in the first opening 209 , the second opening 210 , and the third opening 211 .

[0120] Please refer to Figure 28 , a portion of the fourth initial sacrificial layer 230 located in the fourth opening 212 is removed to form a fourth sacrificial layer 231 , wherein a top surface of the fourth sacrificial layer 231 is lower than a top surface of the dielectric layer 208 .

[0121] In this embodiment, the method for removing a portion of the fourth initial sacrificial layer 230 located in the fourth opening 212 includes: forming a fourth patterned layer (not shown) on the fourth initial sacrificial layer 230 to expose a portion of the top surface of the fourth initial sacrificial layer 230; etching the fourth initial sacrificial layer 230 using the fourth patterned layer as a mask to form the fourth sacrificial layer 231 in the fourth opening 212; and after forming the fourth sacrificial layer 231, removing the fourth patterned layer.

[0122] In this embodiment, the fourth sacrificial layer 231 is made of a BARC material.

[0123] Please refer to Figure 29 , using the fourth sacrificial layer 231 as a mask, the first initial work function layer 215, the second initial work function layer 220, the third initial work function layer 225 and the initial gate dielectric layer 213 are etched to form the fourth gate dielectric layer 232, the first work function layer, the second work function layer 234 and the third work function layer 235; after forming the fourth gate dielectric layer 233, the fourth sacrificial layer 231 is removed.

[0124] In this embodiment, the process of etching the third initial work function layer 225 , the second initial work function layer 220 , the first initial work function layer 215 and the initial gate dielectric layer 213 further includes: etching the initial stop layer 214 to form a fourth stop layer 236 in the fourth opening 212 .

[0125] In this embodiment, the fourth gate dielectric layer 233 is made of a high-K dielectric material (with a dielectric constant greater than 3.9).

[0126] In this embodiment, transistor structures with different threshold voltages are formed by forming work function layers with different numbers of stacked layers in the first opening 209 , the second opening 210 , the third opening 211 and the fourth opening 212 .

[0127] In this embodiment, the first initial work function layer 215 and a portion of the initial gate dielectric layer 213 located in the first opening 209 are removed to form a first gate dielectric layer 218. The first initial work function layer 215, the second initial work function layer 220, and a portion of the initial gate dielectric layer 213 located in the second opening 210 are removed to form a second gate dielectric layer 223. The first gate dielectric layer 218 and the second gate dielectric layer 223 are formed separately through different process steps, so that the heights of the first gate dielectric layer 218 and the second gate dielectric layer 223 can be adjusted and controlled separately, thereby ensuring that the heights of the first gate dielectric layer 218 and the second gate dielectric layer 223 are consistent, thereby improving the performance of the resulting semiconductor structure.

[0128] In addition, it also includes: using different process steps to form the third gate dielectric layer 228 and the fourth gate dielectric layer 233, so that the heights of the third gate dielectric layer 228 and the fourth gate dielectric layer 233 can be adjusted and controlled separately, thereby ensuring that the heights of the first gate dielectric layer 218, the second gate dielectric layer 223, the third gate dielectric layer 228 and the fourth gate dielectric layer 233 finally formed are consistent, thereby improving the performance of the finally formed semiconductor structure.

[0129] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first opening and a second opening; forming an initial gate dielectric layer in the first opening and the second opening respectively; forming a first initial work function layer on the surface of the initial gate dielectric layer in the first opening and the second opening respectively; removing the first initial work function layer and a portion of the initial gate dielectric layer within the first opening to form a first gate dielectric layer, wherein a top surface of the first gate dielectric layer is lower than a top surface of the dielectric layer; forming a second initial work function layer in the first opening and the second opening, respectively, wherein the second initial work function layer is located on a surface of the first gate dielectric layer in the first opening, and the second initial work function layer is located on a surface of the first initial work function layer in the second opening; The first initial work function layer, the second initial work function layer and a portion of the initial gate dielectric layer located in the second opening are removed to form a second gate dielectric layer, wherein the top surface of the second gate dielectric layer is lower than the top surface of the dielectric layer; The first gate dielectric layer and the second gate dielectric layer have the same height; The method for removing the first initial work function layer and a portion of the initial gate dielectric layer located in the first opening includes: forming a first initial sacrificial layer in the first opening; removing a portion of the first initial sacrificial layer located in the first opening to form a first sacrificial layer, wherein a top surface of the first sacrificial layer is lower than a top surface of the dielectric layer; etching the first initial work function layer and the initial gate dielectric layer using the first sacrificial layer as a mask to form a first gate dielectric layer and a first work function layer; after forming the first gate dielectric layer, removing the first sacrificial layer and the first work function layer; The method for removing the first initial work function layer, the second initial work function layer and part of the initial gate dielectric layer located in the second opening includes: forming a second initial sacrificial layer in the second opening; removing part of the second initial sacrificial layer located in the second opening to form a second sacrificial layer, the top surface of the second sacrificial layer is lower than the top surface of the dielectric layer; etching the second initial work function layer, the first initial work function layer and the initial gate dielectric layer using the second sacrificial layer as a mask to form a second gate dielectric layer, a second work function layer and a first work function layer; after forming the second gate dielectric layer, removing the second sacrificial layer, the second work function layer and the first work function layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first gate dielectric layer includes a high-K dielectric material.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second gate dielectric layer includes a high-K dielectric material.

4. The method for forming a semiconductor structure according to claim 1, wherein: The dielectric layer further has a third opening and a fourth opening.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process of forming the initial gate dielectric layer in the first opening and the second opening further includes: forming the initial gate dielectric layer in the third opening and the fourth opening respectively.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process of forming the first initial work function layer in the first opening and the second opening further includes: forming the first initial work function layer on the surface of the initial gate dielectric layer in the third opening and the fourth opening respectively.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sacrificial layer includes anti-reflective material.

8. The method for forming a semiconductor structure according to claim 6, wherein: The process of forming the second initial work function layer in the first opening and the second opening further includes: forming the second initial work function layer on the surface of the initial first work function layer in the third opening and the fourth opening respectively.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second sacrificial layer includes anti-reflective material.

10. The method for forming a semiconductor structure according to claim 8, wherein: After forming the second gate dielectric layer, the method further includes: forming a third initial work function layer in the first opening, the second opening, the third opening and the fourth opening, respectively, wherein in the first opening, the third initial work function layer is located on the surface of the second initial work function layer; in the second opening, the third initial work function layer is located on the surface of the second gate dielectric layer; in the third opening, the third initial work function layer is located on the surface of the second initial work function layer; and in the fourth opening, the third initial work function layer is located on the surface of the second initial work function layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: After forming the third initial work function layer, it also includes: removing the first initial work function layer, the second initial work function layer, the third initial work function layer and part of the initial gate dielectric layer located in the third opening to form a third gate dielectric layer, and the top surface of the third gate dielectric is lower than the top surface of the dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the third gate dielectric layer includes a high-K dielectric material.

13. The method for forming a semiconductor structure according to claim 11, wherein: The method for removing the first initial work function layer, the second initial work function layer, the third initial work function layer and part of the initial gate dielectric layer located in the third opening includes: forming a third initial sacrificial layer in the third opening; removing part of the third initial sacrificial layer located in the third opening to form a third sacrificial layer, the top surface of the third sacrificial layer being lower than the top surface of the dielectric layer; etching the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer using the third sacrificial layer as a mask to form a third gate dielectric layer, a first work function layer, a second work function layer and a third work function layer; after forming the third gate dielectric layer, removing the third sacrificial layer, the first work function layer, the second work function layer and the third work function layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the third sacrificial layer includes anti-reflective material.

15. The method for forming a semiconductor structure according to claim 11, wherein: After forming the third gate dielectric layer, it also includes: removing part of the first initial work function layer, part of the second initial work function layer, part of the third initial work function layer and part of the initial gate dielectric layer located in the fourth opening to form a fourth gate dielectric layer, a first work function layer, a second work function layer and a third work function layer, and the top surfaces of the fourth gate dielectric layer, the first work function layer, the second work function layer and the third work function layer are lower than the top surface of the dielectric layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the fourth gate dielectric layer includes a high-K dielectric material.

17. The method for forming a semiconductor structure according to claim 15, wherein: The method for removing part of the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer located in the fourth opening includes: forming a fourth initial sacrificial layer in the fourth opening; removing part of the fourth initial sacrificial layer located in the fourth opening to form a fourth sacrificial layer, the top surface of the fourth sacrificial layer being lower than the top surface of the dielectric layer; etching the first initial work function layer, the second initial work function layer, the third initial work function layer and the initial gate dielectric layer using the fourth sacrificial layer as a mask to form the fourth gate dielectric layer, the first work function layer, the second work function layer and the third work function layer; after forming the fourth gate dielectric layer, removing the fourth sacrificial layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The material of the fourth sacrificial layer includes anti-reflective material.

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