Semiconductor package structure

Abstract

The present application provides a semiconductor package structure, which includes a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive portion, a second conductive adhesive portion, a plurality of first conductive connection components, a plurality of second conductive connection components, and a build-up line structure below, wherein the integrated chip includes a control chip and a first power chip. The present application adopts the arrangement of integrating the control chip and the first power chip into a single chip to further reduce the volume of the semiconductor package structure. In addition, the present application also provides a manufacturing method of the semiconductor package structure.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor package structure and a manufacturing method thereof, and more particularly to a package structure of a power component and a driving component and a manufacturing method thereof. BACKGROUND

[0002] With the rapid growth of information and vehicle electronics, the Quad Flat No-Lead (QFN) package structure has become an important semiconductor packaging technology because it has better heat dissipation effect and lower impedance and electromagnetic interference.

[0003] In the QFN package structure, the cooper clip technology is a technology to meet the demand of high power. The cooper clip is designed in the shape of an arch bridge with high and low differences, and is bonded to the chip by using the solder dispenser technology. It has a small impedance to carry large current and can withstand the deformation caused by thermal stress, so it is suitable for high power components such as transistors.

[0004] The following will refer to Figures 1A-1D to simply explain the part of the existing package structure using the cooper clip technology to bond the transistor.

[0005] As shown in Figure 1A , a solder paste layer 102 is formed on a lead frame 101 by screen printing. Then, as shown in Figure 1B , a transistor chip 103 is placed on the solder paste layer 102. Then, as shown in Figure 1C , solder 104 is formed on the transistor chip 103. Finally, as shown in Figure 1D , a cooper clip 105 is placed on the corresponding solder paste layer 102 and solder 104, and after the high-temperature reflow process of 380 degrees Celsius, the lead frame 101, the transistor chip 103 and the cooper clip 105 are bonded to each other.

[0006] The above process and finished product have at least the following technical problems:

[0007] (1) The package structure uses a lead frame and a cooper clip, so the height (thickness) of the package cannot be reduced, which limits its application field.

[0008] (2) The solder or solder paste contains a relatively high proportion of lead, and lead metal can cause environmental pollution and have a considerable impact on human health.

[0009] (3) Before all components are fixed by the high-temperature reflow process of 380 degrees Celsius, displacement of each component may occur, resulting in a decrease in precision.

[0010] In view of the above, it is an object of the present application to provide a semiconductor package structure and a manufacturing method thereof, which can further reduce the volume of a semiconductor package structure including a high-power component and a driving component, while increasing electrical performance. Another object of the present application is to provide a semiconductor package structure and a manufacturing method thereof, which can comply with the requirements of environmental protection laws without using a lead-containing process. SUMMARY

[0011] In view of the above, it is an object of the present application to provide a semiconductor package structure and a manufacturing method thereof, which can further reduce the volume of a semiconductor package structure including a high-power component and a driving component, while increasing electrical performance. Another object of the present application is to provide a semiconductor package structure and a manufacturing method thereof, which can comply with the requirements of environmental protection laws without using a lead-containing process.

[0012] To achieve the above objects, the present application provides a semiconductor package structure, which includes a first dielectric layer, a first patterned conductive layer, an integrated chip, a second power chip, a second patterned conductive layer, a first conductive adhesive portion, a second conductive adhesive portion, a plurality of first conductive connection components, a plurality of second conductive connection components, and a build-up wiring structure. The integrated chip includes a control chip and a first power chip.

[0013] The first dielectric layer has a first surface and a second surface disposed opposite to each other. The first patterned conductive layer is disposed on the second surface of the first dielectric layer. The integrated chip is embedded in the first dielectric layer and includes the control chip and the first power chip. The control chip has an active surface and a back surface facing the second surface of the first dielectric layer. The first power chip has a first front surface provided with a first electrode layout and a first back surface provided with a second electrode layout, and the first power chip is electrically connected and adhered to the first patterned conductive layer through the second electrode layout by the first conductive adhesive portion.

[0014] The second power chip is embedded in the first dielectric layer and has a second front surface provided with a third electrode layout and a second back surface provided with a fourth electrode layout, and the second power chip is electrically connected and adhered to the first patterned conductive layer through the fourth electrode layout by the second conductive adhesive portion.

[0015] The second patterned conductive layer is disposed on the first surface of the first dielectric layer and is electrically connected to the first electrode layout of the first power chip and the third electrode layout of the second power chip through the first conductive connection components, respectively.

[0016] The second conductive connection components are electrically connected between the first patterned conductive layer and the second patterned conductive layer.

[0017] The build-up wiring structure is disposed on the first surface of the first dielectric layer and is electrically connected to the second patterned conductive layer.

[0018] In an embodiment according to the present application, the first power chip is a high-side MOSFET and the second power chip is a low-side MOSFET.

[0019] In an embodiment according to the present application, the first electrode layout of the first power chip is identical to the third electrode layout of the second power chip and comprises a gate and a source, respectively, and the second electrode layout of the first power chip is identical to the fourth electrode layout of the second power chip and comprises a drain.

[0020] In an embodiment according to the present application, the source of the first power chip is electrically connected to the drain of the second power chip through one of the first conductive connection components, the second patterned conductive layer, one of the second conductive connection components, the first patterned conductive layer and the first conductive adhesive portion.

[0021] In an embodiment according to the present application, the control chip is a driver chip and the active surface is provided with at least one connection pad, and the second patterned conductive layer is electrically connected to the connection pad through one of the first conductive connection components.

[0022] In an embodiment according to the present application, the first electrode layout of the first power chip is identical to the fourth electrode layout of the second power chip and comprises a gate and a source, respectively, and the second electrode layout of the first power chip is identical to the third electrode layout of the second power chip and comprises a drain.

[0023] In an embodiment according to the present application, the source of the first power chip is electrically connected to the drain of the second power chip through two of the first conductive connection components and the second patterned conductive layer.

[0024] In an embodiment according to the present application, the semiconductor package structure further comprises a first protective layer disposed on the second surface of the first dielectric layer and covering the first patterned conductive layer.

[0025] In an embodiment according to the present application, the build-up line structure further comprises a second dielectric layer, a plurality of third conductive connection components and a third patterned conductive layer. The second dielectric layer has a third surface and a fourth surface disposed opposite to each other, and the fourth surface is connected to the first surface of the first dielectric layer. The third patterned conductive layer is disposed on the third surface of the second dielectric layer and is electrically connected to the second patterned conductive layer through the plurality of third conductive connection components.

[0026] In an embodiment according to the present application, the semiconductor package structure further comprises a second protective layer disposed on the third surface of the second dielectric layer and covering the third patterned conductive layer.

[0027] In addition, to achieve the above object, the present application provides a manufacturing method of a semiconductor package structure, comprising the following steps: providing an additional circuit board; forming a first patterned conductive layer on the additional circuit board; disposing an integrated chip on the first patterned conductive layer through a first conductive adhesive part, wherein the integrated chip comprises a control chip and a first power chip, and the first power chip is a high-side MOSFET; disposing a second power chip on the first patterned conductive layer through a second conductive adhesive part, wherein the second power chip is a low-side MOSFET; forming a plurality of second conductive connection components on the first patterned conductive layer; forming a first dielectric layer having a first surface and a second surface opposite to each other, so as to cover the first patterned conductive layer, the first conductive adhesive part, the second conductive adhesive part, the integrated chip, the second power chip and the second conductive connection components, wherein the second surface of the first dielectric layer is temporarily connected to the additional circuit board; forming a plurality of first conductive connection components to electrically connect with an active surface of the control chip, a first electrode layout of the first power chip and a third electrode layout of the second power chip; forming a second patterned conductive layer on the first surface of the first dielectric layer, and electrically connected with the first conductive connection components and the second conductive connection components; forming a build-up line structure on the first surface of the first dielectric layer, and electrically connected with the second patterned conductive layer; and removing the additional circuit board.

[0028] According to an embodiment of the present application, a back surface of the control chip and a second electrode layout of the first power chip are respectively fixed to the first patterned conductive layer through the first conductive adhesive part and the second conductive adhesive part.

[0029] According to an embodiment of the present application, the second conductive connection components are formed on the surface of the first patterned conductive layer which is not disposed with the first conductive adhesive part or the second conductive adhesive part.

[0030] According to an embodiment of the present application, the first electrode layout of the first power chip comprises a gate and a source, the fourth electrode layout of the second power chip comprises a drain, and the source of the first power chip is electrically connected with the drain of the second power chip through one of the first conductive connection components, the second patterned conductive layer, one of the second conductive connection components, the first patterned conductive layer and the first conductive adhesive part.

[0031] According to an embodiment of the present application, the method for manufacturing the semiconductor package structure further comprises the following steps: forming a plurality of first openings in the first dielectric layer to respectively expose the active surface of the control chip, the first electrode layout of the first power chip and the third electrode layout of the second power chip, and the first conductive connecting components are formed in the first openings.

[0032] According to an embodiment of the present application, the first conductive connecting components and the second patterned conductive layer are formed simultaneously in the same process.

[0033] According to an embodiment of the present application, the first conductive connecting components are formed in advance on the active surface of the control chip, the first electrode layout of the first power chip and the third electrode layout of the second power chip before the step of disposing the integrated chip and the second power chip on the first patterned conductive layer.

[0034] According to an embodiment of the present application, the method for manufacturing the semiconductor package structure further comprises the following step: forming a first protective layer on the second surface of the first dielectric layer to cover the first patterned conductive layer.

[0035] According to an embodiment of the present application, the step of forming the build-up line structure comprises the following sub-steps: forming a plurality of third conductive connecting components on the second patterned conductive layer; forming a second dielectric layer having a third surface and a fourth surface opposite to each other to cover the third conductive connecting components and the second patterned conductive layer, wherein the fourth surface of the second dielectric layer is connected to the first surface of the first dielectric layer; and forming a third patterned conductive layer on the third surface of the second dielectric layer and electrically connected to the third conductive connecting components.

[0036] According to an embodiment of the present application, the method for manufacturing the semiconductor package structure further comprises the following step: forming a second protective layer on the third surface of the second dielectric layer to cover the third patterned conductive layer.

[0037] As mentioned above, the semiconductor package structure and the method for manufacturing the same according to the present application integrate the control chip, such as a driver chip, and the first power chip, such as a transistor chip, into a single chip, so as to reduce the volume of the package structure. On the other hand, the semiconductor process is used to replace the existing reflow process, so as to greatly improve the precision of the package structure. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figures 1A-1D A schematic diagram showing the manufacturing method of the package structure using the copper bridge technology to bond the transistor in the prior art;

[0039] Figure 2A A schematic diagram showing the cross-section of the semiconductor package structure according to the first embodiment of the present application in the first form;

[0040] Figure 2BFIG. 2 is a cross-sectional view of a semiconductor package structure according to a second form of the first embodiment of the present application;

[0041] Figures 3A-3M FIG. 3 is a cross-sectional view of a first manufacturing method of a semiconductor package structure according to the first embodiment of the present application;

[0042] Figures 4A-4C FIG. 4 is a cross-sectional view of a second manufacturing method of a semiconductor package structure according to the first embodiment of the present application;

[0043] Figure 5A-1 FIG. 5 is a cross-sectional view of a semiconductor package structure according to a first form of the first embodiment of the present application connected to an external component; Figure 5A-2

[0044] Figure 5B-1 FIG. 6 is a cross-sectional view of a semiconductor package structure according to a second form of the first embodiment of the present application connected to an external component; Figure 5B-2

[0045] Figure 6 FIG. 7 is a cross-sectional view of a semiconductor package structure according to a second form of the first embodiment of the present application connected to an external component;

[0046] Figure 7 FIG. 8 is a cross-sectional view of a semiconductor package structure according to a second form of the first embodiment of the present application connected to an external component;

[0047] BRIEF DESCRIPTION OF DRAWINGS

[0048] 101: lead frame

[0049] 102: solder paste layer

[0050] 103: transistor chip

[0051] 104: solder

[0052] 105: bridge copper piece

[0053] 2-1, 2-2: semiconductor package structure

[0054] 3, 4: semiconductor package structure

[0055] 20, 20a: first build-up wiring structure

[0056] 30, 30a: second build-up wiring structure

[0057] 21: additional circuit board

[0058] 22: first patterned conductive layer

[0059] 221: surface

[0060] 23-1: first conductive adhesive portion​​

[0061] 23-2: second conductive adhesive portion

[0062] 23-2a, 23-2b: conductive adhesive portion

[0063] 23-2c: conductive adhesive portion

[0064] 24: integration chip

[0065] 25: control chip

[0066] 26: first power chip

[0067] 27: second power chip

[0068] 251: active face

[0069] 252: back face

[0070] 261: first front face

[0071] 262: first back face

[0072] 271: second front face

[0073] 272: second back face

[0074] 28a-1 to 28a-5: first conductive connection assembly

[0075] 28b-1, 28b-2: second conductive connection assembly

[0076] 28aL: end face

[0077] 28bT, 28bL: end face

[0078] 32T, 32L: end face

[0079] 29: first dielectric layer

[0080] 291: first surface

[0081] 292: second surface

[0082] 210: first protective layer

[0083] 29o-1 to 29o-5: first opening

[0084] 210o: second opening

[0085] 35o: third opening

[0086] 31: second patterned conductive layer

[0087] 32-1 to 32-4: third conductive connection assembly

[0088] 33: Second dielectric layer

[0089] 331: Third Surface

[0090] 332: Fourth Surface

[0091] 34: Third patterned conductive layer

[0092] 341: Surface

[0093] 35: Second protective layer

[0094] 36, 38: Conductive components

[0095] 37: Circuit Board

[0096] 39: External Components

[0097] I1: Input connection pad

[0098] S1, S2: Source poles

[0099] G1, G2: Gate

[0100] D1, D2: Absorption

[0101] w1: Horizontal length. Detailed Implementation

[0102] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method as described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative and not intended to limit the invention. It should be noted that components not directly related to this invention have been omitted from the following embodiments and drawings; and the dimensional relationships between components in the drawings are for ease of understanding only and are not intended to limit the actual scale. Furthermore, in the following embodiments, the same components will be described using the same component symbols.

[0103] Figure 2A This is a cross-sectional schematic diagram of a semiconductor packaging structure 2-1 of a first form according to a first embodiment of the present invention. Figure 2A As shown, the first type of semiconductor packaging structure 2-1 includes a first augmentation layer circuit structure 20a and a second augmentation layer circuit structure 30, wherein the first augmentation layer circuit structure 20a is stacked on the second augmentation layer circuit structure 30.

[0104] The first build-up line structure 20a includes a first dielectric layer 29, a first patterned conductive layer 22, a first conductive adhesive portion 23-1, a second conductive adhesive portion 23-2, an integrated chip 24, a second power chip 27, a plurality of first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, 28a-5, a plurality of second conductive connection components 28b-1, 28b-2, a second patterned conductive layer 31, and a first protective layer 210.

[0105] On the other hand, the second build-up line structure 30 includes a second dielectric layer 33, a plurality of third conductive connection components 32-1, 32-2, 32-3, and 32-4, and a third patterned conductive layer 34.

[0106] In the first build-up line structure 20a, the first dielectric layer 29 has a first surface 291 and a second surface 292 disposed opposite to each other. The material of the first dielectric layer 29 can be a high filler content dielectric material, such as a molding compound, which is formed by a Novolac-Based Resin, an Epoxy-Based Resin, or a Silicone-Based Resin as a main matrix, which accounts for about 8 wt% to 12 wt% of the overall proportion of the molding compound, and is doped with fillers accounting for about 70 wt% to 90 wt% of the overall proportion.

[0107] The first patterned conductive layer 22 is disposed on the second surface 292 of the first dielectric layer 29. In detail, the first patterned conductive layer 22 is embedded in the first dielectric layer 29, and a surface 221 of the first patterned conductive layer 22 is exposed to the second surface 292 of the first dielectric layer 29. The first patterned conductive layer 22 has a default circuit layout pattern, and the material thereof is, for example, copper.

[0108] The integrated chip 24 is embedded in the first dielectric layer 29, and the first conductive adhesive portion 23-1 is disposed between the integrated chip 24 and the first patterned conductive layer 22; thus, the integrated chip 24 is fixedly disposed on the first patterned conductive layer 22 through the first conductive adhesive portion 23-1. The integrated chip 24 includes a control chip 25 and a first power chip 26; in other words, the control chip 25 and the first power chip 26 are integrated into a single integrated chip 24 to reduce the volume of the semiconductor package structure 2-1.

[0109] The control chip 25 has a front surface 251 and a back surface 252 oppositely arranged. The control chip 25 is arranged with the back surface 252 facing the second surface 292 of the first dielectric layer 29, and the back surface 252 is connected with the first patterned conductive layer 22 through the first conductive adhesive portion 23-1. The control chip 25 can be, for example, a driver IC, which is used to drive the first power chip 26 and the second power chip 27. In the present embodiment, the front surface 251 of the control chip 25 is provided with at least one connection pad, for example, an input pad I1, and the back surface 252 is not provided with a connection pad. The integrated chip 24 is further provided with a conductive connection component (not shown) to electrically connect the control chip 25 and the first power chip 26, so as to transmit the driving signal generated by the control chip 25 to the first power chip 26.

[0110] The first power chip 26 has a first front surface 261 and a first back surface 262 oppositely arranged. The first power chip 26 is arranged with the first back surface 262 facing the second surface 292 of the first dielectric layer 29, and the first back surface 262 is connected with the first patterned conductive layer 22 through the first conductive adhesive portion 23-1. In addition, the first power chip 26 is further provided with a first electrode layout and a second electrode layout arranged on the first front surface 261 and the first back surface 262, respectively. It is worth mentioning that in the present embodiment, the front surface 251 of the control chip 25 and the first front surface 261 of the first power chip 26 are substantially the same surface, and the back surface 252 of the control chip 25 and the first back surface 262 of the first power chip 26 are substantially the same surface. However, in other embodiments, different structural combinations can be provided according to the design.

[0111] In this embodiment, the first power chip 26 can be a high-side MOSFET, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Thus, in this embodiment, the first electrode layout of the first power chip 26 can include a Gate G1 and a Source S1, and its second electrode layout can include a Drain D1. In other embodiments, the first power chip 26 can also be a bipolar junction transistor (BJT) chip or an Insulated Gate Bipolar Transistor (IGBT) chip, etc. As such, the second electrode layout (which includes the Drain D1) of the first back surface 262 of the first power chip 26 is electrically connected with the first patterned conductive layer 22 through the first conductive adhesive 23-1.

[0112] The first conductive adhesive 23-1 can be, for example, a conductive glue of high heat dissipation conductive material, such as silver or copper; it not only provides the function of fixation between the integrated chip 24 and the first patterned conductive layer 22, but also provides an electrical conduction path between the second electrode layout (which includes the Drain D1) of the first power chip 26 and the first patterned conductive layer 22.

[0113] Similar to the arrangement of the integrated chip 24, the second power chip 27 is also embedded in the first dielectric layer 29 and fixedly arranged on the first patterned conductive layer 22 through the second conductive adhesive 23-2. However, unlike the integrated chip 24, the second power chip 27 itself is a single chip, which does not integrate other control chips or components.

[0114] The second power chip 27 also has a second front surface 271 and a second back surface 272 arranged oppositely; it is arranged with the second back surface 272 facing the second surface 292 of the first dielectric layer 29, and the second back surface 272 is connected with the first patterned conductive layer 22 through the second conductive adhesive 23-2. In addition, the second power chip 27 also has a third electrode layout and a fourth electrode layout, which are arranged on the second front surface 271 and the second back surface 272, respectively.

[0115] Like the first power chip 26, the second power chip 27 can also be a low-side MOSFET, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Thus, the third electrode layout of the second power chip 27 can include a gate G2 and a source S2, and the fourth electrode layout thereof can include a drain D2. In other embodiments, the second power chip 27 can also be a bipolar junction transistor chip or an insulated gate bipolar transistor chip, etc. As such, the fourth electrode layout (which includes the drain D2) of the second back surface 272 of the second power chip 27 is electrically connected to the first patterned conductive layer 22 via the second conductive adhesive portion 23-2 of the high thermal conductive and conductive material.

[0116] The first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, 28a-5 are embedded in the first dielectric layer 29 and disposed between the first surface 291 of the first dielectric layer 29 and the active surface 251 of the control chip 25, the first front surface 261 of the first power chip 26, or the second front surface 271 of the second power chip 27, respectively. Among them, the first conductive connection component 28a-1 is electrically connected to the input connection pad I1 of the control chip 25, the first conductive connection components 28a-2 and 28a-3 are electrically connected to the gate G1 and the source S1 of the first power chip 26, respectively, and the first conductive connection components 28a-4 and 28a-5 are electrically connected to the gate G2 and the source S2 of the second power chip 27, respectively.

[0117] On the other hand, the second conductive connection components 28b-1, 28b-2 are also embedded in the first dielectric layer 29 and disposed on both sides of the second power chip 27. Among them, one end surface 28bT of the second conductive connection components 28b-1, 28b-2 is electrically connected to the first patterned conductive layer 22, and the other end surface 28bL thereof is exposed to the first surface 291 of the first dielectric layer 29. It is particularly noted that, in the first embodiment, the second conductive connection component 28b-1 serves as an electrical conduction path between the source S1 of the first power chip 26 and the drain D2 of the second power chip 27. In addition to the electrical conduction function, the second conductive connection components 28b-1, 28b-2 also have the function of supporting the structural strength to support the first build-up line structure 20a.

[0118] The first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, 28a-5 and the second conductive connection components 28b-1, 28b-2 described above can be, for example, conductive pillars, which are copper pillars, copper alloy pillars, or other conductive metal pillars formed by electroplating processes or non-electroplating processes.

[0119] The second patterned conductive layer 31 is disposed on the first surface 291 of the first dielectric layer 29 (but the second patterned conductive layer 31 is not embedded in the first dielectric layer 29, but embedded in the second dielectric layer 33), and is electrically connected to the active surface 251 of the control chip 25, the first electrode layout of the first front surface 261 of the first power chip 26, and the third electrode layout of the second front surface 271 of the second power chip 27 through the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, 28a-5, respectively. In other words, the second patterned conductive layer 31 is electrically connected to the input connection pad I1 of the control chip 25, the gate G1 and the source S1 of the first power chip 26, and the gate G2 and the source S2 of the second power chip 27 through the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, 28a-5, respectively. In addition, the second patterned conductive layer 31 is also electrically connected to the first patterned conductive layer 22 through the second conductive connection components 28b-1, 28b-2. Like the first patterned conductive layer 22, the second patterned conductive layer 31 also has a default circuit layout pattern, and the material thereof is, for example, copper.

[0120] It is particularly pointed out that in the definition manner of other variations, the second patterned conductive layer 31 can also be defined as a component of the second build-up line structure 30; at this time, the first build-up line structure 20a does not include the second patterned conductive layer 31.

[0121] The first protection layer 210 is disposed on the second surface 292 of the first dielectric layer 29 and covers a surface 221 of the first patterned conductive layer 22 on the uppermost layer of the first build-up line structure 20a. The material of the first protection layer 210 can be selected from insulating and oxidation-resistant materials.

[0122] In the second build-up line structure 30, the second dielectric layer 33 has a third surface 331 and a fourth surface 332 disposed opposite to each other, and the fourth surface 332 is connected to the first surface 291 of the first dielectric layer 29. In other words, the second dielectric layer 33 is disposed below the first dielectric layer 29, and the fourth surface 332 of the second dielectric layer 33 and the first surface 291 of the first dielectric layer 29 are substantially in the same plane. The material of the second dielectric layer 33 is the same as that of the first dielectric layer 29, which can also be a high filler content dielectric material, such as a mold compound.

[0123] The third patterned conductive layer 34 is disposed on the third surface 331 of the second dielectric layer 33 (the third patterned conductive layer 34 is embedded in the second dielectric layer 33), and a surface 341 of the third patterned conductive layer 34 is exposed on the third surface 331 of the second dielectric layer 33, so the third patterned conductive layer 34 can be further electrically connected to other external devices or external components as an electrode pad (for details, please refer to Figure 5A-1 and related descriptions).

[0124] Continuing to refer to Figure 2A , the third conductive connection components 32-1, 32-2, 32-3, 32-4 are also embedded in the second dielectric layer 33. One end surface 32T of the third conductive connection components 32-1, 32-2, 32-3, 32-4 is connected to the second patterned conductive layer 31, and the other end surface 32L is connected to the third patterned conductive layer 34. The third conductive connection components 32-1, 32-2, 32-3, 32-4 can conduct the electrical signals of the input connection pad I1 of the control chip 25, the gate G1 and the source S1 of the first power chip 26, and the gate G2 and the source S2 of the second power chip 27 to the third patterned conductive layer 34, and further to other external components. In addition to the electrical conduction function, the third conductive connection components 32-1, 32-2, 32-3, 32-4 also have the function of supporting the structural strength to support the second build-up wiring structure 30. The third conductive connection components 32-1, 32-2, 32-3, 32-4 can also be, for example, copper pillars, copper alloy pillars, or conductive pillars composed of other conductive metal materials.

[0125] Figure 2B is a cross-sectional view of a second form of a semiconductor package structure 2-2 according to the first embodiment of the present application. As shown in Figure 2B , the second build-up wiring structure 30a of the second form of the semiconductor package structure 2-2 also has a second protective layer 35 at the lowermost position (differently, the first build-up wiring structure 30 of the first form does not have a protective layer disposed below it). The second protective layer 35 is disposed below the second dielectric layer 33, covering the third surface 331 of the second dielectric layer 33 and the third patterned conductive layer 34. The material of the second protective layer 35 can also be selected to be insulating and oxidation-resistant, which is the same as or similar to the material of the first protective layer 210 of the first build-up wiring structure 20a.

[0126] Next, please refer to Figure 2A and Figure 2B and Figures 3A-3M , the first manufacturing method of the first form of the semiconductor package structure 2-1 includes steps S01 to S16, and the manufacturing method of the second form of the semiconductor package structure 2-2 further includes step S17.

[0127] AsFigure 3A As shown, step S01 provides an additional circuit board 21, which can be a metal plate or an insulating plate. It should be particularly noted that this invention employs a panel-level packaging process; the area of ​​the additional circuit board 21 is many times the area of ​​a single wafer. Therefore, the large-size additional circuit board 21 of this invention can simultaneously perform packaging processes on all chips (or dies) cut from multiple wafers, effectively saving manufacturing time.

[0128] Then, in step S02, a first patterned conductive layer 22 is formed on the additional circuit board 21. In this embodiment, the first patterned conductive layer 22 can be formed by photolithography and metal plating techniques, and its material is, for example, copper.

[0129] like Figure 3B As shown, in step S03, a first conductive adhesive portion 23-1 and a second conductive adhesive portion 23-2 are disposed or formed on the first patterned conductive layer 22.

[0130] like Figure 3C As shown, in step S04, the integrated chip 24 is disposed on the first patterned conductive layer 22 through the first conductive adhesive portion 23-1, and the second power chip 27 is disposed on the first patterned conductive layer 22 through the second conductive adhesive portion 23-2.

[0131] In this embodiment, the back surface 252 of the control chip 25 is fixed to the first conductive adhesive portion 23-1, the second electrode layout (including the drain D1) of the first back surface 262 of the first power chip 26 is fixed to the first conductive adhesive portion 23-1, and the fourth electrode layout (including the drain D2) of the second back surface 272 of the second power chip 27 is fixed to the second conductive adhesive portion 23-2.

[0132] like Figure 3D As shown, in step S05, the second conductive connection components 28b-1 and 28b-2 are formed on a portion of the surface of the first patterned conductive layer 22 (the portion of the surface where the first conductive adhesive portion 23-1 or the second conductive adhesive portion 23-2 is not provided), and the second conductive connection components 28b-1 and 28b-2 are disposed on both sides of the second power chip 27. In this embodiment, the second conductive connection components 28b-1 and 28b-2 can be formed by photolithography and metal electroplating, and their material is, for example, copper. In other embodiments, the second conductive connection components 28b-1 and 28b-2 can also be pre-formed by non-electroplating technology and then disposed on the first patterned conductive layer 22 by a conductive adhesive layer (not shown in the figure).

[0133] like Figure 3EAs shown, in step S06, a first dielectric layer 29 is formed on the additional circuit board 21, and covers the first patterned conductive layer 22, the first conductive adhesive portion 23-1, the second conductive adhesive portion 23-2, the integrated chip 24 (including the control chip 25 and the first power chip 26), the second power chip 27, and the second conductive connection components 28b-1 and 28b-2. After forming the first dielectric layer 29, a polishing process can be performed to expose the end faces 28bL of the second conductive connection components 28b-1 and 28b-2 to the first surface 291 of the first dielectric layer 29.

[0134] like Figure 3F As shown, in step S07, first openings 29o-1, 29o-2, 29o-3, 29o-4, and 29o-5 are formed in the first dielectric layer 29 to expose the active surface 251 of the control chip 25 (including the input connection pad I1), the first electrode layout of the first power chip 26 (including the gate G1 and the source S1), and the third electrode layout of the second power chip 27 (including the gate G2 and the source S2), respectively. The first openings 29o-1, 29o-2, 29o-3, 29o-4, and 29o-5 can be formed using laser drilling technology or optionally using photolithography.

[0135] like Figure 3G As shown, step S08 is respectively in Figure 3F The first conductive connection components 28a-1, 28a-2, 28a-3, 29a-4, and 29a-5 are formed at corresponding positions of the first openings 29o-1, 29o-2, 29o-3, 29o-4, and 28a-5, respectively. These components extend downwards and connect to the input connection pad I1 of the control chip 25, the gate G1 and source S1 of the first power chip 26, and the gate G2 and source S2 of the second power chip 27. The first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5 can be fabricated using photolithography and metal electroplating techniques, and their material can be, for example, copper.

[0136] Next, in step S09, a second patterned conductive layer 31 is formed on the first surface 291 of the first dielectric layer 29. The second patterned conductive layer 31 is electrically connected to the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, 28a-5 and the second conductive connection components 28b-1, 28b-2. Similar to the first patterned conductive layer 22, the second patterned conductive layer 31 can be formed by photolithography and metal electroplating techniques, and its material is, for example, copper.

[0137] In other embodiments, the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, 28a-5 and the second patterned conductive layer 31 can be formed simultaneously in the same process (the conductive material constituting the second patterned conductive layer 31 is simultaneously filled downwards). Figure 3F The first openings 29o-1, 29o-2, 29o-3, 29o-4, and 29o-5 are formed to create the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5, thus saving process time. At this step, the first add-on circuit structure 20 is formed on the additional circuit board 21.

[0138] Next, as Figure 3H As shown, step S10 forms the third conductive connection components 32-1, 32-2, 32-3, and 32-4 on the second patterned conductive layer 31. Similar to the second conductive connection components 28b-1 and 28b-2, the third conductive connection components 32-1, 32-2, 32-3, and 32-4 can be formed by photolithography and metal electroplating techniques, and their material is, for example, copper. In other embodiments, the third conductive connection components 32-1, 32-2, 32-3, and 32-4 can also be pre-formed using non-electroplating techniques and then disposed on the second patterned conductive layer 31 through a conductive adhesive layer (not shown in the figure).

[0139] like Figure 3I As shown, in step S11, a second dielectric layer 33 is formed on the first surface 291 of the first dielectric layer 29 to cover the second patterned conductive layer 31 and the third conductive connection components 32-1, 32-2, 32-3, and 32-4.

[0140] like Figure 3J As shown, in step S12, a third patterned conductive layer 34 is formed on the third surface 331 of the second dielectric layer 33, and electrically connected to the third conductive connection components 32-1, 32-2, 32-3, and 32-4.

[0141] like Figure 3K As shown, step S13 performs the molding process again to raise the height of the second dielectric layer 33. After the second molding, the third surface 331 of the second dielectric layer 33 is flush with the surface 341 of the third patterned conductive layer 34. At this step, the second augmented layer circuit structure 30 is formed on the first augmented layer circuit structure 20. Next, step S14 removes the additional circuit board 21.

[0142] like Figure 3L As shown, in step S15, a first protective layer 210 is formed on the second surface 292 of the first dielectric layer 29 after the removal of the additional circuit board 21, which covers the first patterned conductive layer 22, thereby forming a first add-on circuit structure 20a (different from...).Figure 3K The first layered circuit structure 20 is shown.

[0143] like Figure 3M As shown, in step S16, the first layered circuit structure 20a and the second layered circuit structure 30 are flipped vertically as a whole to form a shape as shown in the figure. Figure 2A The semiconductor packaging structure shown is 2-1.

[0144] Furthermore, after step S16, step S17 may also be selectively executed to form as follows: Figure 2B The semiconductor package structure shown in Figure 2-2 is illustrated. Please refer to [reference needed]. Figure 2B In step S17, a second protective layer 35 is formed on the third surface 331 of the second dielectric layer 33, which covers the third patterned conductive layer 34, thereby forming a second add-on circuit structure 30a (which is different from...). Figure 2A The second layered circuit structure 30 shown; the second layered circuit structure 30 does not have a protective layer underneath.

[0145] Next, the following and paired Figures 4A-4C A second manufacturing method for semiconductor package structure 2-1 is briefly described, which includes steps S21 to S35 (the second manufacturing method for the second form of semiconductor package structure 2-2 also includes step S36).

[0146] First, steps S21 to S24 are the same as steps S01 to S04 of the first manufacturing method, so they will not be repeated here.

[0147] Next, please refer to Figure 4A As shown, in step S25, a first conductive connection component 28a-1 is pre-formed or disposed on the active surface 251 of the control chip 25, which is electrically connected to the input connection pad I1 of the control chip 25. Furthermore, first conductive connection components 28a-2 and 28a-3 are pre-formed or disposed on the first electrode layout of the first front surface 261 of the first power chip 26, which are electrically connected to the gate G1 and source S1 of the first power chip 26, respectively. Furthermore, first conductive connection components 28a-4 and 28a-5 are pre-formed or disposed on the third electrode layout of the second front surface 271 of the second power chip 27, which are electrically connected to the gate G2 and source S2 of the second power chip 27, respectively.

[0148] After the integrated chip 24 and the second power chip 27 are fixed to the first conductive adhesive portion 23-1 and the second conductive adhesive portion 23-2, step S25 is executed to form the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5 on the active surface 251 of the control chip 25, the first front surface 261 of the first power chip 26, and the second front surface 271 of the second power chip 27. In this embodiment, the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5 are formed using photolithography and metal electroplating techniques.

[0149] In another embodiment, before the integrated chip 24 and the second power chip 27 are fixed to the first conductive adhesive portion 23-1 and the second conductive adhesive portion 23-2, first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5 can be pre-formed on the input connection pad I1 of the control chip 25, the gate G1 and source S1 of the first power chip 26, and the gate G2 and source S2 of the second power chip 27, respectively. In this embodiment, the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5 are pre-formed conductive bumps.

[0150] Then as Figure 4B As shown, in step S26, second conductive connection components 28b-1 and 28b-2 are formed on the first patterned conductive layer 22, and the end faces 28bL of the second conductive connection components 28b-1 and 28b-2 are substantially flush with the end faces 28aL of the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5. The remaining details of step S26 are the same as those of step S05 in the first manufacturing method, and therefore will not be repeated.

[0151] Then as Figure 4C As shown, in step S27, a first dielectric layer 29 is formed, and the end faces 28bL of the second conductive connection components 28b-1 and 28b-2, as well as the end faces 28aL of the first conductive connection components 28a-1, 28a-2, 28a-3, 28a-4, and 28a-5, are exposed to the first surface 291 of the first dielectric layer 29 through a polishing process.

[0152] Next, the subsequent steps S28 to S35 are performed to finally form the following... Figure 2A The semiconductor packaging structure 2-1 shown is identical to steps S28 to S35 of the first manufacturing method, and therefore will not be repeated here.

[0153] Furthermore, step S36 (same as step S17 in the first manufacturing method) can be selectively performed to form a second protective layer 35 on the third surface 331 of the second dielectric layer 33, thus ultimately forming a layer as shown in the figure. Figure 2B The semiconductor packaging structure shown in Figure 2-2.

[0154] In this invention, the two forms of semiconductor packaging structures 2-1 and 2-2 in the first embodiment can be further electrically connected to other external components. For example: Please refer to... Figure 5A-1 In the first form of semiconductor package structure 2-1, since the third patterned conductive layer 34 can serve as an electrode pad, a conductive component 36 is further formed on its exposed surface 341, and the semiconductor package structure 2-1 is electrically connected to a circuit board 37 through the conductive component 36. The circuit board 37 can be a printed circuit board, a metal core circuit board, or a glass circuit board.

[0155] In addition, such as Figure 5A-2 As shown, a plurality of second openings 210o can be formed in the first protective layer 210 of the semiconductor package structure 2-1, exposing a portion of the first patterned conductive layer 22; and conductive components 38 are formed at corresponding positions of each second opening 210o. An external component 39 can be electrically connected to the semiconductor package structure 2-1 through the conductive components 38.

[0156] On the other hand, please refer to Figure 5B-1 In the second form of semiconductor package structure 2-2, the second protective layer 35 may form a plurality of third openings 35o and a conductive component 36 at the corresponding position, so as to place the semiconductor package structure 2-2 on the circuit board 37 through the conductive component 36.

[0157] Similarly, such as Figure 5B-2 As shown, the first protective layer 210 of the second type of semiconductor package structure 2-2 can also form multiple second openings 210o and correspondingly provide conductive components 38, so that the external component 39 can be disposed above the semiconductor package structure 2-2 through the conductive components 38.

[0158] In addition to the two forms of semiconductor packaging structures 2-1 and 2-2 in the first embodiment described above, this invention further discloses different packaging structures in other embodiments. Please refer to [link to relevant documentation]. Figure 6 and Figure 7 See below for further explanation.

[0159] Figure 6 This is a cross-sectional schematic diagram of the semiconductor packaging structure 3 according to a second embodiment of the present invention. Figure 6As shown, the main difference between the semiconductor package structure 3 of the second embodiment and the semiconductor package structure 2-1 of the first embodiment is that the second power chip 27 is arranged in a reverse direction in the vertical direction, in other words, the second front surface 271 of the second power chip 27 is arranged upwardly toward the direction of the first patterned conductive layer 22.

[0160] In the second embodiment, the gate G2 and the source S2 of the second power chip 27 are respectively electrically connected to the first patterned conductive layer 22 through two separate conductive adhesive portions 23-2a and 23-2b. In addition, the drain D2 of the second power chip 27 is electrically connected to the source S1 of the first power chip 26 through the second patterned conductive layer 31 (which does not need to pass through the second conductive connection assembly 28b-1 as shown), and the electrical conduction path between the second power chip 27 and the first power chip 26 can be shortened to increase the electrical performance. Figure 2A

[0161] Figure 7 A cross-sectional view of a semiconductor package structure 4 according to a third embodiment of the present application is shown in FIG. 4. As shown, the main difference between the semiconductor package structure 4 of the third embodiment and the semiconductor package structure 2-1 of the first embodiment is that the second power chip 27 is arranged in a vertical stacked manner with the integrated chip 24, and the second power chip 27 is embedded in the second dielectric layer 33 of the second build-up line structure 30. Figure 7

[0162] In the third embodiment, the second front surface 271 of the second power chip 27 is arranged downwardly toward the direction of the third patterned conductive layer 34, and the drain D2 of the second power chip 27 is arranged on the second patterned conductive layer 31 through the conductive adhesive portion 23-2c. Since the drain D2 of the second power chip 27 is directly arranged below the source S1 of the first power chip 26, the electrical conduction path between the second power chip 27 and the first power chip 26 is further shortened. In addition, since the second power chip 27 is arranged in a stacked manner below the integrated chip 24, the horizontal length w1 of the semiconductor package structure 4 can be reduced.

[0163] In summary, the semiconductor package structure and the manufacturing method thereof according to the present application integrate the control chip 25 and the first power chip 26 into a single chip (the integrated chip 24), and arrange the second power chip 27 in the same package structure unit, which has the following technical effects:

[0164] (1) The three-chip package (the control chip 25, the first power chip 26, and the second power chip 27) is simplified into a two-chip package (the integrated chip 24 and the second power chip 27), and the volume of the package structure unit is further reduced.

[0165] ​​(2) The semiconductor process is used to replace the existing reflow process, so as to greatly improve the precision of the packaging structure.

[0166] (3) The process abandons the lead-containing reflow process, so as to meet the requirements of environmental protection trend and laws.

[0167] (4) The surface of the integrated chip 24 and the second power chip 27 is fixedly arranged on the first patterned conductive layer (or the second patterned conductive layer) through the conductive adhesive part, which can simplify the process and achieve good heat dissipation effect based on the high heat dissipation material characteristics of the conductive adhesive part.

[0168] The above merely describes the preferred embodiments of the present application, and cannot limit the patent application scope of the present application. Any equivalent modification or change made by those skilled in the art according to the spirit of the present application shall be included in the protection scope of the claims.

Claims

1. A semiconductor package structure, comprising: The integrated chip includes: a first dielectric layer having a first surface and a second surface opposite to each other; a first patterned conductive layer embedded in the first dielectric layer, and one side surface of which is exposed to the second surface of the first dielectric layer; a control chip having an active surface and a back surface, and the control chip is adhered to the first patterned conductive layer by the back surface through a first conductive adhesive; a first power chip being a high-end field effect transistor chip, and having a first front surface provided with a first electrode layout, and having a first back surface provided with a second electrode layout, and the first power chip is electrically connected and adhered to the first patterned conductive layer by the second electrode layout through the first conductive adhesive; a second patterned conductive layer located on the first surface of the first dielectric layer, and electrically connected to the first electrode layout of the first power chip and the active surface of the control chip through a plurality of first conductive connection components of copper or copper alloy material respectively; a second conductive connection component embedded in the first dielectric layer and electrically connected between the first patterned conductive layer and the second patterned conductive layer; a second dielectric layer covering the second patterned conductive layer, and having a third surface and a fourth surface opposite to each other, and being connected to the first surface of the first dielectric layer by the fourth surface; a second power chip being a low-end field effect transistor chip embedded in the second dielectric layer, and having a second front surface provided with a third electrode layout, and having a second back surface provided with a fourth electrode layout, and the second power chip is electrically connected and adhered to the second patterned conductive layer by the fourth electrode layout through a second conductive adhesive, and the second power chip and the integrated chip partially overlap in a projection direction; a third patterned conductive layer embedded in the second dielectric layer, and one side surface of which is exposed to the third surface of the second dielectric layer, and electrically connected to the third electrode layout of the second power chip through a plurality of fourth conductive connection components of copper or copper alloy; and a plurality of third conductive connection components embedded in the second dielectric layer and electrically connected between the second patterned conductive layer and the third patterned conductive layer. The first electrode layout of the first power chip is the same as the third electrode layout of the second power chip and respectively includes a gate and a source, and the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip and respectively includes a drain.

2. The semiconductor package structure of claim 1, wherein, The source of the first power chip is electrically connected to the drain of the second power chip through one of the first conductive connection components, the second patterned conductive layer and the second conductive adhesive.

3. The semiconductor package structure of claim 2, wherein, The control chip is a driving chip and the active surface is provided with at least one connection pad, and the second patterned conductive layer is electrically connected to the connection pad through one of the first conductive connection components.

4. The semiconductor package structure of claim 1, wherein, ​

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