Semiconductor memory, method of making the same, and electronic device

Abstract

The present disclosure provides a semiconductor memory, a manufacturing method thereof, and an electronic device. The semiconductor memory includes a bit line layer having at least one bit line, an active layer located above the bit line layer and including at least one active region, a gate stack surrounding sidewalls of the active region, and a storage layer located above the active layer and including at least one storage region. The semiconductor memory separates the bit line layer and the storage region vertically to the upper / lower active region, so that the two layers separated in the upper / lower direction and the contact connecting the intermediate active region are not in the same plane, ensuring the process margin in the plane, thereby improving the design level of the semiconductor memory and improving the performance of the semiconductor memory.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor memory, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that typically includes an array of memory cells, each capable of storing a bit of information. A typical memory cell configuration consists of a capacitor for storing an electrical charge (i.e., a bit of information) and an access transistor that provides access to the capacitor during read and write operations. The access transistor is connected between a bit line and the capacitor and is gated (turned on or off) by a word line signal. During a read operation, the stored bit of information is read from the cell via the associated bit line. During a write operation, a bit of information is stored in the cell from the bit line via the transistor. Memory cells are inherently dynamic (due to leakage) and must therefore be periodically refreshed.

[0003] The manufacturing method of the existing DRAM is, from bottom to top, in sequence, active area (area where transistor source / drain is located), bit line (BL) and storage area (area where capacitor is located), each area is separated from each other, and therefore also has a first contact (i.e., bit line node contact) connecting the active area and the bit line and a second contact (i.e., storage node contact) connecting the active area and the storage area. At this time, the second contact connecting the uppermost storage area passes through the plane where the first contact and the bit line exist to connect the electrode of the storage area.

[0004] Therefore, if there is a lack of sufficient process margin between the first contact and the second contact, leakage will occur, and if the separation distance between the second contact and the bit line is insufficient, current interference phenomenon and other problems will also occur, which causes difficulties for further miniaturization of DRAM devices. SUMMARY

[0005] The purpose of the present disclosure is to provide a semiconductor memory, a manufacturing method of a semiconductor memory, and an electronic device.

[0006] A first aspect of the present disclosure provides a semiconductor memory, comprising:

[0007] a bit line layer having at least one bit line;

[0008] an active layer located above the bit line layer and comprising at least one active region;

[0009] a gate stack, sidewalls of the active region being surrounded by the gate stack; and,

[0010] a storage layer located above the active layer and comprising at least one storage region.

[0011] The second aspect of the present disclosure provides a method for manufacturing a semiconductor memory, comprising:

[0012] providing a substrate;

[0013] forming at least one bit line on the substrate and forming a bit line isolation film on the bit line;

[0014] forming a gate conductor layer on the bit line isolation film;

[0015] forming an active region slot through the gate conductor layer and the bit line isolation film until the bit line is exposed;

[0016] forming, in the active region slot, a gate dielectric layer, a side wall portion of the active region, and a plug portion in sequence;

[0017] forming a landing pad and a storage region on top of the active region, the top of the active region being in contact with the storage region through the landing pad.

[0018] The third aspect of the present disclosure provides an electronic device, comprising:

[0019] the semiconductor memory as described in the first aspect.

[0020] The present disclosure has the following advantages compared with the prior art:

[0021] (1) There is no other conductive substance on the bit line plane, which can reduce parasitic capacitance.

[0022] (2) Since there is no other conductive substance on the bit line plane, the width of the bit line can be increased to reduce the resistance of the bit line.

[0023] (3) A vertical channel is formed, which facilitates adjustment of the channel length.

[0024] (4) In the channel process, the bit line contact and the storage contact process can be performed together, so the process can be simplified.

[0025] (5) The bit line and the bit line contact and the storage contact process are not performed on the same plane, so there is no need to consider the separation process margin. BRIEF DESCRIPTION OF DRAWINGS

[0026] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments and are not meant to limit the present disclosure. Moreover, the same reference numerals in the attached drawings indicate the same or similar components. In the drawings:

[0027] FIG. 1AA plan view of a semiconductor memory provided in this disclosure is shown;

[0028] FIG. 1B A cross-sectional view taken along line a in Figure 1 is shown;

[0029] FIG. 1C A cross-sectional view taken along line b in Figure 1 is shown;

[0030] FIG. 2 A flowchart illustrating the method for fabricating the semiconductor memory provided in this disclosure is shown;

[0031] FIG. 3A This shows a plan view after the bit line formation stage in the semiconductor memory fabrication method of this disclosure;

[0032] FIG. 4A This shows a plan view after the gate conductor layer formation stage in the semiconductor memory fabrication method of this disclosure;

[0033] FIG. 5A This shows a plan view after the active region trench formation stage in the semiconductor memory fabrication method of this disclosure;

[0034] FIG. 6A This shows a plan view after the active region formation stage in the semiconductor memory fabrication method of this disclosure;

[0035] FIGS. 3B-6B It is along FIGS. 3A-6A A cross-sectional view taken from line a;

[0036] FIGS. 3C-6C It is along FIGS. 3A-6A A cross-sectional view taken from line b;

[0037] FIGS. 5D-5F Is FIG. 5B Based on this, a stage cross-sectional diagram of the active region is formed. Detailed Implementation

[0038] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] Various structural diagrams according to embodiments of the present disclosure are shown in the drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and may omit certain details. The shapes of various regions, layers, and the relative size and positional relationship therebetween shown in the drawings are merely exemplary, and may deviate in actuality due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed according to actual needs by those skilled in the art.

[0040] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0041] The existing manufacturing method of DRAM is that, from bottom to top, there are the layer where the active region is located, the layer where the bit line is located, and the layer where the storage region is located, and each region is separated from each other, thus also having a first contact (i.e., bit line node contact) connecting the active region and the bit line, and a second contact (i.e., storage node contact) connecting the active region and the storage region. At this time, the second contact connecting the uppermost storage region passes through the plane where the first contact and the bit line exist to connect the electrode of the storage region.

[0042] Therefore, if there is a lack of process margin between the first contact and the second contact, it will cause leakage, and if the separation distance between the second contact and the bit line is insufficient, it will also cause current interference and other problems.

[0043] In order to solve the problems existing in the prior art described above, embodiments of the present disclosure provide a semiconductor memory, a manufacturing method of a semiconductor memory, and an electronic device, which are described below with reference to the drawings.

[0044] FIG. 1A A plan view of a semiconductor memory provided by the present disclosure is shown; FIG. 1B A cross-sectional view taken along line a in FIG. 1A A cross-sectional view taken along line b in FIG. 1C A cross-sectional view taken along line b in FIG. 1A A cross-sectional view taken along line b in

[0045] Please refer to FIGS. 1A-1C The semiconductor memory includes, from bottom to top in the vertical direction, a bit line layer 100, an active layer 200, a storage layer 300, and a gate stack 210.

[0046] Specifically, the bit line layer 100 has at least one bit line 110. The active layer 200 is located above the bit line layer 100 and includes at least one active region 220, the sidewall of which is surrounded by the gate stack 210. The storage layer 300 is located above the active layer 200 and includes at least one storage region (not shown). In embodiments of the present application, the storage region includes a capacitor structure, which can be, for example, a lower electrode, a dielectric layer, and an upper electrode (not shown).

[0047] Specifically, the active region 220 has a circular horizontal cross section, and as shown, the active region 220 is a vertical cylinder.

[0048] Specifically, the bit line layer 100 further includes a bit line substrate 120, on which the at least one bit line 110 is located, and a bit line isolation film 130 covering the at least one bit line 110.

[0049] Specifically, the bit line substrate 120 can be made of silicon dioxide, the bit line 110 can be made of tungsten, and the bit line isolation film 130 can be made of silicon nitride. Of course, the materials of the above-mentioned parts can also be other materials as required, and the present disclosure does not limit this.

[0050] Continuing to refer to FIGS. 1A-1C The bottom of the active region 220 is in contact with the bit line 110 through the bit line isolation film 130. The top of the active region 220 is in contact with the storage region in the storage layer 300 through the landing pad 230.

[0051] Specifically, the active region 220 includes a plug 222 and a sidewall 221 surrounding the plug 222, the top of the plug 222 is in contact with the storage region in the storage layer 300 through the landing pad 230, and the bottom of the plug 222 is in contact with the bit line 110 through the bit line isolation film 130.

[0052] Specifically, the plug 222 of the active region 220 and the sidewall 221 surrounding the plug 222 can both be made of doped polysilicon.

[0053] Specifically, the gate stack 210 includes a gate dielectric layer 211 and a gate conductor layer 212, the height of the gate conductor layer 212 is lower than that of the active region 220, and the height of the gate dielectric layer 211 is flush with that of the active region 220. One side of the gate dielectric layer 211 is attached to the sidewall and bottom wall of the sidewall 221 of the active region 220, and the other side of the gate dielectric layer 211 is attached to the gate conductor layer 212. That is, the sidewall of the active region 220 is surrounded by the gate dielectric layer 211.

[0054] Specifically, the gate conductor layer 212 and the landing pad 230 can be made of tungsten, and the gate dielectric layer 211 can be made of silicon dioxide.

[0055] Compared with the existing semiconductor memory, the semiconductor memory provided by the present disclosure separates the bit line layer and the storage area vertically to the upper / lower of the active area, so that the two layers separated by the upper / lower and the contact connecting the intermediate active area are not in the same plane, which ensures the process margin on the plane, thereby improving the design level of the semiconductor memory and improving the performance of the semiconductor memory.

[0056] Please refer to FIG. 2 The present disclosure also provides a manufacturing method of a semiconductor memory for preparing the semiconductor memory as in the above embodiments. FIGS. 3A-6A and FIG. 1A Embodiments of the manufacturing method of the semiconductor memory are shown at various stages. FIGS. 3B-6B and FIG. 1B is a cross-sectional view taken along the line a of FIGS. 3A-6A and FIG. 1A FIGS. 3C-6C and FIG. 1C is a cross-sectional view taken along the line b of FIGS. 3A-6A and FIG. 1A FIGS. 5D-5F is a semiconductor structure diagram based on FIG. 5B

[0057] The manufacturing method comprises the following steps:

[0058] Step S101: providing a substrate 120.

[0059] Step S102: forming at least one bit line 110 on the substrate 120, and forming a bit line isolation film 130 on the bit line 110.

[0060] Specifically, please refer to FIGS. 3A-3C The manufacturing material of the substrate 120 can be silicon dioxide and has a certain thickness. Then the pattern of the bit line 110 as shown in the figure can be formed on the substrate 120 by related processes, and the bit line isolation film 130 is deposited on the bit line 110. Specifically, the manufacturing material of the bit line 110 can be tungsten, and the manufacturing material of the bit line isolation film 130 can be silicon nitride. Of course, the manufacturing materials of the above-mentioned parts can also be other materials meeting the requirements, which are not limited by the present disclosure. It can be seen that since no other conductive substance is arranged on the bit line plane, the bit line capacitance can be reduced, and the bit line resistance can be reduced by increasing the width of the bit line.

[0061] Step S103: forming a gate conductor layer 212 on the bit line isolation film 130.

[0062] Specifically, please refer to FIGS. 4A-4C ​​​After the process of forming the bit line isolation film 130, a pattern of the gate conductor layer 212 can be formed on the bit line isolation film 130 by a related process. Specifically, the material of the gate conductor layer 212 can be tungsten. For example, the pattern of the gate conductor layer 212 can be formed by a damascene process and a photolithography process.

[0063] Step S104: Forming an active region slot H through the gate conductor layer 212 and the bit line isolation film 130 until the bit line 110 is exposed.

[0064] Specifically, referring to FIGS. 5A-5C , after the pattern of the gate conductor layer 212 is formed, a layer of isolation film composed of silicon nitride can be deposited on the gate conductor layer 212. A photolithography and etching process is performed at the intersection of the pattern of the bit line 110 and the pattern of the gate conductor layer 212 to form a pattern of the active region slot H until the underlying bit line 110 is exposed. The bottom of the active region slot H can be slightly recessed into the bit line 110 so as to facilitate the subsequent contact between the bit line and the active region.

[0065] Step S105: Forming the gate dielectric layer 211, the sidewall 221 of the active region and the plug 222 in the active region slot H in sequence.

[0066] The specific manufacturing process is described on the basis of FIG. 5B , and referring to FIG. 5D , the gate dielectric layer 211 and the first layer of doped polysilicon 221 are deposited on the sidewall and the bottom wall of the active region slot H in sequence. Referring to FIG. 5E , the gate dielectric layer 211 and the first layer of doped polysilicon 221 are etched to form the sidewall 221 of the active region 220 and expose the underlying bit line 110. Specifically, the existing sidewall process can be used for manufacturing. Referring to FIG. 5F , the second layer of doped polysilicon is deposited in the space surrounded by the sidewall 221, and then the chemical mechanical planarization (CMP) process is used to remove the excess doped polysilicon outside the active region slot H to form the plug 222 of the active region. Specifically, after the active region is formed, the semiconductor structure is as shown in FIGS. 6A-6C In this step, a vertical active region is formed, which makes it easy to adjust the length of the active region. Moreover, through this step, the active region and the bit line are directly connected, and no other contact process is needed, thus simplifying the process steps.

[0067] Step S106: Forming a landing pad and a storage region on the top of the active region, and the top of the active region is in contact with the storage region through the landing pad. The storage region can include a capacitor structure.

[0068] Specifically, referring to FIGS. 1A-1CAs shown in the figure, in order to form the storage region, a honeycomb-shaped landing pad 230 is formed on the active region 220, the material of the landing pad 230 can be tungsten, and the landing pads are filled with silicon dioxide. Through this step, the top of the active region and the storage region are connected through the landing pad, and no other contact process is needed, so the process steps can also be simplified.

[0069] In the above method, in the active channel process, the bit line contact and the storage contact process are performed together, so that the process can be simplified. Moreover, the bit line and the bit line contact and the storage contact process are not performed in the same plane, so that the separation margin does not need to be considered.

[0070] The semiconductor memory manufactured by the above method separates the bit line layer and the storage region vertically to the top / bottom of the active region, so that the two layers separated vertically and the contact connecting the middle active region are not in the same plane, which ensures the process margin in the plane, so that the limitation of the design level of the semiconductor memory can be improved, and the performance of the semiconductor memory is improved.

[0071] The embodiments of the present disclosure also provide an electronic device including the semiconductor memory in the above embodiments. The semiconductor memory can be included in at least one of a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a mobile power supply.

[0072] Please refer to FIGS. 1A-1C , the semiconductor memory includes, from bottom to top in the vertical direction, a bit line layer 100, an active layer 200, a storage layer 300, and a gate stack 210.

[0073] Specifically, the bit line layer 100 has at least one bit line 110. The active layer 200 is located above the bit line layer 100 and includes at least one active region 220, and the sidewall of the active region 220 is surrounded by the gate stack 210. The storage layer 300 is located above the active layer 200 and includes at least one storage region (not shown). In the embodiments of the present disclosure, the storage region includes a capacitor structure, for example, can be a lower electrode, a dielectric layer and an upper electrode (not shown).

[0074] Specifically, the active region 220 has a circular horizontal cross section, as shown in the figure, the active region 220 is a vertical cylindrical shape.

[0075] Specifically, the bit line layer 100 further includes: a bit line substrate 120, and the at least one bit line 110 is located on the bit line substrate 120; and a bit line isolation film 130 covering the at least one bit line 110.

[0076] Specifically, the material of the bit line substrate 120 can be silicon dioxide, the material of the bit line 110 can be tungsten, and the material of the bit line isolation film 130 can be silicon nitride. Of course, the materials of the above-mentioned parts can also be other materials meeting the requirements, and the present disclosure does not limit this.

[0077] With reference to the above description FIGS. 1A-1C The bottom of the active region 220 is in contact with the bit line 110 through the bit line isolation film 130. The top of the active region 220 is in contact with the storage region in the storage layer 300 through the landing pad 230.

[0078] Specifically, the active region 220 includes a plug 222 and a sidewall 221 surrounding the plug 222, the top of the plug 222 is in contact with the storage region in the storage layer 300 through the landing pad 230, and the bottom of the plug 222 is in contact with the bit line 110 through the bit line isolation film 130.

[0079] Specifically, the material of the plug 222 and the sidewall 221 surrounding the plug 222 of the active region 220 can be doped polysilicon.

[0080] Specifically, the gate stack 210 includes a gate dielectric layer 211 and a gate conductor layer 212, the height of the gate conductor layer 212 is lower than that of the active region 220, and the height of the gate dielectric layer 211 is flush with that of the active region 220. One side of the gate dielectric layer 211 is attached to the sidewall and bottom wall of the sidewall 221 of the active region 220, and the other side of the gate dielectric layer 211 is attached to the gate conductor layer 212.

[0081] Specifically, the material of the gate conductor layer 212 and the landing pad 230 can be tungsten, and the material of the gate dielectric layer 211 can be silicon dioxide.

[0082] The electronic device provided by the present disclosure, the semiconductor memory, by vertically separating the bit line layer and the storage region to the upper / lower active region, the contact of the two layers separated by the upper / lower and the intermediate active region is not in the same plane, which ensures the process margin on the plane, so as to improve the limitation of the design level of the semiconductor memory and improve the performance of the semiconductor memory.

[0083] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the above-described methods. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0084] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor memory, characterized in that, include: Provide substrate; At least one bit line is formed on the substrate, and a bit line isolation film is formed on the bit line; A gate conductor layer is formed on the bit line isolation film; An active region trench is formed that penetrates the gate conductor layer and the bit line isolation film until the bit line is exposed; A gate dielectric layer, a sidewall of the active region, and a plug are sequentially formed in the active region trench; A landing pad and a storage area are formed on top of the active area, and the top of the active area is in contact with the storage area through the landing pad; A gate dielectric layer, a sidewall of the active region, and a plug are sequentially formed in the active region trench, including: A gate dielectric layer and a first layer of doped polysilicon are sequentially deposited on the sidewall and bottom wall of the active region trench; The gate dielectric layer and the first layer of doped polysilicon are etched to form the sidewalls of the active region, and the bit line is exposed; A second layer of doped polysilicon is deposited in the space surrounding the sidewalls to form the plug of the active region.

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