Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device may include a substrate including a cell region and a core / peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core / peripheral region of the substrate. Lower contact plugs and upper contact plugs may be between the bit line structures. The lower contact plugs and the upper contact plugs may be stacked in a vertical direction. A land pad pattern may contact an upper sidewall of the upper contact plug. The land pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the land pad pattern may be higher than an upper surface of each of the bit line structures. Peripheral contact plugs may be in the core / peripheral region of the substrate. Wiring may be electrically connected to an upper surface of the peripheral contact plugs.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2020 - 0094363, filed with the Korean Intellectual Property Office on Jul. 29, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of the present disclosure relate to semiconductor devices and methods of manufacturing the semiconductor devices. More specifically, aspects of the present disclosure relate to dynamic random access memory (DRAM) devices and methods of manufacturing the DRAM devices. Background Art

[0004] As DRAM devices are increasingly integrated, the size of patterns used in the formation can be reduced and the arrangement density of the patterns can be increased. Accordingly, the number of lithography processes for forming the patterns constituting the DRAM may increase. In addition, when forming patterns, defects of the patterns may be generated. Summary of the Invention

[0005] Aspects of the present disclosure provide a semiconductor device and a method for manufacturing the semiconductor device.

[0006] According to some aspects of the present disclosure, a semiconductor device is provided. The semiconductor device may include a substrate including a cell region and a core / peripheral region. A plurality of bit - line structures may be in the cell region of the substrate. A gate structure may be in the core / peripheral region of the substrate. A lower contact plug and an upper contact plug may be between the bit - line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit - line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit - line structures. A peripheral contact plug may be in the core / peripheral region of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

[0007] According to some example embodiments, a semiconductor device is provided. The semiconductor device may include a substrate including a cell region and a core / peripheral region. A first gate structure is buried in the substrate. The first gate structure may be below the upper surface of the substrate. A plurality of bit line structures may be in the cell region of the substrate. A second gate structure may be in the core / peripheral region of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A capping insulating pattern may be on the bit line structures, the upper contact plug, and the second gate structure. A landing pad pattern may be in contact with an upper sidewall of the upper contact plug. The landing pad pattern may be in a recessed portion of an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. Wiring may be in a first opening of the capping insulating pattern in the core / peripheral region. A contact plug may be in a second opening communicating with the first opening. The contact plug may be electrically connected to the wiring, and the contact plug may be below the wiring. A capacitor may be electrically connected to the landing pad pattern. The landing pad pattern, the contact plug, and the wiring include the same metal.

[0008] According to some example embodiments, a semiconductor device is provided. The semiconductor device may include a substrate including a cell region and a core / peripheral region. A conductive structure may be formed in the cell region of the substrate. A gate structure may be in the core / peripheral region of the substrate. A cell contact plug may be between the conductive structures. A landing pad pattern may be electrically connected to the cell contact plug. An upper surface of the landing pad pattern may be higher than an upper surface of each of the conductive structures. An insulating layer may cover the core / peripheral region of the substrate. A contact plug and wiring may be in an opening included in the insulating layer. An upper surface of the wiring may be coplanar with an upper surface of the insulating layer.

[0009] According to some example embodiments, a method of manufacturing a semiconductor device is provided. The method may include forming a bit line structure in a cell region of a substrate. A gate structure may be formed in a core / peripheral region of the substrate. Lower contact plugs and upper contact plugs may be formed between the bit line structures. The lower contact plugs and the upper contact plugs may be stacked in a vertical direction. A capping insulating layer may be formed on the bit line structures and the upper contact plugs in the cell region and on the gate structure in the core / peripheral region. A first photoresist pattern for forming a landing pad pattern in the cell region and a contact plug in the core / peripheral region may be formed on the capping insulating layer by performing a first exposure process. The layer may be etched using the first photoresist pattern as an etching mask to form a first opening in the cell region and a second opening in the core / peripheral region. A second photoresist pattern for forming a wiring in the core / peripheral region may be formed on the capping insulating layer by performing a second exposure process. The layer may be etched using the second photoresist pattern as an etching mask to form a third opening communicating with the second opening in the core / peripheral region. A metal material may be used to fill the first opening, the second opening, and the third opening to form a landing pad pattern in the first opening, a contact plug in the second opening, and a wiring in the third opening.

[0010] In some example embodiments, a semiconductor device may be manufactured by a process that potentially has a reduced number of operations. For example, in some embodiments, a semiconductor device, pattern, and / or contact plug having a bottom surface at a different level in a vertical direction from a substrate may be formed by a single photolithography process. In the case of a DRAM device, a pad pattern electrically connected to a capacitor in a cell region and a peripheral contact plug contacting a wiring in a substrate or a core / peripheral region may be formed by a single photolithography process using EUV light. A peripheral wire may be formed on the peripheral contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings. Figures 1 to 47 Illustrate non-limiting example embodiments described herein.

[0012] Figures 1 to 5 are cross-sectional views and plan views showing aspects of a semiconductor device according to some example embodiments;

[0013] Figures 6 to 31 is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to some example embodiments;

[0014] Figure 32 is a cross-sectional view showing aspects of a semiconductor device according to some example embodiments;

[0015] Figure 33 is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to some example embodiments;

[0016] Figure 34 is a cross-sectional view showing aspects of a semiconductor device according to some example embodiments;

[0017] Figures 35 to 41 is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to some example embodiments;

[0018] Figure 42 and Figure 43 is a cross-sectional view showing aspects of a semiconductor device according to some example embodiments; and

[0019] Figures 44 to 47 is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0020] Figures 1 to 5 is a cross-sectional view and a plan view showing aspects of a semiconductor device according to example embodiments.

[0021] Figure 1 、 Figure 2 、 Figure 4 and Figure 5 is a cross-sectional view, and Figure 3 is a plan view.

[0022] Figure 1 includes cross-sectional views taken along line A-A' and line B-B' of Figure 3 , and Figure 2 includes cross-sectional views taken along line C-C' and line D-D' of Figure 3 . Figures 1 to 5 shows the structures in cell region I and core / peripheral region II. In Figure 2 , the cross-sectional view taken along line C-C' of Figure 3 shows the structures in cell region I and core / peripheral region II, and the cross-sectional view taken along line D-D' of Figure 3 shows the structures in core / peripheral region II. Figure 4 is an enlarged cross-sectional view showing a part of a land pad pattern, and Figure 5 is an enlarged cross-sectional view of a part of a transistor in core / peripheral region II.

[0023] Reference Figures 1 to 5, the substrate 100 may include a cell region I and a core / periphery region II. A first gate structure 116, a bit line structure 140, a spacer structure 152, an insulating pattern 154, lower contact plugs 158 and upper contact plugs 162, landing pad patterns 198a, and a capacitor 200 may be formed in the cell region I of the substrate 100. A second gate structure 142, a lower interlayer 132, contact plugs 198b, and wirings 198c may be formed in the core / periphery region II of the substrate 100.

[0024] The substrate 100 may include silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, or GaSb. In some exemplary embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0025] The substrate 100 may include isolation trenches, and device isolation patterns 106 may be formed in the isolation trenches. The substrate 100 between the isolation trenches may be used as an active pattern 104. The device isolation patterns 106 may include, for example, silicon oxide and / or silicon nitride.

[0026] The first gate structure 116 may be buried in the substrate 100 of the cell region I. That is, the first gate structure 116 may extend in a first direction (see Figure 3 ) through the upper portions of the active pattern 104 and the device isolation pattern 106. A plurality of first gate structures may be spaced apart from each other in a second direction. The first gate structure 116 may include a first gate insulating layer 110, a gate electrode 112, and a capping mask pattern 114.

[0027] The first gate insulating layer 110 may be formed on the surface of the active pattern 104. The gate electrode 112 may be formed on the first gate insulating layer 110 and the device isolation pattern 106. The gate electrode 112 may extend in the first direction. The capping mask pattern 114 may cover the upper surface of the gate electrode 112.

[0028] The first gate insulating layer 110 may include an oxide such as silicon oxide. The gate electrode 112 may include, for example: a metal such as tungsten (W), titanium (Ti), tantalum (Ta), etc., and / or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, etc. The capping mask pattern 114 may include a nitride such as silicon nitride.

[0029] A first insulating layer 120 and a second insulating layer 122 may be sequentially stacked on the active pattern 104, the device isolation pattern 106, and the capping mask pattern 114 in the cell region I. A second gate insulating layer 121 may be formed on the active pattern 104 in the core / periphery region II.

[0030] The bit line structure 140 in the unit region I may include a first conductive pattern 124a, a first barrier pattern (not shown), a first metal pattern 128a, a first capping layer pattern 130a, and a second capping layer pattern 134a that are sequentially stacked. In an exemplary embodiment, the bit line structure 140 may be formed on the active pattern 104 and the second insulating layer 122. The bit line structure 140 may extend in a second direction.

[0031] A portion of the first conductive pattern 124a included in the bit line structure 140 may be formed in a first opening 150 in the upper surfaces of the active pattern 104, the device isolation pattern 106, and the capping mask pattern 114 adjacent to the active pattern 104. Accordingly, a portion of the first conductive pattern 124a may contact the upper surface of the active pattern 104 exposed through the first opening 150. The first conductive pattern 124a may include, for example, polysilicon doped with impurities.

[0032] The first barrier pattern may include, for example: metals such as titanium (Ti), tantalum (Ta), etc., and / or metal nitrides such as titanium nitride, tantalum nitride, etc. In some embodiments, the first barrier pattern may include multiple metals and / or multiple metal nitrides. The first metal pattern 128a may be, for example, a metal such as tungsten (W). The first capping layer pattern 130a and the second capping layer pattern 134a may include nitrides such as silicon nitride.

[0033] The second gate structure 142 in the core / peripheral region II may include a gate insulating layer 121, a first conductive pattern 124a, a first metal pattern 128a, and a first capping layer pattern 130a that are sequentially stacked.

[0034] As described above, each of the second gate structure 142 in the core / peripheral region II and the bit line structure 140 in the unit region I may include a stacked structure that includes a first conductive pattern 124a, a first metal pattern 128a, and a first capping layer pattern 130a. That is, the second gate structure 142 and the bit line structure 140 may have the same stacked structure.

[0035] Spacers 136 may be formed on the sidewalls of the second gate structure 142. In addition, the bit line structure 140 may extend from the unit region I to a part of the core / peripheral region II. The spacers 136 may be formed on the edges of the bit line structure 140 in the second direction.

[0036] The lower interlayer insulating layer 132 may be formed on the substrate between the second gate structures 142. The second capping layer pattern 134a may be formed on the second gate structures 142 and the lower interlayer insulating layer 132 in the core / peripheral region II.

[0037] The spacer structure 152 may be formed on the sidewalls of the bit line structure 140, and the spacer structure 152 may extend in a second direction. In some example embodiments, the spacer structure 152 may include a plurality of spacers stacked from the sidewalls of the bit line structure 140. In some example embodiments, the spacer structure 152 may include air spacers, which serve as empty spaces.

[0038] The insulating pattern 154 may be formed on the second insulating layer 122. The insulating pattern 154 may be formed on the first gate structure 116 between the bit line structures 140.

[0039] In some example embodiments, the upper surface of the insulating pattern 154 may be coplanar with the upper surface of the bit line structure 140. The insulating pattern 154 may include a nitride such as silicon nitride.

[0040] A third opening may be formed at a portion between the bit line structures 140 and a portion between the insulating pattern 154, and the third opening may expose the active pattern 104. The lower contact plug 158 and the upper contact plug 162 may be formed in the third opening.

[0041] The lower contact plug 158 may fill the lower portion of the third opening. The lower contact plug 158 may include, for example, polysilicon doped with impurities.

[0042] In some example embodiments, the upper surface of the lower contact plug 158 may be higher than the upper surface of the first conductive pattern 124a included in the bit line structure 140, and the upper surface of the lower contact plug 158 may be lower than the upper surface of the first capping layer pattern 130a. In other words, the upper surface of the lower contact plug 158 may be between the upper surface of the first conductive pattern 124a and the upper surface of the first capping layer pattern 130a. In some embodiments, the upper surface of the lower contact plug 158 may be disposed at a position along the sidewall of the first metal pattern 128a. However, the position of the upper surface of the lower contact plug 158 may not be limited thereto. When the lower contact plug 158 is formed, the parasitic capacitance between the lower contact plug 158 and the bit line structure 140 may be reduced.

[0043] The upper spacer 160 may be formed on the upper sidewalls of the insulating pattern 154. Specifically, the upper spacer 160 may be formed on the upper sidewalls of the insulating pattern 154 such that the upper spacer 160 is positioned higher than the upper surface of the lower contact plug 158. Although not shown, the upper spacer may be further formed on the spacer structure 152.

[0044] The upper contact plug 162 may contact the upper surface of the lower contact plug 158. The upper contact plug 162 may be formed in the upper portion of the third opening.

[0045] The upper contact plug 162 may include a second barrier pattern 161a and a second metal pattern 161b. The second barrier pattern 161a may be formed on the upper surfaces of the spacer structure 152, the upper spacer 160, and the lower contact plug 158, and the second barrier pattern 161a may conform to the surfaces of the upper surfaces of the spacer structure 152, the upper spacer 160, and the lower contact plug 158. The second barrier pattern 161a is formed on the upper surface of the lower contact plug 158. Accordingly, the second barrier pattern 161a may surround the sidewalls and the bottom of the second metal pattern 161b. The second barrier pattern 161a may include, for example, a metal such as titanium (Ti) or tantalum (Ta), and / or a metal nitride such as titanium nitride or tantalum nitride. In some embodiments, the second barrier pattern 161a may include multiple metals and / or multiple metal nitrides. The second metal pattern 161b may include a metal such as tungsten (W).

[0046] In some exemplary embodiments, the uppermost surface of the upper contact plug 162 may be coplanar with the uppermost surface of the bit line structure 140.

[0047] A third capping insulating pattern 170a may be formed on the upper contact plug 162 and the bit line structure 140 in the cell region I, and the third capping insulating pattern 170a may be formed on the second capping layer pattern 134a in the core / peripheral region II. The third capping insulating pattern 170a may include a nitride such as silicon nitride.

[0048] The third capping insulating pattern 170a in the cell region I may include a sixth opening 180. A part of the upper contact plug 162, the spacer structure 152, and the bit line structure 140 may be exposed through the sixth opening 180. The parts of the upper contact plug 162, the spacer structure 152, and the bit line structure 140 exposed through the sixth opening 180 may have an etched shape such that the parts exposed through the sixth opening and having the etched shape may correspond to the recessed parts. Among the upper contact plug 162, the spacer structure 152, and the bit line structure 140, the parts facing the recessed parts may not have an etched shape.

[0049] A landing pad pattern 198a electrically connected to the upper contact plug 162 may be formed in the sixth opening 180. The lower part of the landing pad pattern 198a may contact the sidewalls of the upper contact plug 162 and the sidewalls of the first capping layer pattern 130a and the second capping layer pattern 134a of the bit line structure 140. The bottom of the landing pad pattern 198a may be lower than the uppermost surface of the bit line structure 140 and the uppermost surface of the upper contact plug 162.

[0050] The third capping insulating pattern 170a may be on the upper sidewalls of the landing pad patterns 198a. The third capping insulating pattern 170a may fill the space between the landing pad patterns 198a.

[0051] The landing pad patterns 198a may include a third barrier pattern 196a and a third metal pattern 196b. The third barrier pattern 196a may be formed on the sidewalls and bottom of the layer exposed through the sixth opening 180, and the third barrier pattern 196a may be flush with the surface on which the third barrier pattern 196a is formed. The third metal pattern 196b may be formed on the third barrier pattern 196a to fill the sixth opening 180.

[0052] The third barrier pattern 196a may include, for example, a metal such as titanium (Ti) or tantalum (Ta), and / or a metal nitride such as titanium nitride or tantalum nitride. In some embodiments, the third barrier pattern 196a may include multiple metals and / or multiple metal nitrides. The third metal pattern 196b may include a metal such as tungsten (W).

[0053] The upper surface of the landing pad pattern 198a may be substantially coplanar with the upper surface of the third capping insulating pattern 170a.

[0054] The landing pad pattern 198a may have a size of about 20 nm or less. This size may be a critical dimension. The landing pad pattern 198a may have a pitch of 40 nm or less. The pitch may be the sum of the width of each of the patterns and the spacing between the patterns. The landing pad patterns 198a may be densely arranged, and the landing pad patterns 198a may have a first arrangement density. In some exemplary embodiments, in a plan view, the landing pad patterns 198a may be arranged in a honeycomb shape.

[0055] Accordingly, the landing pad pattern 198a may be formed on the upper contact plug 162. The third barrier pattern 196a may be disposed at the contact portion between the upper contact plug 162 and the landing pad pattern 198a.

[0056] The third capping insulating pattern 170a in the core / periphery region II may include a ninth opening 194. The ninth opening 194 may extend in one direction to have a trench shape. In addition, a seventh opening 182a may be formed below the ninth opening 194 and may communicate with the ninth opening 194.

[0057] The contact plug 198b may be formed in the seventh opening 182a. The wiring 198c may be formed in the ninth opening 194. The arrangement of the contact plugs 198b may not be denser than the arrangement of the landing pad pattern 198a. The arrangement density of the contact plugs 198b may be lower than the arrangement density of the landing pad pattern 198a. In other words, the contact plugs 198b may have a second arrangement density that is lower than the first arrangement density of the landing pad pattern 198a. The pitch of the contact plugs 198b may be greater than the pitch of the landing pad pattern 198a and the pitch of the wiring 198c.

[0058] The contact plug 198b may include a first contact plug and a second contact plug. The first contact plug may be formed on an end portion in a second direction of the bit line structure 140 in the core / periphery region II. The first contact plug may pass through an upper portion of the bit line structure 140, and the first contact plug may contact a first conductive pattern 124a in the bit line structure 140. In addition, the second contact plug may pass through the lower interlayer dielectric 132, and the second contact plug may contact a substrate adjacent to a side surface of the second gate structure 142.

[0059] The wiring 198c may extend to contact an upper portion of the contact plug 198b.

[0060] The wiring 198c may have a size (e.g., line width) of about 20 nm or less. This size may be a critical dimension. The pitch of the wiring 198c may be about 40 nm or less. The wiring 198c may be arranged more densely than the arrangement of the contact plugs. The wiring 198c may have a third arrangement density that is higher than the second arrangement density of the contact plug 198b.

[0061] The contact plug 198b and the wiring 198c may include a third barrier pattern 196a and a third metal pattern 196b. The third barrier pattern 196a may be formed on a surface exposed through the seventh opening 182a and the ninth opening 194, and the third barrier pattern 196a may conform to the surface on which the third barrier pattern 196a is formed. The third metal pattern 196b may be formed on the third barrier pattern 196a to fill the seventh opening 182a and the ninth opening 194.

[0062] The landing pad pattern 198a, the contact plug 198b, and the wiring 198c may be formed by the same one or more processes such that the landing pad pattern 198a, the contact plug 198b, and the wiring 198c may include the same conductive material. The third barrier pattern 196a included in the landing pad pattern 198a, the contact plug 198b, and the wiring 198c may have the same material, and the third metal pattern 196b included in the landing pad pattern 198a, the contact plug 198b, and the wiring 198c may have the same material.

[0063] The capacitor 200 may be formed on the upper surface of the landing pad pattern 198a.

[0064] As described above, the semiconductor device may include a lower contact plug 158 and an upper contact plug 162 between bit line structures 140. The lower portion of the landing pad pattern 198a may be positioned between the upper portion of the upper contact plug 162 and the upper portion of the bit line structure 140. The lower portion of the landing pad pattern 198a may contact the upper sidewalls of the upper contact plug 162 and the bit line structure 140, respectively.

[0065] The landing pad pattern 198a may include a third metal pattern 196b and a third barrier pattern 196a formed on the sidewalls and bottom surface of the third metal pattern 196b.

[0066] The contact plugs 198b and wirings 198c in the core / periphery region II may have a conductive material substantially the same as that of the landing pad pattern 198a.

[0067] In some embodiments, components of the semiconductor device, such as the landing pad pattern 198a, the contact plugs 198b, and the wirings 198c, may be manufactured by a process with a reduced number of operations.

[0068] Figures 6 to 31 is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to some example embodiments.

[0069] Specifically, Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 15 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 and Figure 30 are cross-sections taken along lines A-A' and B-B' of Figure 3 . Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 and Figure 31 are cross-sections taken along lines C-C' and D-D' of Figure 3 .Figures 6 to 31 In Figure 3 , the cross-sections taken along the lines A-A' and B-B' of Figures 6 to 31 are the cross-sections of the cell region I. In Figure 3 , the cross-section taken along the line C-C' of Figure 3 is the cross-section of the cell region I and the core / peripheral region II, and the cross-section taken along the line D-D' of

[0070] Reference Figure 6 and Figure 7 , the substrate 100 may include the cell region I and the core / peripheral region II. The cell region I may be the region where memory cells are formed, and the core / peripheral region II may be the region where peripheral circuits or core circuits are formed.

[0071] The upper portion of the substrate 100 may be etched to form isolation trenches 102, and device isolation patterns 106 may be formed to fill the isolation trenches 102. The portions of the substrate 100 between the device isolation patterns 106 may be active patterns 104. The device isolation patterns 106 may serve as field regions, and the active patterns 104 may serve as active regions.

[0072] Reference Figure 8 and Figure 9 , impurity regions (not shown) may be formed in the substrate 100 of the cell region I by performing an ion implantation process. The active patterns 104 and portions of the device isolation patterns in the cell region I may be etched to form first recesses 108 extending in a first direction.

[0073] Thereafter, first gate structures 116 may be formed in the first recesses 108. The first gate structures 116 may include first gate insulating layers 110, gate electrodes 112, and capping mask patterns 114.

[0074] Reference Figure 10 and Figure 11 , a first insulating layer 120 and a second insulating layer 122 may be sequentially formed on each of the active patterns 104, device isolation patterns 106, and capping mask patterns 114 in the cell region I. A second gate insulating layer 121 may be formed on the active pattern 104 in the core / peripheral region II.

[0075] A first conductive layer 124 may be formed on the second insulating layer 122 and the second gate insulating layer 121.

[0076] Portions of the first conductive layer 124, the second insulating layer 122, and the first insulating layer 120 in the etchable unit region I may be etched to form a first opening 150 that exposes a portion of the active pattern 104 in the unit region I. In some example embodiments, the first opening 150 may expose a central portion of the upper surface of each of the active patterns 104 in the unit region I.

[0077] A second conductive layer 126 may be formed to fill the first opening 150. The upper surfaces of the first conductive layer 124 and the second conductive layer 126 may be coplanar with each other. The first conductive layer 124 and the second conductive layer 126 may include polysilicon doped with impurities. The first conductive layer 124 and the second conductive layer 126 may include the same material such that the first conductive layer 124 and the second conductive layer 126 may be merged or may be merged into one layer.

[0078] A first barrier layer (not shown), a first metal layer 128, and a first capping layer 130 may be sequentially formed on the upper surfaces of the first conductive layer 124 and the second conductive layer 126.

[0079] A first etch mask pattern (not shown) may be formed on the first capping layer 130 to cover the unit region I and expose a portion of the core / peripheral region II. The first capping layer 130, the first metal layer 128, the first barrier layer, and the first conductive layer 124 in the core / peripheral region II may be sequentially etched using the first etch mask pattern. Accordingly, a preliminary bit line structure may be formed on the unit region I. In addition, a second gate structure 142 may be formed on the core / peripheral region II. The second gate structure 142 may include a second gate insulating layer 121, a first conductive pattern 124a, a first metal pattern 128a, and a first capping layer pattern 130a that may be sequentially stacked.

[0080] Spacers 136 may be formed on the sidewalls of the preliminary bit line structure and the sidewalls of the second gate structure 142. In the etching process for forming the spacers 136, portions of the first insulating layer 120, the second insulating layer 122, and the second gate insulating layer 121 between the spacers 136 may be removed. In some example embodiments, these portions may be removed together, for example, in a single process. In some example embodiments, a nitride liner (not shown) may be further formed on the upper surface of the preliminary bit line structure, the upper surface of the second gate structure 142, the spacers 136, and the substrate 100 between the spacers. The nitride liner may include silicon nitride.

[0081] Reference Figure 12 and Figure 13 , a lower interlayer dielectric 132 may be formed on the substrate 100 of the core / peripheral region II to fill the region between the second gate structures 142.

[0082] A second capping layer may be formed over the preliminary bit line structure, the second gate structure 142, and the lower insulating interlayer 132. The second capping layer may include silicon nitride. The first capping layer 130, the nitride liner, and the second capping layer include silicon nitride, and thus, the first capping layer 130, the nitride liner, and the second capping layer may be combined into one silicon nitride layer.

[0083] The second capping layer and the first capping layer 130 in the cell region I may be patterned to form a second capping layer pattern 134a and a first capping layer pattern 130a in the cell region I and the core / peripheral region II. The stack of the first capping layer pattern 130a and the second capping layer pattern 134a in the cell region I may have a linear shape extending in the second direction. The second capping layer pattern 134a may be formed over the entirety of the core / peripheral region II.

[0084] The first metal layer 128, the first barrier layer, the second conductive layer 126, and the first conductive layer 124 in the cell region I may be etched using the first capping layer pattern 130a and the second capping layer pattern 134a as an etch mask. Accordingly, a first conductive pattern 124a, a first barrier pattern (not shown), a first metal pattern 128a, and the first capping layer pattern 130a and the second capping layer pattern 134a may be sequentially stacked over the active pattern 104 in the first opening 150. Additionally, the first conductive pattern 124a, the first barrier pattern, the first metal pattern 128a, the first capping layer pattern 130a, and the second capping layer pattern 134a may be sequentially stacked over the second insulating layer 122 adjacent to the first opening 150. The first conductive layer and the second conductive layer may have the same material such that the conductive patterns formed by patterning the first conductive layer and the second conductive layer may be referred to as the first conductive pattern 124a.

[0085] The stacked structure including the first conductive pattern 124a, the first barrier pattern, the first metal pattern 128a, the first capping layer pattern 130a, and the second capping layer pattern 134a may be referred to as a bit line structure 140.

[0086] The bit line structure 140 may extend in the second direction, and a plurality of bit line structures 140 are arranged in the first direction. The bit line structure 140 may extend in the second direction to contact the surface of the active pattern 104 exposed through the first opening 150.

[0087] Reference Figure 14 may be made to form a spacer structure 152 to cover the sidewalls of the bit line structure 140. In Figure 14 the spacer structure 152 may be simply shown as one spacer, but in some example embodiments, the spacer structure 152 may include a plurality of spacers stacked laterally.

[0088] In some example embodiments, the spacer structure 152 may include a first spacer and a second spacer. The first spacer may cover the lower sidewall of the bit line structure 140 positioned in the first opening 150, and the second spacer may be formed on the uppermost surface of the first spacer to cover the upper sidewall of the bit line structure 140. In addition, a third spacer and a fourth spacer may be sequentially stacked on the surface of the second spacer.

[0089] A first interlayer dielectric (not shown) may be formed to fill the space between the spacer structures 152. After a second etch mask pattern (not shown) is formed on the first interlayer dielectric and the spacer structures 152, the first interlayer dielectric may be etched using the etch mask pattern to form a second opening (not shown).

[0090] In some example embodiments, the second etch mask pattern may extend in a first direction. A plurality of second etch mask patterns may be spaced apart from each other in a second direction. In some example embodiments, the second opening may be formed to overlap with the first gate structure 116 thereunder. Thereafter, an insulating pattern 154 may be formed to fill the second opening. The insulating pattern 154 may be formed to include a nitride such as silicon nitride.

[0091] The first interlayer dielectric may be etched, and then the second insulating layer 122, the first insulating layer 120, and a surface portion of the underlying substrate 100 may be etched to form a third opening 156 exposing the surface of the substrate 100.

[0092] Reference Figure 15 may be made to form a lower contact plug 158 to fill the lower portion of the third opening 156.

[0093] In some example embodiments, a conductive layer may be formed to fill the third opening 156, and then the upper portion of the conductive layer may be removed to form the lower contact plug 158. The conductive layer may include polysilicon doped with impurities. When the conductive layer is formed of a polysilicon layer, the conductive layer may fill the third opening 156 having a high aspect ratio.

[0094] When performing the processes shown in reference Figure 14 and Figure 15 the structures formed in the core / peripheral region II may be maintained. In other words, when performing the processes shown in reference Figure 14 and Figure 15 the core / peripheral region II may be substantially unmodified.

[0095] Reference Figure 16 and Figure 17, an upper spacer 160 can be formed on the upper sidewall of the insulating pattern 154. In the process of forming the upper spacer 160, an upper spacer (not shown) can also be formed on the spacer structure 152.

[0096] A second barrier layer can be formed on the surfaces of the lower contact plug 158, the bit line structure 140, and the upper spacer in the cell region I, and the second capping layer pattern 134a in the core / peripheral region II. The second barrier layer can conform to the surfaces on which it is formed. A second metal layer can be formed on the second barrier layer to fill the spaces between the bit line structures 140 and between the insulating patterns 154.

[0097] The second barrier layer can include, for example, a metal such as titanium (Ti) or tantalum (Ta), and / or a metal nitride such as titanium nitride or tantalum nitride. The second metal layer can include, for example, a metal such as tungsten (W).

[0098] After that, the second metal layer and the second barrier layer can be planarized until the upper surfaces of the bit line structure 140 and the insulating pattern 154 can be exposed. In the planarization process, the second metal layer and the second barrier layer formed in the core / peripheral region II can be completely removed, and the upper part of the second capping layer pattern 134a can be partially removed. In the cell region I, an upper contact plug 162 can be formed on the upper surface of the lower contact plug 158 to fill the third opening.

[0099] The upper contact plug 162 can include a second barrier pattern 161a and a second metal pattern 161b. The second barrier pattern 161a can be formed on the surfaces of the spacer structure 152, the upper spacer 160, and the lower contact plug 158, and the second barrier pattern 161a can conform to the surfaces on which it is formed. Thus, the second barrier pattern 161a can surround the sidewalls and the bottom of the second metal pattern 161b.

[0100] In some example embodiments, the uppermost surface of the upper contact plug 162 can be coplanar with the uppermost surface of the bit line structure 140.

[0101] In some example embodiments, after forming the upper contact plug 162, some of the spacers included in the spacer structure 152 can be removed to form air spacers.

[0102] Reference Figure 18 and Figure 19 , a third capping insulating layer 170 can be formed on the upper contact plug 162, the bit line structure 140, and the second capping layer pattern 134a. A first layer 172 and a second layer 174 are sequentially formed on the third capping insulating layer 170.

[0103] The third capping insulating layer 170 may include silicon nitride. The first layer 172 may include, for example, a spin-on hard mask (SOH). The second layer 174 may include silicon oxynitride.

[0104] The first photoresist layer may be coated on the second layer 174. The first photoresist pattern 176 may be formed by performing a light process on the first photoresist layer. The first photoresist pattern 176 may be used as an etching mask to form a landing pad pattern in the cell region I and a contact plug in the core / periphery region II.

[0105] The landing pad pattern may be formed between the upper contact plug 162 and the capacitor, and the landing pad pattern may be electrically connected to the upper contact plug 162 and the capacitor. The contact plug in the core / periphery region II may be electrically connected to the surface of the substrate 100, or may be electrically connected to the bit line structure 140.

[0106] In a DRAM device, the landing pad pattern may have a size of 20 nm or less and a pitch of 40 nm or less. Therefore, the light process for forming the landing pad pattern may be performed by an EUV exposure process using light having a short wavelength of about 13.5 nm. On the other hand, the arrangement density of the contact plugs may be lower than the arrangement density of the landing pad patterns. Therefore, the contact plugs may be patterned by an exposure process having a lower resolution than the EUV exposure process. For example, the contact plugs may be patterned by an argon fluoride (ArF) immersion exposure process using light having a wavelength of about 193 nm.

[0107] The light process for forming the first photoresist pattern 176 may include an EUV exposure process. The first exposure mask (i.e., reticle) used in the EUV exposure process may include a pattern portion for forming a landing pad pattern in the cell region I and a pattern portion for forming a contact plug in the core / periphery region II, respectively. Therefore, in some example embodiments, the photoresist layer for forming a landing pad pattern in the cell region I and the photoresist layer for forming a contact plug in the core / periphery region II may be simultaneously exposed by a single EUV exposure process using the first exposure mask.

[0108] On the other hand, when forming patterns having a size of about 20 nm or less and a pitch of about 40 nm or less in the cell region I and the core / periphery region II, respectively, it may be difficult to form a photoresist pattern in the cell region I and the core / periphery region II by using a single EUV process. Therefore, a first EUV light process may be performed on the photoresist layer in the cell region I to form a photoresist pattern in the cell region I, and a second EUV light process may be independently performed on the photoresist layer in the core / periphery region II to form a photoresist pattern in the core / periphery region II.

[0109] However, the contact plugs in the core / peripheral region II may have a low layout density and a pitch of 40 nm or greater, such that the first photoresist pattern 176 for forming the landing pad pattern in the cell region I and the contact plugs in the core / peripheral region II can be formed by a single EUV light process. That is, for forming the contact plugs, an independent ArF immersion exposure process may not be performed. Therefore, the number of exposure processes for forming the landing pad pattern in the cell region I and the contact plugs in the core / peripheral region II can be reduced, and the exposure process can be simplified.

[0110] The horizontal in the vertical direction at the bottom of the landing pad pattern in the cell region I may be different from the horizontal in the vertical direction at the bottom of the contact plugs in the core / peripheral region II. As described above, the photoresist pattern for forming the landing pad pattern and the contact plugs in different regions and having different shapes and layout densities can be formed by a single EUV process.

[0111] The first photoresist pattern 176 may include a fourth opening 178a that exposes a part of the landing pad pattern in the cell region I. Additionally, the first photoresist pattern 176 may include a fifth opening 178b that exposes a part of the contact plugs in the core / peripheral region II.

[0112] Reference Figure 20 and Figure 21 , the first photoresist pattern 176 can be used as an etching mask to sequentially etch the second layer 174 and the first layer 172 to form the second pattern and the first pattern.

[0113] After that, the first pattern and the second pattern can be used as etching masks to etch the third capping insulating layer 170 to form the third capping insulating pattern 170a. In the etching process, the second pattern can be removed.

[0114] In the cell region I and the core / peripheral region II, the layer between the third capping insulating patterns 170a can be etched.

[0115] That is, in the cell region I, the upper contact plugs 162, the spacer structures 152, and a part of the bit line structures 140 between the third capping insulating patterns 170a can be partially etched to form a sixth opening 180. The upper sidewalls of the upper contact plugs 162 can be exposed through the sixth opening 180. The sixth opening 180 can be used as a part for forming the landing pad pattern.

[0116] In the core / peripheral region II, the upper portion of the bit line structure 140 between the partial second capping layer pattern 134a and the third capping insulating pattern 170a can be etched to form a preliminary seventh opening 182. Additionally, in the core / peripheral region II, the upper portion of the lower insulating interlayer 132 between the third capping insulating patterns 170a can be etched to form a preliminary seventh opening 182.

[0117] The first pattern can be removed by ashing and / or a stripping process.

[0118] Reference Figure 22 and Figure 23 , a photoresist layer can be coated to cover the third capping insulating pattern 170a, the sixth opening 180, and the seventh preliminary opening 182. Thereafter, a photolithography process can be performed on the photoresist layer to form a photoresist pattern (not shown). The photolithography process can include an exposure process with low resolution and using a long wavelength. For example, the photolithography process can be performed by using a krypton fluoride (KrF) photolithography process of approximately 248 nm.

[0119] The photoresist pattern can cover the entirety of the third capping insulating pattern 170a and the sixth opening 180 in the cell region I. Additionally, the photoresist pattern can expose only a part of the seventh preliminary opening 182 in the core / peripheral region II, and the photoresist pattern can cover the core / peripheral region II outside of a part of the seventh preliminary opening 182.

[0120] Thereafter, the layer below the preliminary seventh opening 182 can be further etched using the photoresist pattern as an etch mask. Accordingly, a seventh opening 182a exposing the first conductive pattern 124a of the bit line structure 140 can be formed in the core / peripheral region II. Additionally, a seventh opening 182a exposing the substrate 100 adjacent to the side surface of the second gate structure 142 can be formed in the core / peripheral region II.

[0121] The photoresist pattern can be removed by ashing and / or a stripping process.

[0122] Reference Figure 24 and Figure 25 , a third layer 186 can be formed on the third capping insulating pattern 170a to fill the sixth opening 180 and the seventh opening 182a. A fourth layer 188 can be sequentially formed on the third layer 186. The third layer 186 can include, for example, a spin-on hard mask. The fourth layer 188 can include silicon oxynitride.

[0123] A second photoresist layer can be coated on the fourth layer 188. A photolithography process can be performed on the second photoresist layer to form a second photoresist pattern 190. The second photoresist pattern 190 can be used as an etch mask for forming wiring in the core / peripheral region II.

[0124] The wiring in the core / peripheral region II may have a size (e.g., line width) of about 20 nm or less and a pitch of about 40 nm or less. Thus, the photolithography process for forming the wiring may be an EUV exposure process using light with a short wavelength such as about 13.5 nm.

[0125] The photolithography process for forming the second photoresist pattern 190 may include an EUV exposure process. The second exposure mask used in the EUV exposure process may include a part of the pattern for forming the wiring in the core / peripheral region II.

[0126] The second photoresist pattern 190 may include an eighth opening 192 that exposes a part of the wiring in the core / peripheral region II. The eighth opening 192 may extend in one direction to have a trench shape. The eighth opening 192 may overlap with a part of the seventh opening 182a. The second photoresist pattern 190 may cover the entirety of the fourth layer 188 in the cell region I.

[0127] Reference Figure 26 and Figure 27 , the fourth layer 188 and the third layer 186 may be sequentially etched using the second photoresist pattern 190 as an etch mask to form a fourth pattern and a third pattern.

[0128] After that, the third capping insulating pattern 170a in the core / peripheral region II may be etched using the third pattern and the fourth pattern as etch masks to form a ninth opening 194. Thus, the ninth opening 194 may extend in one direction to have a trench shape, and the ninth opening 194 may communicate with the seventh opening 182a.

[0129] The third pattern may be removed by an ashing and / or stripping process.

[0130] Thus, the seventh opening 182a and the ninth opening 194 for forming contact plugs and wiring may be formed in the core / peripheral region II. Additionally, a sixth opening 180 for forming a landing pad pattern may be formed in the cell region I.

[0131] As described above, the first photoresist pattern 176 formed by an EUV exposure process may be used to form the sixth opening 180 and the seventh opening 182a. Additionally, the second photoresist pattern 190 formed by an EUV exposure process may be used to form the ninth opening 194. That is, two EUV masks may be used to form the sixth opening 180, the seventh opening 182a, and the ninth opening 194.

[0132] Reference Figure 28 and Figure 29, a third barrier layer 195a may be formed on the surfaces of the third cover insulation pattern 170a, the sixth opening 180, the seventh opening 182a, and the ninth opening 194, and the third barrier layer 195a may be flush with the surfaces on which it is formed. A third metal layer 195b may be formed on the third barrier layer 195a to completely fill the sixth opening 180, the seventh opening 182a, and the ninth opening 194.

[0133] The third barrier layer 195a may be formed to include, for example, metals such as titanium (Ti), tantalum (Ta), etc., and / or metal nitrides such as titanium nitride, tantalum nitride, etc. The third metal layer 195b may be formed to include a metal such as tungsten (W).

[0134] Reference Figure 30 and Figure 31 , the third metal layer 195b and the third barrier layer 195a may be planarized until the upper surface of the third cover insulation pattern 170a is exposed to form a landing pad pattern 198a, a contact plug 198b, and a wiring 198c. The planarization process may include a chemical mechanical polishing process.

[0135] The landing pad pattern 198a may be formed in the sixth opening 180 in the cell region I. The contact plug 198b may be formed in the seventh opening 182a in the core / peripheral region II, and the wiring 198c may be formed in the ninth opening 194 in the core / peripheral region II.

[0136] The landing pad pattern 198a may include a third barrier pattern 196a and a third metal pattern 196b. The third barrier pattern 196a may be formed on the sidewalls and bottom of the sixth opening 180 and may be flush with the surfaces on which it is formed. The third metal pattern 196b may be formed on the third barrier pattern 196a to fill the sixth opening. The lower portion of the landing pad pattern 198a may contact the upper sidewalls of the upper contact plug 162 and the sidewalls of the first cover layer pattern 130a and the second cover layer pattern 134a of the bit line structure 140. Additionally, the upper sidewalls of the upper contact plug 162 and the sidewalls of the first cover layer pattern 130a and the second cover layer pattern 134a of the bit line structure 140 that contact the lower portion of the landing pad pattern 198a may be partially etched to include the etched portions. The third cover insulation pattern 170a may be disposed on the upper sidewalls of the landing pad pattern 198a.

[0137] As described above, the contact plug 198b and the wiring 198c in the core / peripheral region II may be formed by a dual damascene process.

[0138] The contact portion between the contact plug 198b and the wiring 198c may include a third barrier pattern 196a and a third metal pattern 196b. The third barrier pattern 196a may be formed on the surfaces of the seventh opening 182a and the ninth opening 194, and the third barrier pattern 196a may be flush with the surfaces on which it is formed. The third metal pattern 196b may be formed on the third barrier pattern 196a to fill the seventh opening 182a and the ninth opening 194.

[0139] In the contact plug 198b, the first contact plug may contact the first conductive pattern 124a of the bit line structure 140, and the second contact plug may contact the substrate adjacent to the side surface of the second gate structure 142.

[0140] Referring again to Figure 1 and Figure 2 , the capacitor 200 may be formed on the upper surface of the landing pad pattern.

[0141] As described above, a DRAM device may be manufactured.

[0142] Figure 32 is a cross-sectional view showing aspects of a semiconductor device according to some example embodiments.

[0143] Figure 32 is an enlarged cross-sectional view of a part of the landing pad pattern.

[0144] Except for the shape of the upper contact plug, Figure 32 the semiconductor device of Figures 1 to 5 may be substantially the same as or similar to the semiconductor device shown in the reference

[0145] For example, the structure in the core / peripheral region II may be substantially the same as or similar to the structure in the core / peripheral region II of the semiconductor device shown in the reference Figures 1 to 5 Therefore, the same elements are given the same reference numerals and their repeated descriptions are omitted.

[0146] Referring to Figure 32 , the uppermost surface of the upper contact plug 162a may be lower than the uppermost surface of the bit line structure 140. Accordingly, the third capping insulating pattern 170a may be formed on the upper portion of the third opening between the bit line structures 140.

[0147] When the uppermost surface of the upper contact plug 162a is lower than the uppermost surface of the bit line structure 140, electrical short circuit defects between the upper contact plug 162a and other conductive patterns (e.g., adjacent landing pad patterns) may be reduced.

[0148] Figure 33It is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to some example embodiments.

[0149] Figure 33 It is a cross-sectional view taken along Figure 3 lines A-A' and B-B'.

[0150] Referring to Figure 33 , first, a process substantially the same as or similar to the process shown in the reference Figures 6 to 15 can be performed.

[0151] After that, an upper spacer 160 can be formed on the sidewalls of the insulating pattern 154. In the process of forming the upper spacer 160, the upper spacer can be further formed on the spacer structure 152.

[0152] A second barrier layer can be formed on the surfaces of the lower contact plug 158, the bit line structure 140, and the upper spacer 160 in the cell region I and on the surface of the second capping layer pattern 134a in the core / periphery region II. The second barrier layer can conform to the surface on which it is formed. A second metal layer can be formed on the second barrier layer to fill the spaces between the bit line structures 140 and between the insulating patterns 154.

[0153] The second metal layer and the second barrier layer can be planarized until the upper surfaces of the bit line structure 140 and the insulating pattern 154 are exposed. In the planarization process, the upper portion of the second capping layer pattern 134a in the core / periphery region II can be partially removed.

[0154] After that, the second barrier layer and the second metal layer in the third opening can be additionally and partially etched to form an upper contact plug 162a. The upper contact plug 162a can be formed on the upper surface of the lower contact plug 158 in the third opening.

[0155] The upper surface of the upper contact plug 162a can be lower than the upper entrance portion of the third opening. The upper surface of the upper contact plug 162a can be lower than the upper surface of the bit line structure 140. Additionally, the upper space of the third opening can be reserved above the upper contact plug 162a.

[0156] Subsequently, a process similar to or the same as the process shown in the reference Figures 18 to 31 can be performed to form a semiconductor device.

[0157] However, when performing the processes shown in the references Figure 18 and Figure 19 , a third capping insulating layer can be formed on the upper contact plug 162a, the bit line structure 140, and the second capping layer pattern to fill the upper space of the third opening. Thus, in the semiconductor device, the third capping insulating pattern ([Figure 32 The third opening above the upper contact plug 162a can be filled with <170a>.

[0158] Figure 34 is a cross-sectional view showing aspects of a semiconductor device according to some example embodiments.

[0159] Figure 34 is an enlarged cross-sectional view of a part of the landing pad pattern.

[0160] Except for the shape of the upper contact plug, Figure 34 the semiconductor device of Figures 1 to 5 can be substantially the same as or similar to the semiconductor device shown in the reference Figures 1 to 5 For example, the structure in the core / peripheral region II can be substantially the same as or similar to the structure in the core / peripheral region II of the semiconductor device shown in the reference

[0161] Reference Figure 34 shows that a landing pad pattern 214 can be formed on the lower contact plug 158. The upper part of the bit line structure 140 can include an etched portion.

[0162] In some example embodiments, a metal silicide pattern (not shown) can be further formed between the lower contact plug 158 and the landing pad pattern 214.

[0163] The landing pad pattern 214 can be stacked on the lower contact plug 158. The landing pad pattern 214 can be formed on the uppermost surface of the unetched portion of the bit line structure 140.

[0164] The sidewall of the landing pad pattern 214 can have an etched shape. The etched portion of the landing pad pattern 214 and the etched portion of the bit line structure 140 can be used as the recessed portion 216.

[0165] The landing pad pattern 214 can include a second barrier pattern 210a and a second metal pattern 212a. The second barrier pattern 210a can be formed on the surface of the spacer structure 152 and the lower contact plug 158 and the upper surface of the bit line structure 140. The second barrier pattern 210a can be flush with the surface on which it is formed. The second metal pattern 212a can be formed on the upper surface of the second barrier pattern 210a. That is, the second barrier pattern 210a can be formed on the lower surface of the second metal pattern 212a between the recessed portions 216.

[0166] The upper insulating pattern 218 can be formed in the recessed portion 216.

[0167] The landing pad pattern 214 may directly contact the upper surface of the lower contact plug 158.

[0168] Figures 35 to 41 FIG. is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to some example embodiments.

[0169] Figure 35 、 Figure 37 、 Figure 39 and 41 include cross-sectional views taken along lines A-A' and B-B' of Figure 3 while Figure 36 、 Figure 38 and Figure 40 include cross-sectional views taken along lines C-C' and D-D' of Figure 3 .

[0170] Referring to Figure 35 and Figure 36 , first, a process substantially the same as or similar to the process shown in reference Figures 6 to 15 may be performed.

[0171] After that, an upper spacer 160 may be formed on the sidewalls of the insulating pattern 154. In the process of forming the upper spacer, the upper spacer may be further formed on the spacer structure 152.

[0172] A second barrier layer may be formed on the surfaces of the lower contact plug 158, the bit line structure 140, and the upper spacer 160 in the cell region I and on the surface of the second capping layer pattern 134a in the core / periphery region II. A second metal layer may be formed on the second barrier layer to fill the spaces between the bit line structures 140 and between the insulating patterns 154. In some example embodiments, the upper surface of the second metal layer 212 may be higher than the upper surface of the bit line structure 140.

[0173] After that, the second barrier layer 210 and the second metal layer 212 in the core / periphery region II may be removed. Accordingly, the second capping layer pattern 134a may be exposed in the core / periphery region II.

[0174] Referring to Figure 37 and Figure 38 , a third capping insulating layer 170 may be formed on the second metal layer in the cell region I and on the second capping layer pattern in the core / periphery region II. A first layer 172 and a second layer 174 may be sequentially formed on the third capping insulating layer 170.

[0175] The third capping insulating layer 170 may include silicon nitride. The first layer 172 may include, for example, a spin-on hard mask (SOH). The second layer 174 may include silicon oxynitride.

[0176] The first photoresist layer may be coated on the second layer 174. The first photoresist pattern 176a may be formed by performing a light process on the first photoresist layer.

[0177] The first photoresist pattern 176a may be used as an etching mask to form a landing pad pattern in the cell region I and a contact plug in the core / periphery region II.

[0178] The process for forming the first photoresist pattern 176a may be the same as the process Figure 18 and Figure 19 shown. That is, the process for forming the first photoresist pattern 176a may include an EUV light process.

[0179] In some example embodiments, the landing pad pattern may be formed by an emboss process, and the position of the fourth opening 179a of the first photoresist pattern 176a in the cell region I may be different from Figure 18 and Figure 19 that position. The first photoresist pattern 176a may cover a part of the landing pad pattern in the cell region I. Thus, the fourth opening 179a of the first photoresist pattern 176a may expose the part where the landing pad pattern is not formed. The first photoresist pattern 176a may include a fifth opening 178b that exposes a part of the contact plug in the core / periphery region II.

[0180] Reference Figure 39 and Figure 40 may be used to sequentially etch the second layer 174 and the first layer 172 using the first photoresist pattern 176a as an etching mask to form a second pattern and a first pattern.

[0181] After that, the second metal layer, the bit line structure, and the insulating pattern in the cell region I may be etched using the first pattern and the second pattern as etching masks to form a landing pad pattern 214. The landing pad pattern 214 may be formed on the lower contact plug. In addition, a recessed portion 216 may be formed between the landing pad patterns 214. The landing pad pattern 214 may have a structure including a stacked second barrier pattern 210a and a second metal pattern 212a. The second barrier pattern 210a may be formed on the lower surface of the second metal pattern 212a between the recessed portions.

[0182] In addition, the upper part of the second capping layer pattern and the bit line structure in the core / periphery region II may be etched using the first pattern and the second pattern as etching masks to form a seventh preliminary opening. The upper part of the second capping layer pattern and the lower insulating interlayer 132 in the core / periphery region II may be etched to form a seventh preliminary opening.

[0183] After that, the process may be performed as in reference Figure 22and Figure 23 a process that is substantially the same as or similar to the process shown, such that the layer below the seventh preliminary opening can be further etched to form the seventh opening 182a. The seventh opening 182a exposing the first conductive pattern 124a of the bit line structure 140 can be formed in the core / peripheral region II. Additionally, the seventh opening 182a exposing the substrate 100 adjacent to the side surface of the second gate structure 142 can be formed in the core / peripheral region II.

[0184] Referring Figure 41 to, an upper insulating pattern 218 can be formed to fill the recessed portion 216 in the cell region I.

[0185] After that, a process substantially the same as or similar to the process referring Figures 24 to 31 and Figure 1 and Figure 2 shown can be executed.

[0186] In some example embodiments, the landing pad pattern 214 in the cell region I can be formed by an imprint process, and then, the contact plugs and wirings in the core / peripheral region II can be formed by a dual damascene process.

[0187] Accordingly, by executing the process referring Figure 28 and Figure 29 shown, a third barrier layer and a third metal layer can be formed on the landing pad pattern 214 and the upper insulating pattern 218 in the cell region I. In the planarization process referring Figure 30 and Figure 31 shown, the third barrier layer and the third metal layer in the cell region I can be completely removed. In some example embodiments, the third barrier layer and the third metal layer in the cell region I can be further removed.

[0188] As described above, a semiconductor device including a landing pad pattern 216 as Figure 34 shown can be manufactured.

[0189] Figure 42 and Figure 43 are cross-sectional views showing aspects of a semiconductor device according to some example embodiments.

[0190] Figure 42 is an enlarged cross-sectional view of a part of a transistor in the core / peripheral region II. Figure 43 is an enlarged cross-sectional view of a part of a bit line structure in the cell region I and the core / peripheral region II.

[0191] Except for the contact plugs and wirings in the core / peripheral region II, the semiconductor device can be the same as the reference Figures 1 to 5The semiconductor devices shown are substantially the same or similar. For example, the structure in cell region I may be substantially the same or similar to the structure in cell region I of the semiconductor device shown in the reference Figures 1 to 5 Thus, the same elements are given the same reference numerals and their repeated description is omitted.

[0192] Referring to Figure 42 and Figure 43 , the contact plug 198b in the core / periphery region II may include a first contact plug (refer to Figure 42 ) and a second contact plug (refer to Figure 43 ).

[0193] The first contact plug may pass through the third capping insulating pattern 170a, the second capping pattern 134a, and the lower insulating interlayer, and the first contact plug may contact the surface of the substrate 100. The second contact plug may contact the first conductive pattern 124a of the bit line structure 140 through the third capping insulating pattern 170a and the upper portion of the bit line structure 140.

[0194] The upper surface of the contact plug 198b may be coplanar with the upper surface of the third capping insulating pattern 170a.

[0195] The wiring 234 may be formed on the contact plug 198b. The upper surface of the wiring 234 may be higher than the upper surface of the third capping insulating pattern 170a. The wiring 234 may have a structure including a fourth barrier pattern 230a and a fourth metal pattern 232a stacked in the vertical direction.

[0196] Figures 44 to 47 is a cross-sectional view showing aspects of a method of manufacturing a semiconductor device according to some example embodiments.

[0197] Figure 44 and Figure 46 are cross-sectional views taken along lines A-A' and B-B' of Figure 3 , while Figure 45 and Figure 47 are cross-sectional views taken along lines C-C' and D-D' of Figure 3 .

[0198] Referring to Figure 44 and Figure 45 , first, a process substantially the same or similar to the process shown in the reference Figures 6 to 23 may be performed.

[0199] After that, a third barrier layer may be formed on the surfaces of the third capping insulating pattern 170a, the sixth opening 180, and the seventh opening 182a, and the third barrier layer may be flush with the surfaces on which it is formed. A third metal layer may be formed on the third barrier layer to completely fill the sixth opening 180 and the seventh opening 182a.​

[0200] The third metal layer and the third barrier layer may be planarized until the upper surface of the third capping insulating pattern 170a is exposed to form a landing pad pattern and a contact plug. The planarization process may include a chemical mechanical polishing process.

[0201] The landing pad pattern 198a may be formed in the sixth opening 180 in the cell region I. The contact plug 198b may be formed in the seventh opening 182a in the core / periphery region II. Each of the landing pad pattern 198a and the contact plug 198b may include a third barrier pattern 196a and a third metal pattern 196b.

[0202] Reference Figure 46 and Figure 47 , a fourth barrier layer and a fourth metal layer may be sequentially formed on the third capping insulating pattern 170a, the landing pad pattern, and the contact plug.

[0203] A third layer and a fourth layer may be sequentially formed on the fourth metal layer. The third layer may include, for example, a spin-on hard mask. The fourth layer may include silicon oxynitride.

[0204] A second photoresist layer may be coated on the fourth layer. A photolithography process may be performed on the second photoresist layer to form a second photoresist pattern. The second photoresist pattern may be used as an etching mask to form a wiring in the core / periphery region II by an imprint process. Accordingly, the second photoresist pattern may selectively cover a part of the wiring. The photolithography process for forming the second photoresist pattern may include an EUV exposure process.

[0205] Thereafter, the fourth metal layer and the fourth barrier layer may be etched using the second photoresist pattern as an etching mask to form a wiring. The wiring 234 may be formed on the third capping insulating pattern 170a and the contact plug 198b in the core / periphery region II. The wiring 234 may include a fourth barrier pattern 230a and a fourth metal pattern 232a. The fourth barrier pattern 230a may be formed on the bottom of the fourth metal pattern 232a.

[0206] As described above, when manufacturing a semiconductor device, the landing pad pattern in the cell region I and the contact plug in the core / periphery region II may be formed through a single EUV exposure process. Accordingly, the semiconductor device may be manufactured through a process with a reduced number of operations.

[0207] The foregoing is a description of example embodiments and should not be construed as a limitation thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined by the claims.

Claims

1. A semiconductor device, comprising: a substrate including a cell region and a core / peripheral region; a plurality of bit line structures in the cell region of the substrate; gate structures in the core / peripheral region of the substrate; lower contact plugs and upper contact plugs between the bit line structures, the lower contact plugs and the upper contact plugs being stacked in a vertical direction; landing pad patterns in contact with upper sidewalls of the upper contact plugs, the landing pad patterns being between an upper portion of the upper contact plugs and an upper portion of a first bit line structure among the plurality of bit line structures, wherein an upper surface of the landing pad patterns is higher than an upper surface of each of the bit line structures; and peripheral contact plugs in the core / peripheral region of the substrate; and wiring electrically connected to an upper surface of the peripheral contact plugs; wherein the upper surface of the landing pad patterns and the upper surface of the wiring are coplanar with each other.

2. The semiconductor device according to claim 1, further comprising: a cover insulating pattern on the plurality of bit line structures and the upper contact plugs, and the cover insulating pattern filling a space between the plurality of landing pad patterns.

3. The semiconductor device according to claim 2, wherein, The cover insulating pattern is on the gate structures in the core / peripheral region, and the wiring is formed in each of openings included in the cover insulating pattern.

4. The semiconductor device according to claim 1, wherein Bottoms of the landing pad patterns, the peripheral contact plugs, and the wiring are positioned at different vertical heights.

5. The semiconductor device according to claim 1, wherein, The landing pad patterns, the peripheral contact plugs, and the wiring include the same barrier pattern and the same metal pattern.

6. The semiconductor device according to claim 1, wherein, A conductive material of the lower contact plugs is different from a conductive material of the upper contact plugs.

7. The semiconductor device according to claim 6, wherein, The lower contact plugs include polysilicon doped with impurities, and wherein the upper contact plugs include a metal.

8. The semiconductor device according to claim 1, wherein A topmost surface of the upper contact plugs is coplanar with a topmost surface of the bit line structures.

9. The semiconductor device according to claim 1, wherein, A topmost surface of the upper contact plugs is lower than a topmost surface of the bit line structures.

10. The semiconductor device according to claim 1, wherein, The bit line structures include a conductive pattern, a metal pattern, and a cover pattern stacked in sequence, and wherein the landing pad patterns are in contact with the cover patterns.

11. The semiconductor device according to claim 1, wherein, The peripheral contact plugs include a first contact plug and a second contact plug, and wherein the first contact plug contacts the substrate adjacent to the gate structures, and the second contact plug is electrically connected to the conductive pattern included in the bit line structures.

12. The semiconductor device according to claim 1, further comprising: a cell gate structure below an upper surface of the substrate; and a capacitor electrically connected to the landing pad patterns.

13. The semiconductor device according to claim 1, wherein, Each of the landing pad patterns and the wiring has a size of less than 20 nm and a pitch of less than 40 nm.

14. The semiconductor device according to claim 1, wherein, An arrangement density of the peripheral contact plugs is lower than an arrangement density of the landing pad patterns and lower than an arrangement density of the wiring.

15. A semiconductor device, comprising: a substrate including a cell region and a core / peripheral region; a first gate structure in the substrate, the first gate structure being below an upper surface of the substrate; a plurality of bit line structures in the cell region of the substrate; a second gate structure in the core / peripheral region of the substrate; Lower contact plugs and upper contact plugs between the bit line structures, the lower contact plugs and the upper contact plugs being stacked in a vertical direction; A capping insulating pattern on the bit line structures, the upper contact plugs, and the second gate structure; A landing pad pattern in contact with an upper sidewall of the upper contact plug, wherein the landing pad pattern is at a recessed portion of an upper portion of the upper contact plug and an upper portion of one of the bit line structures, and wherein an upper surface of the landing pad pattern is higher than an upper surface of each of the bit line structures; A wiring in a first opening of the capping insulating pattern in the core / peripheral region; A contact plug in a second opening communicating with the first opening, the contact plug being electrically connected to the wiring and below the wiring; and A capacitor electrically connected to the landing pad pattern, wherein the landing pad pattern, the contact plug, and the wiring comprise the same metal.

16. The semiconductor device according to claim 15, wherein, The upper surface of the landing pad pattern and the upper surface of the wiring are coplanar with each other.

17. The semiconductor device according to claim 15, wherein, Bottoms of the landing pad pattern, the contact plug, and the wiring are positioned at different vertical heights.

18. A semiconductor device, comprising: A substrate including a cell region and a core / peripheral region; A conductive structure in the cell region of the substrate; A gate structure in the core / peripheral region of the substrate; Cell contact plugs between the conductive structures; A landing pad pattern electrically connected to the cell contact plugs, and wherein an upper surface of the landing pad pattern is higher than an upper surface of each of the conductive structures; An insulating layer covering the core / peripheral region of the substrate; and Contact plugs and a wiring in an opening included in the insulating layer, wherein an upper surface of the wiring is coplanar with an upper surface of the insulating layer.

19. The semiconductor device according to claim 18, wherein, The insulating layer is between a plurality of landing pad patterns, and each of the landing pad patterns is in a recessed portion exposing a sidewall of the cell contact plug through the insulating layer.

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