memory

Abstract

The present application provides a memory. The memory is provided with isolation pillars of different heights, for example, a first isolation pillar of a higher height is arranged for the two node contact portions arranged at the edge and adjacent to each other, the height of the isolation pillar is lowered for the node contact portions inside the memory area, and the isolation pillars of different heights can be arranged in the peripheral area.

Description

[0001] Related information of divisional application

[0002] The present application is a divisional application of parent application No. CN202010072104.9, filed on February 21, 2020, entitled “Memory and Forming Method Thereof”. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor, in particular to a memory. BACKGROUND

[0004] The memory, such as dynamic random access memory (DRAM), generally has a memory cell array, which includes a plurality of memory cells arranged in an array. The memory also includes a storage capacitor for storing electric charges representing storage information, and the memory cell can be electrically connected to the storage capacitor through a node contact, thereby realizing the storage function of each memory cell. However, the structure of the current memory still needs to be further optimized. SUMMARY

[0005] The present application aims to provide a memory to optimize the structure of the memory.

[0006] To solve the above technical problems, the present application provides a memory, comprising:

[0007] a substrate, wherein a memory region and a peripheral region are defined on the substrate, and the peripheral region is located outside the memory region;

[0008] a plurality of isolation columns formed on the substrate and defining a plurality of node contact windows in the memory region on the substrate; and

[0009] a plurality of node contacts, wherein the node contacts fill the node contact windows;

[0010] The isolation columns for spacing adjacent node contacts include first isolation columns and second isolation columns, and the isolation columns formed in the peripheral region constitute third isolation columns, the top surface of the first isolation columns is higher than the top surface of the second isolation columns, the top surface of the second isolation columns is higher than the top surface of at least part of the third isolation columns, and the first isolation columns, the second isolation columns and the third isolation columns are composed of the same material.

[0011] Optionally, in the third isolation columns in the peripheral region, the top surface of a part of the third isolation columns is flush with the top surface of the first isolation columns.

[0012] Optionally, a part of the top surface of the third isolation column in the peripheral region is flush with the top surface of the second isolation column.

[0013] Optionally, an insulating filling column is arranged between adjacent third isolation columns.

[0014] Optionally, the memory further comprises an electrically conductive layer formed on at least a part of the third isolation column, wherein the top surface of the part of the third isolation column covered by the electrically conductive layer is flush with the top surface of the first isolation column.

[0015] Optionally, the top surface of the second isolation column is lower than the top surface of the node contact portion.

[0016] Optionally, the memory further comprises a first shielding layer filled between adjacent independent contact portions and arranged on the second isolation column.

[0017] The application further provides another memory, comprising:

[0018] a substrate, wherein a memory region and a peripheral region are defined on the substrate, and the peripheral region is located outside the memory region;

[0019] a plurality of isolation columns formed on the substrate, comprising first isolation columns with a first height, second isolation columns with a second height, and third isolation columns with a third height, wherein the first isolation columns, the second isolation columns, and the third isolation columns are composed of the same material, and the first height is higher than the second height, and the second height is higher than the third height.

[0020] Optionally, the first isolation columns are located in the memory region.

[0021] Optionally, the second isolation columns are located in the memory region, and the third isolation columns are located in the peripheral region.

[0022] Optionally, the first isolation columns and the second isolation columns define a plurality of node contact windows in the memory region, and the memory further comprises a plurality of node contact portions filled in the node contact windows and arranged in a plurality of rows, and each row is filled with two node contact portions at the edge and connected to each other, the two node contact portions connected to each other constitute a combined contact portion, and the isolation column spaced between the two node contact portions in the combined contact portion constitutes a first isolation column.

[0023] Optionally, the node contact portions in the plurality of node contact portions located on the side of the combined contact portion away from the peripheral region constitute independent contact portions, the isolation column spaced between adjacent independent contact portions constitutes a second isolation column, and a first shielding layer is further formed on the top surface of the second isolation column.

[0024] Optionally, two node contact portions in the combination contact portion are connected at the top of the first isolation column and cover the top surface of the first isolation column.

[0025] Optionally, the top of the third isolation column is further covered with a passivation layer.

[0026] Optionally, an electrically conductive layer is further formed on part of the third isolation column, and the passivation layer covers the electrically conductive layer.

[0027] Optionally, an insulating filling column is arranged between adjacent third isolation columns.

[0028] In the memory provided by the present application, by arranging isolation columns with different heights, the device structure of the memory is optimized. For example, a higher first isolation column is arranged between two node contact portions arranged at the edge and adjacent to each other, the height of the isolation column is reduced for node contact portions inside the memory area, and isolation columns with different heights can be arranged in the peripheral area. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1a A cross-sectional view of the memory in Embodiment One of the present application, which is formed with isolation columns and node contact portions;

[0030] Figure 1b A cross-sectional view of the memory in Embodiment One of the present application, which is formed with a shielding layer;

[0031] Figure 2 A flowchart of the forming method of the memory in Embodiment One of the present application;

[0032] Figures 3a to 3e A structure diagram of the memory in Embodiment One of the present application in the preparation process thereof;

[0033] Figure 4 A structure diagram of the memory in Embodiment Two of the present application;

[0034] Figure 5 A structure diagram of the memory in Embodiment Three of the present application.

[0035] Wherein, the reference signs are as follows:

[0036] 100 - substrate;

[0037] 100A - memory area;

[0038] 100B - peripheral area;

[0039] 110 - first trench isolation structure;

[0040] 120 - second trench isolation structure;

[0041] 210 - combined contact;

[0042] 220 - independent contact;

[0043] 200a - first conductive layer;

[0044] 200b - second conductive layer;

[0045] 200c - third conductive layer;

[0046] 300 - isolation pillar;

[0047] 310 - first isolation pillar;

[0048] 320 - second isolation pillar;

[0049] 330 - third isolation pillar;

[0050] 400 - insulating fill pillar;

[0051] 510 - first masking layer;

[0052] 520 - second masking layer;

[0053] 520' - isolation sidewall;

[0054] 530' - insulating film layer;

[0055] 610 - combined contact window;

[0056] 620 - independent contact;

[0057] 630 - peripheral contact;

[0058] 710 - first pattern;

[0059] 720 - second pattern;

[0060] 730 - third pattern;

[0061] 800 - conductive material layer;

[0062] 900 - passivation layer. DETAILED DESCRIPTION

[0063] The memory and its forming method according to the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are in a very simplified form and all use non-precise proportions, only for the purpose of facilitating and clarifying the purpose of assisting the description of the embodiments of the present application.

[0064] Figure 1a is a cross-sectional schematic view of the memory in the first embodiment of the present application, which is formed with an isolation pillar and a node contact, Figure 1bFIG1 is a cross-sectional diagram of a memory device according to the first embodiment of the present invention having a shielding layer formed thereon. Figure 1a and Figure 1b As shown, the memory includes: a substrate 100, a plurality of isolation pillars 300 formed on the substrate 100, and a plurality of node contacts.

[0065] Specifically, multiple active areas are formed in the substrate 100. These active areas are arranged in an array, for example. Adjacent active areas can be separated from each other by a first trench isolation structure 110. Memory cells are formed on these active areas. The active areas arranged at the edge constitute a first active area AA1, and the active areas surrounded by the first active area AA1 constitute a second active area AA2.

[0066] It should be noted that due to the limitations of existing semiconductor manufacturing processes, it is easy for the active areas arranged at the edge positions among the multiple active areas formed (for example, the first active area AA1) to have lower quality. If memory cells are further prepared on the low-quality active areas, the device performance of the memory cells formed based on the active areas at the edge positions will be affected, so that the memory cells with performance defects need to be scrapped, which will inevitably lead to a waste of costs.

[0067] Based on this, in this embodiment, at least the active area located at the edge can be defined as a non-functional active area, which is not used to form a memory cell. That is, the non-functional active area includes the first active area AA1. Furthermore, at least a portion of the second active area AA2 surrounded by the first active area AA1 is defined as a functional active area, which is used to form an effective memory cell.

[0068] Continue to refer Figure 1a As shown, in this embodiment, a memory region 100A and a peripheral region 100B located outside the memory region 100A are defined on the substrate 100, and the multiple active regions are formed in the memory region 100A. A second trench isolation structure 120 is formed in the region where the peripheral region 100B connects to the memory region 100A to isolate the semiconductor devices in the memory region 100A from the semiconductor devices in the peripheral region 100B. It should be noted that the first active region AA1, which is arranged at an edge position among the multiple active regions, is correspondingly close to the peripheral region 100B.

[0069] It can be considered that the active area closest to the peripheral area 100B among the multiple active areas constitutes the first active area AA1, and the active area located on the side of the first active area AA1 away from the peripheral area 100B among the multiple active areas constitutes the second active area AA2.

[0070] Continue to referFigure 1a As shown, a plurality of isolation columns 300 are formed on the substrate 100 and located in the memory region 100A, for defining a plurality of node contact windows on the substrate 100, and the plurality of node contact windows are arranged in multiple rows in a predetermined direction. It can be considered that the plurality of isolation columns 300 include isolation columns extending in a first direction and isolation columns extending in a second direction, and the node contact windows can be surrounded by the isolation columns extending in different directions.

[0071] Further, the isolation columns extending in the first direction and the isolation columns extending in the second direction in the plurality of isolation columns 300 are, for example, perpendicular to each other, so that the plurality of node contact windows defined thereby are arranged in alignment in both the first direction and the second direction. At this time, it can be considered that the plurality of node contact windows are arranged in multiple rows in both the first direction and the second direction.

[0072] Continuing to refer to Figure 1a As shown, the node contact portions fill the node contact windows and are arranged in multiple rows accordingly, and the node contact portions are electrically connected to the corresponding active regions. Among each row of node contact portions, two node contact portions filling the two node contact windows at the edge and adjacent to each other are connected to each other.

[0073] As described above, in the embodiment, at least the active regions located at the edge are defined as non-functional active regions, and at this time, the node contact portions located at the edge and connected to the non-functional active regions can also be defined as non-functional contact portions accordingly. Therefore, even if the two node contact portions at the edge are connected to each other, the device performance of the entire memory will not be affected.

[0074] In the embodiment, the two node contact portions filling the two node contact windows at the edge in each row and connected to each other are defined as a combined contact portion 210, and the node contact portions in each row located on the side of the combined contact portion 210 away from the peripheral region 100B are defined as independent contact portions 220, and each of the independent contact portions 220 fills one node contact window.

[0075] That is, the combined contact portion 210 composed of the node contact portions connected to each other has a width dimension larger than that of the independent contact portion 220. For example, the width dimension D1 of the combined contact portion 210 can be greater than 2 times the width dimension D2 of the independent contact portion 220 (i.e., D1>2*D2).

[0076] It should be noted that in the conventional process, when the same conductive material layer is patterned to divide the conductive material layer to form the node contact portions disconnected from each other, the node contact portions located at the edge positions are usually subjected to a greater etching attack, which can cause the node contact portions at the edge positions to be easily eroded and deformed. Based on this, in the present embodiment, the active regions at the edge positions are defined as non-functional active regions, and the node contact portions at the edge positions are connected to each other to form the combined contact portion 210 with a larger size. In this way, even if the combined contact portion 210 is subjected to a greater etching attack, the topography of the combined contact portion 210 can still be guaranteed. Moreover, under the blocking protection of the combined contact portion 210 with a larger width size, the problem of the independent contact portion 220 adjacent to the combined contact portion 210 being excessively eroded can also be effectively alleviated.

[0077] Further, the node contact portion includes a first conductive layer 200a, a second conductive layer 200b, and a third conductive layer 200c. The first conductive layer 200a fills the bottom of the node contact window, the second conductive layer 200b is located between the first conductive layer 200a and the third conductive layer 200c, and covers the bottom surface and at least part of the sidewall of the third conductive layer 200c.

[0078] It should be noted that the node contact window is surrounded by the isolation column 300, and the corresponding spacing between adjacent node contact portions is the isolation column 300. Specifically, the isolation column 300 between the two node contact portions in the combined contact portion 210 constitutes a first isolation column 310, and the two node contact portions in the combined contact portion 210 cover the first isolation column 310 and are connected to each other on the top surface of the first isolation column 310. In the present embodiment, in the combined contact portion 210, the two second conductive layers 200b of the two node contact portions are connected to each other on the top surface of the first isolation column 310, and the two third conductive layers 200c of the two node contact portions are connected to each other above the first isolation column 310.

[0079] In addition, the isolation column 300 between adjacent independent contact portions 220 constitutes a second isolation column 320, and the top surface of the second isolation column 320 is lower than the top surface of the independent contact portion 220. In the present embodiment, the top surface of the second isolation column 320 is also lower than the top surface of the first isolation column 310.

[0080] In combination Figure 1a and Figure 1bAs shown, in the embodiment, the top surfaces of the independent contact portions 220 and the combined contact portion 210 are flush, and at this time, the independent contact portions 220 and the combined contact portion 210 are both protruded relative to the second isolation columns 320. Based on this, the memory in the embodiment further includes a first shielding layer 510, which at least fills between adjacent independent contact portions 220 and is located on the second isolation columns 320. Further, the first shielding layer 510 is also spaced between the independent contact portions 220 and the combined contact portion 210.

[0081] In addition, the isolation columns 300 can further be formed in the peripheral region 100B and constitute third isolation columns 330, and at this time, for example, a peripheral contact window can be defined in the peripheral region 100B. In addition, the peripheral contact window is filled with insulating filling columns 400, in other words, the insulating filling columns 400 are spaced between adjacent third isolation columns 330.

[0082] In an optional solution, the memory further includes an electrically conductive layer 230, which is at least formed on part of the third isolation columns 330. The top surface of the part of the third isolation columns 330 covered by the electrically conductive layer 230 is higher than the top surface of another part of the third isolation columns 330 not covered by the electrically conductive layer 230. In the embodiment, the electrically conductive layer 230 covers the top surface of the third isolation columns 330 and also extends to cover the adjacent insulating contact columns 400, and the top surfaces of the third isolation columns and the insulating contact columns covered by the electrically conductive layer 230 are all higher than the top surfaces of the third isolation columns and the insulating contact columns not covered by the electrically conductive layer 230.

[0083] In the embodiment, the electrically conductive layer 230 closest to the memory region 100A and the combined contact portion 210 are spaced from each other, and the top surfaces of the third isolation columns 330 and the insulating filling columns 400 located between the electrically conductive layer 230 and the combined contact portion 210 are more sunken relative to the top surface of the node contact portion, so as to define a groove between the electrically conductive layer 230 and the combined contact portion 210. More specifically, the top surfaces of the third isolation columns 330 and the insulating filling columns 400 located between the electrically conductive layer 230 and the combined contact portion 210 are more sunken relative to the top surfaces of the third isolation columns 330 and the insulating filling columns 400 covered by the electrically conductive layer 230.

[0084] It should be noted that the number of third isolation columns 330 and the number of insulating filling columns 400 between the electrically conductive layer 230 and the combined contact portion 210 can be adjusted according to actual conditions (i.e., the number of third isolation columns 330 and the number of insulating filling columns 400 in the groove can be adjusted according to actual conditions). For example, in the embodiment, there are two third isolation columns 330 and two insulating filling columns 400 between the electrically conductive layer 230 and the combined contact portion 210. In addition, the number of third isolation columns and insulating filling columns covered by the electrically conductive layer 230 can also be adjusted to one or more. In the embodiment, the electrically conductive layer 230 is covered by two third isolation columns and one insulating filling column.

[0085] Specifically, the top surface of the third isolation column 330 and the insulating contact column 400 not covered by the electrically conductive layer 230 can be flush with the top surface of the second isolation column 320, for example. In addition, the top surface of the third isolation column 330 and the insulating contact column 400 covered by the electrically conductive layer 230 can be flush with the top surface of the first isolation column 310, for example.

[0086] Continuing to refer to Figure 1a and Figure 1b As shown, the electrically conductive layer 230 includes a first electrically conductive layer and a second electrically conductive layer, which are arranged in a stack from top to bottom on the third isolation column 330 and the insulating filling column 400.

[0087] Among them, the second conductive layer 300b and the third conductive layer 300c in the electrically conductive layer 230 and the node contact portion can be based on the same conductive material layer and be prepared at the same time by using a patterning process. The formation method of the electrically conductive layer 230 and the node contact portion will be described in detail below.

[0088] Continuing to refer to Figure 1b As shown, the memory further includes a second shielding layer 520, which is filled at least in the groove between the electrically conductive layer 230 and the combined contact portion 210.

[0089] In a further scheme, a plurality of electrically conductive layers 230 can be formed in the peripheral region 100B, and the height of the third isolation column 330 and the insulating filling column 400 between adjacent electrically conductive layers 230 is also correspondingly lower. Based on this, the second shielding layer 520 is also filled between adjacent electrically conductive layers 230.

[0090] The following will be described in conjunction with the accompanying Figure 2 and Figures 3a to 3eThe method for forming the memory as described above in the embodiment is explained in detail. Wherein, Figure 2 The flow chart of the method for forming the memory in the first embodiment of the present application, Figures 3a to 3e The structural schematic diagram of the memory in the first embodiment of the present application during its preparation process.

[0091] In step S100, referring to Figure 3a illustrated, a substrate 100 is provided, and the substrate 100 is defined with a memory area 100A and a peripheral area 100B, and the peripheral area 100B is located outside the memory area 100A.

[0092] Specifically, a plurality of active areas are formed in the memory area 100A of the substrate 100, and the adjacent active areas are separated from each other by, for example, a first trench isolation structure 110. Wherein, the active area arranged at the edge position in the plurality of active areas constitutes a first active area AA1, and the active area located away from the peripheral area on the side of the first active area AA1 constitutes a second active area AA2.

[0093] In the embodiment, the active area arranged at the edge position can be defined as a non-functional active area, and the non-functional active area is not used to form a memory cell, that is, the non-functional active area includes the first active area AA1. And the second active area AA2 surrounded by the first active area AA1 is at least partially defined as a functional active area for forming a memory cell.

[0094] Further, a second trench isolation structure 120 can also be formed in the substrate outside the active area array, so that the active area array in the memory area 100A can be isolated from the devices in the peripheral area 100B.

[0095] In step S200, continuing to refer to Figure 3a illustrated, a plurality of isolation columns 300 are formed on the substrate 100, and a plurality of node contact windows are defined on the substrate 100, and the plurality of node contact windows are arranged in alignment in a predetermined direction and form multiple rows. In the embodiment, the plurality of node contact windows are formed in the memory area 100A.

[0096] As described above, the plurality of isolation columns 300 can include a part of isolation columns extending along a first direction and another part of isolation columns extending along a second direction, and then the plurality of node contact windows can be surrounded by the isolation columns intersecting in different directions. Wherein, the isolation columns extending along the first direction and the isolation columns extending along the second direction are, for example, perpendicular to each other, so that the plurality of node contact windows defined can be arranged in alignment in the first direction and the second direction. At this time, it can be considered that the plurality of node contact windows are arranged in multiple rows in the first direction and the second direction.

[0097] In this embodiment, the two node contact windows located at the edge and adjacent to each other in each row are jointly defined as a combined contact window 610, and the node contact window located away from the peripheral area 100B in each row is defined as an independent contact window 620.

[0098] With reference to Figure 3a As shown, a plurality of isolation columns 300 are formed in the memory area 100A to define the node contact windows (including the combined contact window 610 and the independent contact window 620) in the memory area 100A, and the isolation columns 300 are also formed in the peripheral area 100B to define the peripheral contact window 630 in the peripheral area 100B. In addition, in this step, the top surfaces of the plurality of isolation columns 300 (including the isolation columns formed in the memory area 100A and the isolation columns formed in the peripheral area 100B) are flush.

[0099] In a further aspect, with reference to Figure 3b As shown, the peripheral contact window 630 is also filled with an insulating filling column 400.

[0100] In this embodiment, after the node contact windows are defined, the bottom of the node contact window is further etched to further extend the bottom of the node contact window into the active area of the substrate 100.

[0101] In step S300, with reference to Figures 3c to 3d As shown, a plurality of node contact portions are formed, the node contact portions fill the node contact windows and are arranged in multiple rows, and the two node contact portions filling the two node contact windows located at the edge and adjacent to each other in each row are connected to each other.

[0102] In this embodiment, the two node contact portions filling the two node contact windows located at the edge and adjacent to each other in each row are jointly defined as a combined contact portion 210, and the node contact portion located away from the peripheral area 100B in each row is defined as an independent contact portion 220, and each of the independent contact portions 220 fills one node contact window. It can also be understood that the two node contact portions filled in the combined contact window 610 are connected to each other to form the combined contact portion 210, and the node contact portions filled in the independent contact window 620 form the independent contact portion 220.

[0103] With reference to Figure 3dAs shown, the node contact portion includes a first conductive layer 200a, a second conductive layer 200b and a third conductive layer 200c. The first conductive layer 200a fills the bottom of the node contact window to electrically connect with the active region. The second conductive layer 200b covers the top surface of the first conductive layer 200a and the sidewall of the node contact window. The third conductive layer 200c is formed on the second conductive layer 200b and fills the node contact window, and the third conductive layer 200c also extends upward out of the node contact window to protrude from the node contact window.

[0104] Specifically, the method for forming the node contact portion includes the following steps.

[0105] The first step, with reference to Figure 3c As shown, the first conductive layer 200a is formed at the bottom of the node contact window. The material of the first conductive layer 200a includes, for example, polysilicon.

[0106] The second step, with reference to Figure 3c As shown, the conductive material layer 800 is formed to fill the node contact window and cover the top surface of the isolation column 300. In this embodiment, the conductive material layer 800 is not only formed in the memory region 100A, but also formed in the peripheral region 100B to cover the isolation column 300 and the insulating filling column 400 in the peripheral region 100B.

[0107] The conductive material layer 800 specifically includes a lower conductive material layer and an upper conductive material layer stacked one above the other. The material of the lower conductive material layer includes, for example, titanium nitride, and the upper conductive material layer is, for example, a metal layer, and the material of the metal layer can further include tungsten.

[0108] In this embodiment, the conductive material layer 800 can be a planarized film layer to utilize the subsequent patterning precision of the conductive material layer 800.

[0109] The third step, with reference to Figure 3c As shown, the patterned mask layer is formed on the conductive material layer 800. The patterned mask layer is, for example, a patterned photoresist layer.

[0110] Specifically, the patterned mask layer includes at least a first pattern 710 and a second pattern 720. Both the first pattern 710 and the second pattern 720 are formed in the memory region 100A. The first pattern 710 covers the combined contact window to define the pattern of the combined contact portion. The first pattern 710 also covers the isolation pillar 300 between the two node contact windows in the combined contact window. Furthermore, the second pattern 720 covers the independent contact window to define the pattern of the independent contact portion.

[0111] Furthermore, the width of the first graphic 710 is correspondingly greater than the width of the second graphic 720 (for example, the width of the first graphic 710 is greater than twice the width of the second graphic 720 ).

[0112] It should be noted that when forming a patterned mask layer, the first pattern 710 at the edge may also be overdeveloped, thereby affecting the pattern accuracy of the first pattern 710. To address this issue, in this embodiment, the width of the first pattern 710 is made larger than the width of the second pattern 720. This ensures that the first pattern 710 still meets the dimensional requirements even after overdevelopment. Furthermore, the protection provided by the larger width of the first pattern 710 prevents overdevelopment of the second pattern 720, thereby ensuring the pattern accuracy of the second pattern 720.

[0113] In an optional solution, the patterned mask layer further includes a third pattern 730 , and the third pattern 730 is formed in the peripheral area 100B to define a pattern of an electrically conductive layer in the peripheral area 100B.

[0114] Step 4, specific reference Figure 3d As shown, the conductive material layer 800 is etched using the patterned mask layer as a mask, so that the conductive material layer corresponding to the contact windows of different nodes is separated from each other, thereby forming a combined contact portion 210 and an independent contact portion 220 separated from each other. At this time, the width dimension of the combined contact portion 210 is correspondingly larger than the width dimension of the independent contact portion 220. For example, the width dimension D1 of the combined contact portion 210 can be larger than the width dimension D2 of the independent contact portion 220 (i.e., D1>2*D2).

[0115] Similarly, when etching the conductive material layer 800, the node contact portions located at the edge position will be subjected to a greater etching attack, thereby causing the node contact portions at the edge position to be easily eroded and deformed. Based on this, in the embodiment, two node contact portions located at the edge position and adjacent to each other are connected to each other to form a combined contact portion 210 with a larger size. In this way, even if the combined contact portion 210 is subjected to a greater etching attack, the topography of the combined contact portion 210 can still be guaranteed. Moreover, under the blocking protection of the combined contact portion 210 with a larger width size, the problem of excessive erosion of the independent contact portion 220 adjacent to the combined contact portion 210 can also be effectively alleviated.

[0116] In the embodiment, when etching the conductive material layer 800 with the patterned mask layer as a mask, the method further includes forming an electrically conductive layer 230 corresponding to the third pattern 730 in the peripheral region 100B.

[0117] Next, referring to Figure 3e As shown in FIG. 7, in a further scheme, after the conductive material layer is etched to expose the isolation columns 300, the method further includes etching the isolation columns 300 to a predetermined depth. By further etching the isolation columns 300 between adjacent node contact portions, the conductive material between adjacent node contact portions can be effectively removed to ensure that adjacent node contact portions are separated from each other.

[0118] In the embodiment, the isolation columns 300 between adjacent independent contact portions 220 are exposed, the isolation columns 300 between the combined contact portion 210 and the adjacent independent contact portion 220 are also exposed, and the isolation columns between two node contact portions in the combined contact portion 210 are not exposed. Based on this, when the isolation columns 300 are etched, the height of the isolation columns 300 between adjacent independent contact portions 220 and the isolation columns 300 between the combined contact portion 210 and the adjacent independent contact portion 220 are both reduced and can form second isolation columns 320; and the isolation columns between two node contact portions in the combined contact portion 210 are not etched and form first isolation columns 310 with a higher height.

[0119] Continuing to refer to Figure 3e As shown in FIG. 7, in the peripheral region 100B, the electrically conductive layer 230 covers part of the isolation columns and also extends to cover the adjacent insulating filling columns 400. Based on this, when the isolation columns 300 are etched, the isolation columns and the insulating filling columns 400 not covered by the electrically conductive layer 230 are also etched at the same time to correspondingly reduce the height of the isolation columns and the insulating filling columns 400 not covered by the electrically conductive layer 230. Among them, the isolation columns located in the peripheral region 100B form third isolation columns 330.

[0120] Furthermore, after etching the isolation pillars 300 , a first shielding layer 510 is formed between the independent contact portions 220 and between the independent contact portions 220 and the combined contact portion 210 .

[0121] In this embodiment, when forming the first shielding layer 510, a second shielding layer 520 is also formed. The second shielding layer 520 is at least filled between the electrically conductive layer 230 and the combined contact portion 210. It should be understood that when multiple electrically conductive layers 230 are formed in the peripheral area 100B, the second shielding layer 520 is also filled between adjacent electrically conductive layers 230.

[0122] Example 2

[0123] The difference from the first embodiment is that in this embodiment, an isolation sidewall is formed on the sidewall of the groove between the combined contact portion and the electrically conductive layer, so that the isolation sidewall at least covers the sidewall of the combined contact portion close to the peripheral area.

[0124] Figure 4 FIG. 1 is a schematic diagram of the structure of the memory in the second embodiment of the present invention, as shown in FIG. Figure 4 As shown, the top surfaces of the third isolation pillar and the insulating filling pillar located between the electrically conductive layer 230 and the combined contact portion 210 are lower, thereby defining a recess between the electrically conductive layer 230 and the combined contact portion 210. In this case, a portion of the sidewall of the combined contact portion 210 facing the peripheral region is exposed in the recess. Furthermore, the isolation spacers 520' are formed on the sidewalls of the recess, and accordingly, the isolation spacers 520' cover at least a portion of the sidewalls of the combined contact portion 210.

[0125] Furthermore, an insulating film layer 530 ′ is formed on the bottom wall of the groove. The insulating film layer 530 ′ covers the top surface of the third isolation column and the top surface of the insulating filling column in the groove and connects to the bottom of the isolation sidewall 520 ′.

[0126] The isolation spacers 520' and the insulating film layer 530' can be formed simultaneously with the first shielding layer 510 formed in the memory region 100A. Specifically, the method for forming the first shielding layer 510, the isolation spacers 520' and the insulating film layer 530' includes the following steps.

[0127] A first step, forming an insulating material layer, which fills the gap between adjacent independent contact portions 220, and fills the gap between the independent contact portions 220 and the combined contact portion 210, and also fills at least the recess between the combined contact portion 210 and the electrically conductive layer 230, and the top surface of the insulating material layer further protrudes upwardly from the node contact portion top surface.

[0128] A second step, performing a back-etching process to remove the portion of the insulating material layer that protrudes above the node contact portion, and to retain the portion of the insulating material layer that fills between adjacent independent contact portions 220 and the portion of the insulating material layer that fills between the independent contact portions 220 and the combined contact portion 210 to form a first shielding layer 510; and, through the back-etching process, also partially remove the insulating material layer in the recess to form the isolation sidewall 520' on the sidewall of the recess, and retain a portion of the insulating material layer at the bottom of the recess to form an insulating film layer 530'.

[0129] In an optional solution, after forming the isolation sidewall 520', further comprising: forming a passivation layer 900, which fills the recess to correspondingly cover the isolation sidewall 520' and the insulating film layer 530'. And, the passivation layer 900 can also cover the first shielding layer 510 and the node contact portion in the memory region 100A.

[0130] Embodiment Three

[0131] The difference from Embodiment Two is that, in this embodiment, in the recess that is not covered by the electrically conductive layer, the top surface of the third isolation column covered by the isolation sidewall is higher than the top surface of the third isolation column not covered by the isolation sidewall.

[0132] Figure 5 The structural diagram of the memory in Embodiment Three of the present application is shown in FIG. 5, in which Figure 5 the isolation sidewall 520' is formed on the sidewall of the recess, and the bottom of the isolation sidewall 520' also partially covers the third isolation column 330 located in the recess. Among them, in the recess, the top surface of the third isolation column covered by the isolation sidewall 520' is higher than the top surface of the third isolation column not covered by the isolation sidewall 520'.

[0133] That is, in this embodiment, at least three different heights are provided for the plurality of different isolation columns. Among them, in the peripheral region, a part of the top surface of the third isolation column is flush with the top surface of the first isolation column; a part of the top surface of the third isolation column is flush with the top surface of the second isolation column; and, a part of the top surface of the third isolation column is further sunken relative to the top surface of the second isolation column.

[0134] Specifically, in this embodiment, the top of the first isolation column 310 between the two node contact portions in the combination contact portion 220 is located at a first height position H1, and the top of the third isolation column covered by the electrically conductive layer 230 in the peripheral region 100B is also located at the first height position H1. In addition, the area in the peripheral region 100B not covered by the electrically conductive layer 230 is formed with a recess, and the top of the third isolation column covered by the isolation side wall 520' in the recess is located at a second height position H2, and the top of the second isolation column 320 in the memory region 100A is also located at the second height position H2. Further, the top of the third isolation column not covered by the isolation side wall 520' in the recess is located at a third height position H3. Among them, the first height position H1 is higher than the second height position H2, and the second height position H2 is higher than the third height position H3.

[0135] In this embodiment, in the recess not covered by the electrically conductive layer 230, not only the third isolation column is exposed from the isolation side wall 520', but also the insulating filling column 400 is exposed. At this time, similar to the third isolation column, the top surface of the insulating filling column covered by the isolation side wall 520' in the recess is higher than the top surface of the insulating filling column not covered by the isolation side wall 520'. That is, the plurality of different insulating filling columns in this embodiment also correspondingly have at least three different heights.

[0136] Further, similar to embodiment two, the isolation side wall 520' and the first shielding layer 510 formed in the memory region 100A can be formed at the same time. Specifically, when performing the etch-back process, the part of the insulating material layer covering the bottom of the recess can be completely removed to form the isolation side wall 520' and expose the third isolation column and the insulating material layer. In addition, after the third isolation column and the insulating material layer are exposed, the third isolation column and the insulating material layer can be further etched to reduce the height of the third isolation column and the insulating material layer not covered by the isolation side wall 520' to the third height position H3.

[0137] It should be noted that the recess in this embodiment and the recess in embodiment two, for example, have different opening sizes (specifically, the opening size of the recess in this embodiment can be larger than the opening size of the recess in embodiment two). In this way, when performing the etch-back process to remove the part of the insulating material layer higher than the node contact portion, for the recess with a larger opening size, the isolation side wall 520' can be formed, and the insulating material layer at the bottom of the recess can be completely removed; and for the recess with a smaller opening size, part of the insulating material layer at the bottom of the recess can still be retained to constitute the insulating film layer 530'.

[0138] Similarly, after forming the isolation side wall 520', a passivation layer 900 can be further formed to fill the recesses and correspondingly cover the isolation side wall 520', the third isolation column and the insulating filling column.

[0139] In summary, in the memory as described above, the two node contact portions in the two node contact windows at the edge of each row are connected to each other to form a combined contact portion. At this time, the width of the combined contact portion at the edge is larger than that of the independent contact portion arranged inside. In this way, the appearance of the combined contact portion at the edge can be ensured even if it is easily eroded, and the remaining node contact portions can be protected from being eroded by the combined contact portion with a larger width, thereby improving the appearance accuracy of the independent node contact portions and further improving the device performance of the formed memory.

[0140] In a further solution, the active region at the edge can be defined as a non-functional active region, and the node contact portion at the edge can be connected to the non-functional active region. At this time, the node contact portion at the edge can be defined as a non-functional contact portion. Based on this, even if the two node contact portions at the edge are connected to each other, the device performance of the entire memory will not be affected.

[0141] It should be noted that although the present application has been disclosed with the preferred embodiments as above, the above embodiments are not intended to limit the present application. For any skilled person in the art, many possible changes and modifications of the above disclosed technical content, or equivalent embodiments of equivalent changes, can be made without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application, without departing from the content of the technical solutions of the present application, all still belong to the scope of protection of the technical solutions of the present application.

[0142] It should also be understood that, unless specifically described or indicated, the terms "first", "second", "third" and the like in the specification are merely used to distinguish different components, elements, steps and the like in the specification, and are not intended to represent a logical relationship or sequence relationship between the components, elements, steps and the like.

[0143] It is also to be appreciated that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the scope of the present application. It must be noted that, as used herein, the articles "a", "an" and "the" are intended to include both singular and plural references unless the context clearly dictates otherwise. For example, the references "a step" or "an element" can mean one or more steps or elements, and the references "the first step" or "the first element" can mean one or more steps or elements. Also, the use of the term "about" is intended to encompass variations, for example, due to manufacturing or processing tolerances, or variations in the natural properties of a given material. In addition, the use of the term "or" is intended to encompass both exclusive and inclusive meanings of the term, unless the context clearly indicates otherwise. Furthermore, the embodiments of methods and / or apparatuses can be implemented in hardware, software, or a combination thereof.

Claims

1. A memory, characterized in that: include: a substrate, wherein a memory area and a peripheral area are defined on the substrate, and the peripheral area is located outside the memory area; A plurality of isolation pillars are formed on the substrate and define a plurality of node contact windows in the memory region of the substrate; as well as, a plurality of node contacts, the node contacts filling the node contact windows and arranged in multiple rows, wherein two node contacts filling the edge of each row and adjacent to each other are connected to form a combined contact portion, and the node contacts located on a side of the combined contact portion away from the peripheral area constitute independent contacts; Among them, the isolation column used to separate adjacent node contact parts includes a first isolation column and a second isolation column, and the isolation column formed in the peripheral area constitutes a third isolation column, the top surface of the first isolation column is higher than the top surface of the second isolation column, the top surface of the second isolation column is higher than the top surface of at least part of the third isolation column, and the first isolation column, the second isolation column and the third isolation column are composed of the same material.

2. The memory according to claim 1, wherein In the third spacer located in the peripheral region, a top surface of a portion of the third spacer is flush with a top surface of the first spacer.

3. The memory according to claim 1, wherein In the third spacer located in the peripheral region, a top surface of a portion of the third spacer is flush with a top surface of the second spacer.

4. The memory according to claim 1, wherein Adjacent third isolation columns are separated by insulating filling columns.

5. The memory according to claim 1, wherein The memory further includes an electrically conductive layer formed on at least a portion of the third isolation pillar, wherein a top surface of a portion of the third isolation pillar covered by the electrically conductive layer is flush with a top surface of the first isolation pillar.

6. The memory according to claim 1, wherein: A top surface of the second spacer is lower than a top surface of the node contact portion.

7. The memory according to claim 6, wherein: The memory further includes a first shielding layer, which is at least filled between adjacent independent contact portions and is located on the second isolation column.

8. A memory, characterized in that: include: a substrate, wherein a memory area and a peripheral area are defined on the substrate, and the peripheral area is located outside the memory area; a plurality of isolation pillars formed on the substrate, including a first isolation pillar having a first height, a second isolation pillar having a second height, and a third isolation pillar having a third height, wherein the first isolation pillar, the second isolation pillar, and the third isolation pillar are made of the same material, and the first height is higher than the second height, and the second height is higher than the third height; A plurality of node contacts are formed on the substrate and arranged in multiple rows, wherein two adjacent node contacts at the edge of each row are connected to each other to form a combined contact, and the node contacts located on a side of the combined contact away from the peripheral area constitute independent contacts; The isolation sidewall at least covers a portion of the sidewall of the combined contact portion facing the peripheral region.

9. The memory according to claim 8, wherein The first isolation column is located in the memory area.

10. The memory according to claim 8, wherein The second isolation pillar is located in the memory area, and the third isolation pillar is located in the peripheral area.

11. The memory according to claim 8, wherein The first isolation column and the second isolation column define a plurality of node contact windows in the memory area, the node contacts are filled in the node contact windows and arranged in multiple rows, and the isolation column spaced between two node contacts in the combined contact portion constitutes a first isolation column.

12. The memory according to claim 11, wherein Among the plurality of node contacts, the spacers spaced between adjacent independent contacts constitute second spacers, and a first shielding layer is further formed on top surfaces of the second spacers.

13. The memory according to claim 11, wherein Two node contacts in the combined contact portion are connected at the top of the first isolation column and cover the top surface of the first isolation column.

14. The memory according to claim 8, wherein The top of the third isolation column is also covered with a passivation layer.

15. The memory according to claim 14, wherein: An electrical conductive layer is also formed on a portion of the third isolation column, and the passivation layer covers the electrical conductive layer.

16. The memory according to claim 8, wherein Adjacent third isolation columns are separated by insulating filling columns.

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