Semiconductor memory device and method of manufacturing the same

Abstract

Embodiments provide a semiconductor storage device capable of reducing the influence of load effect at the time of manufacturing and a manufacturing method thereof. The manufacturing method of the semiconductor storage device (10) of the embodiments includes the steps of: forming a processed portion (70) by alternately laminating an insulating layer (30) and a sacrificial layer (60); forming an etching mask (300) on a surface (S11) of the processed portion (70); forming, in a first region that is a part of the etching mask (300), a plurality of through holes (310) that reach the surface (S11) of the processed portion (70) from a surface (S20) of the etching mask (300), and forming, in a second region that is adjacent to the first region in the etching mask (300), a recessed portion (320) in which a part of the surface (S20) of the etching mask (300) is recessed toward the processed portion (70).

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2020-132863 (Filing Date: August 5, 2020). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] The disclosed embodiments relate to a semiconductor memory device and a manufacturing method thereof. BACKGROUND

[0004] In a semiconductor memory device such as a NAND (Not AND) type flash memory, for example, columnar memory pillars are provided in a manner that a laminate portion in which a plurality of insulating layers and conductor layers are alternately laminated is penetrated. In each memory pillar, a plurality of memory cells for storing information are formed along the length direction thereof.

[0005] When manufacturing a semiconductor memory device configured as described above, it is necessary to etch a portion that becomes a laminate portion to form a plurality of recesses, i.e., memory holes, for arranging the memory pillars. At this time, there is a tendency that, due to so-called "loading effect", the etching rate is reduced at a recess formed at an end portion compared to other recesses in a region in which a plurality of recesses are formed.

[0006] For example, if the inner diameter of a recess formed at an end portion is made larger than that of other recesses by performing OPC (Optical Proximity Correction) correction or the like on a mask used at the time of etching, it is possible to make the etching rates of all recesses close to uniform. However, since a high degree of miniaturization and high integration of semiconductor memory devices has been required in recent years, the method of increasing the shape of a part of the recesses is not desirable. SUMMARY

[0007] The problem to be solved by the present application is to provide a semiconductor memory device and a manufacturing method thereof that can reduce the influence of loading effect at the time of manufacturing.

[0008] A semiconductor memory device according to an embodiment includes: a stacked portion formed by alternating layers of insulating and conductive layers; and a plurality of memory pillars penetrating the stacked portion. Viewed along a direction perpendicular to the surface of the stacked portion, the stacked portion has a first region where the plurality of memory pillars are disposed, and a second region adjacent to the first region but without memory pillars. When the memory pillar formed at the position closest to the boundary between the first and second regions is designated as the first memory pillar, and the memory pillar formed at a position adjacent to the first memory pillar along a direction perpendicular to the boundary is designated as the second memory pillar, the width of the first memory pillar on the surface of the stacked portion and the width of the second memory pillar on the same surface are the same.

[0009] In addition, the method for manufacturing a semiconductor memory device disclosed herein includes the following steps: forming a work-bearing portion by alternately depositing an insulating layer and a sacrificial layer; forming an etching mask on the surface of the work-bearing portion; forming a plurality of through holes in a first region, which is part of the etching mask, extending from the surface of the etching mask to the surface of the work-bearing portion; and forming a recess in a second region of the etching mask adjacent to the first region, such that a portion of the surface of the etching mask is concavely recessed toward the work-bearing portion. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view showing the configuration of a semiconductor memory device according to an embodiment.

[0011] Figure 2 It means Figure 1 A top view showing the configuration of a semiconductor memory device.

[0012] Figure 3 It means Figure 1 A cross-sectional view of a method for manufacturing a semiconductor memory device.

[0013] Figure 4 It means Figure 1 A cross-sectional view of a method for manufacturing a semiconductor memory device.

[0014] Figure 5 It means Figure 1 A cross-sectional view of a method for manufacturing a semiconductor memory device.

[0015] Figure 6 It means Figure 1 A cross-sectional view of a method for manufacturing a semiconductor memory device.

[0016] Figure 7 It means Figure 1 A cross-sectional view of a method for manufacturing a semiconductor memory device.

[0017] Figure 8 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1

[0018] Figure 9 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1

[0019] Figure 10 is a diagram for explaining a problem in a conventional manufacturing method.

[0020] Figure 11 is a diagram for explaining a problem in a conventional manufacturing method.

[0021] Figure 12 is a diagram for explaining a problem in a conventional manufacturing method.

[0022] Figure 13 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1

[0023] is a plan view showing a manufacturing method of a semiconductor storage device. Figure 14 Figure 1

[0024] Figure 15 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1

[0025] Figure 16 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1

[0026] Figure 17 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1

[0027] Figure 18 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1

[0028] is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 19 Figure 1 is a sectional view showing a manufacturing method of a semiconductor storage device.

[0029] Figure 20 Figure 1 is a sectional view showing a manufacturing method of a semiconductor storage device.

[0030] Figure 21 is a sectional view showing a manufacturing method of a semiconductor storage device. Figure 1 ​​​​​​​​​A sectional view of the manufacturing method of the semiconductor storage device.

[0031] Figure 22 is a sectional view of the manufacturing method of the semiconductor storage device. Figure 1 A sectional view of the manufacturing method of the semiconductor storage device.

[0032] Figure 23 is a sectional view of the manufacturing method of the semiconductor storage device. Figure 1 A sectional view of the manufacturing method of the semiconductor storage device. DETAILED DESCRIPTION

[0033] Hereinafter, the present embodiment will be described with reference to the drawings. In order to make the description easy to understand, the same reference signs are attached to the same constituent elements in each drawing as much as possible, and repetitive description will be omitted.

[0034] The semiconductor storage device 10 of the present embodiment is a nonvolatile storage device configured as a NAND-type flash memory. In the semiconductor storage device 10, a plurality of memory cells are arranged three-dimensionally. Referring to FIG. 1, the semiconductor storage device 10 is configured as a memory card. The semiconductor storage device 10 is not limited to the memory card, and can be configured as a memory module, a memory stick, or the like. Figure 1 The configuration of the semiconductor storage device 10 will be described.

[0035] The semiconductor storage device 10 is provided with a semiconductor layer 20, a lamination portion 50, and a plurality of memory pillars 100.

[0036] The semiconductor layer 20 is a layer that functions as a so-called "source line" connected to the lower end of each memory pillar 100. The semiconductor layer 20 is, for example, a silicon substrate in which a part is doped with impurities. The semiconductor layer 20 can also be a layer containing amorphous silicon formed so as to cover the silicon substrate from the upper surface. In this case, a peripheral circuit for reading and writing data to and from the semiconductor storage device 10 can also be formed between the silicon substrate and the semiconductor layer 20.

[0037] The lamination portion 50 is a film formed so as to cover the semiconductor layer 20 from the upper side. Further, the "upper side" referred to herein is the "upper side" when the semiconductor storage device 10 is viewed as in FIG. 1. In the following description, the terms "upper" and "lower" and the like are also sometimes used, in which case, they are used as terms indicating the directions when the semiconductor storage device 10 is viewed as in FIG. 1. Figure 1 Figure 1

[0038] ​​In the stacked section 50, multiple insulating layers 30 and conductor layers 40 are alternately stacked in a direction perpendicular to the upper surface of the semiconductor layer 20. The insulating layers 30 are used to electrically insulate the conductor layers 40 from each other. The insulating layers 30 are formed, for example, of a material containing silicon oxide. As explained below, the conductor layers 40 are connected to the gates of the transistors formed along the memory pillars 100 and are used to apply voltage to these gates. The conductor layers 40 function as so-called "word lines." The conductor layers 40 are formed, for example, of a material containing tungsten.

[0039] The memory pillar 100 is a rod-shaped component formed in a generally cylindrical shape. The memory pillar 100 is arranged along its length in the stacking direction of the plurality of insulating layers 30 and conductive layers 40. The memory pillar 100 extends downward from the upper end of the stacked portion 50 to a position midway into the semiconductor layer 20. That is, the memory pillar 100 penetrates the entire stacked portion 50, including the insulating layers 30 and conductive layers 40, in the vertical direction, and its lower end is connected to the semiconductor layer 20, which serves as a substrate layer. In the semiconductor memory device 10, a plurality of memory pillars 100 are provided.

[0040] Each memory post 100 is disposed inside the memory aperture MH formed in the stacking section 50. The memory aperture MH is disposed along the stacking direction, i.e., along... Figure 1 It is formed in a manner that extends through the entire insulating layer 30 and conductor layer 40 in the vertical direction.

[0041] Each memory pillar 100 has a semiconductor layer 110 and a memory film 120. The semiconductor layer 110 occupies most of the memory pillar 100 and is formed, for example, of a material containing amorphous silicon. Other layers, such as those containing insulating materials, may also be formed on the inside of the memory pillar 100.

[0042] The memory film 120 is a film covering the entire side of the semiconductor layer 110. The memory film 120 is formed by laminating multiple film layers, but... Figure 2 In this context, these membranes are collectively depicted as a single storage membrane 120. Among the multiple membranes constituting the storage membrane 120, from its inner side, there are sequentially a tunnel insulating membrane, a charge storage membrane, and a barrier insulating membrane. The outermost barrier insulating membrane connects to each of the deposited conductor layers 40.

[0043] In the memory pillar 100, the inner side of the portion connecting each conductor layer 40 functions as a transistor. That is, in the semiconductor memory device 10, multiple transistors are connected in series along the length of each memory pillar 100. Each conductor layer 40 functions as the gate of its respective transistor. The semiconductor layer 110 located inside the transistor functions as the channel of that transistor.

[0044] The transistors arranged in series along the length direction of the memory pillar 100 function as storage units for storing data. In addition, the transistors formed at both end portions of the plurality of storage units arranged in series function as selection transistors for controlling the current flowing through the channel of each storage unit.

[0045] In the charge accumulation film of the storage film 120, charges are accumulated by applying a voltage to the conductor layer 40. The amount of charges accumulated in the charge accumulation layer corresponds to the data stored in the storage unit. The storage unit can be, for example, a charge-trapping type using a silicon nitride film or the like as the charge accumulation layer, or a floating gate type using a silicon film or the like as the charge accumulation layer.

[0046] At the end portion of the lower side of the memory pillar 100, the storage film 120 is removed, and the lower end of the semiconductor layer 110 is connected to the semiconductor layer 20. Thus, the semiconductor layer 20 functioning as a source line is electrically connected to the channel of each transistor. The upper end of the semiconductor layer 110 is connected to a bit line via a contact not shown.

[0047] Furthermore, as the configuration of the peripheral circuit for realizing reading and writing of data and the like to each storage unit or the specific operation thereof, various modes already known can be adopted. Therefore, a more specific description is omitted.

[0048] Figure 1 is a view of the semiconductor storage device 10 as viewed from the upper surface. Figure 2 is a view of the semiconductor storage device 10 as viewed from the upper surface. Figure 2 is a view of the semiconductor storage device 10 as viewed from the upper surface.

[0049] Figure 2 The single-dot chain line marked with the symbol "BD" indicates the boundary between the first region and the second region. Hereinafter, the boundary is also referred to as "boundary BD". Such a boundary BD is, for example, a straight line that is tangent to the outer periphery of the plurality of memory pillars 100 and can be defined as a boundary that divides the laminate portion 50 into a portion where the plurality of memory pillars 100 are arranged and a portion where the memory pillars 100 are not arranged, in the case of being viewed in the direction perpendicular to the surface S10 as described above. Figure 1

[0050] In addition, Figure 2 and Figure 2 does not represent the entire semiconductor storage device 10, but only a portion of the semiconductor storage device 10. For example, in Figure 2 ​The right side of the 2nd region depicted in FIG. 1 can also be provided with the same 1st region as the left side. In addition, the left side of the 1st region depicted in FIG. 1 can also be provided with the same 2nd region as the right side. Figure 1 The right side of the 1st region depicted in FIG. 1 can also be provided with the same 2nd region as the left side.

[0051] The 2nd region is provided with a separation portion 200. The separation portion 200 divides the plurality of memory pillars 100 and the laminate portion 50 in units of groups called "blocks" or groups called "fingers". The separation portion 200 is provided in a manner extending in the depth direction of the paper surface along the laminate direction. Figure 3 The separation portion 200, like the memory pillars 100, penetrates the laminate portion 50.

[0052] The separation portion 200 is provided inside the slit ST formed in the laminate portion 50. The slit ST, like the memory hole MH, is formed in a manner penetrating the entire insulating layer 30 and the conductor layer 40 along the laminate direction.

[0053] The separation portion 200 has a semiconductor 210 and an insulating film 220. The semiconductor 210 is a portion occupying a large portion of the separation portion 200, and is formed of, for example, a material containing amorphous silicon. Another layer containing, for example, a conductive material can also be formed inside the separation portion 200. The insulating film 220 is a film covering the entire side surface of the semiconductor 210. The insulating film 220 is formed of, for example, a material containing silicon oxide.

[0054] At the end portion of the lower side of the separation portion 200, the insulating film 220 is removed, and the lower end of the semiconductor 210 is connected to the semiconductor layer 20. Thus, the semiconductor layer 20 functioning as a source line is electrically connected to the semiconductor 210. The upper end of the semiconductor 210 is connected to an unillustrated wiring layer formed in the upper side portion of the semiconductor memory device 10 via an unillustrated contact. In this way, the separation portion 200 has a function of electrically connecting the semiconductor layer 20 and the wiring layer in addition to a function of dividing the plurality of memory pillars 100 and the laminate portion 50.

[0055] Next, a manufacturing method of the semiconductor memory device 10 of the present embodiment will be described.

[0056] The laminate step is a step in which a plurality of insulating layers 30 and sacrificial layers 60 are alternately formed in a manner covering the upper surface of the semiconductor layer 20. In the present embodiment, the laminate step is performed in a manner in which the insulating layers 30 and the sacrificial layers 60 are alternately formed in a manner covering the entire upper surface of the semiconductor layer 20. Figure 4 FIG. 1 shows a state in which the laminate step has been completed. As will be described later, the entire insulating layers 30 and the sacrificial layers 60 laminated are portions for implementing processing for forming the memory hole MH and the like. Therefore, hereinafter, the entire insulating layers 30 and the sacrificial layers 60 laminated in the laminate step will be described as "processed portions 70".

[0057] The processed portion 70 is a portion that becomes the build-up portion 50 described above after the replacement step. Hereinafter, a portion of the processed portion 70 that becomes the first region of the build-up portion 50 after the replacement step will be described as "the first region of the processed portion 70". Similarly, hereinafter, a portion of the processed portion 70 that becomes the second region of the build-up portion 50 after the replacement step will be described as "the second region of the processed portion 70". Furthermore, as in the case of the build-up portion 50, hereinafter, the boundary between the first region and the second region of the processed portion 70 will be described as "the boundary BD".

[0058] The sacrificial layer 60 is a layer that is replaced into the conductor layer 40 in the replacement step later, and is formed of a material containing silicon nitride, for example. In the build-up step, the processed portion 70 including the insulating layer 30 and the sacrificial layer 60 is formed by CVD (Chemical Vapor Deposition), for example. As such, the build-up step is a step of forming the processed portion 70 by alternately building up the insulating layer 30 and the sacrificial layer 60.

[0059] Hereinafter, the surface of the processed portion 70 at the point of time when the build-up step is completed will also be described as "the surface S11". The surface S11 is a surface S10 that eventually becomes the surface of the build-up portion 50.

[0060] The mask forming step is a step of forming the etching mask 300 in a manner of covering the surface S11 of the processed portion 70 after the build-up step. In the mask forming step, the etching mask 300 is formed in a manner of covering the surface S11 of the processed portion 70. Figure 5 The state in which the mask forming step is completed is shown in FIG. 6. As the etching mask 300, a carbon-based mask having relatively high etching resistance is preferably used, and an APF (Advanced Patterning Film) is preferably used, for example. As such, the mask forming step is a step of forming the etching mask 300 on the surface S11 of the processed portion 70. Hereinafter, the surface of the etching mask 300 at the point of time when the mask forming step is completed will also be described as "the surface S20".

[0061] The mask processing step is a step of forming the through-hole 310 and the recess 320 in the etching mask 300 after the mask forming step. In the mask processing step, the through-hole 310 and the recess 320 are formed in the etching mask 300. Figure 2 The state in which the mask processing step is completed is shown in FIG. 7. The through-hole 310 is a hole that is formed in a manner of penetrating the through-hole 310 at each position where the memory hole MH is to be formed. Each through-hole 310 is formed in a manner of reaching the surface S11 of the processed portion 70 from the surface S20 of the etching mask 300. The shape of the through-hole 310 when viewed in a direction perpendicular to the surface S20 is substantially the same as the shape of the memory hole MH formed later.

[0062] Regarding the etching mask 300, the terms "first region" and "second region" are defined in the same way as those for the stacked portion 50 and the processed portion 70. That is, the "first region" of the etching mask 300 refers to the portion of the etching mask 300 in which the through-hole 310 is formed and covers the processed portion 70 from above. The "second region" of the etching mask 300 refers to the portion of the etching mask 300 in which the through-hole 310 is not formed and covers the processed portion 70 from above.

[0063] Similar to the case of the stacked portion 50, the boundary between the first region and the second region in the etching mask 300 will also be referred to as "boundary BD" below. When viewed along a direction perpendicular to the surface S20, the boundary BD of the etching mask 300 is in a state of overlapping with the boundary BD of the processed portion 70.

[0064] The boundary BD of the etch mask 300 can be compared with the reference. Figure 5 The boundary BD of the stacked portion 50 described herein is similarly defined. That is, when viewed along a direction perpendicular to the surface S20, the boundary BD of the etch mask 300 is a straight line tangent to the edge of the plurality of through holes 310, and can be defined as the boundary that divides the etch mask 300 into portions having the plurality of through holes 310 and portions not having the plurality of through holes 310.

[0065] In the mask processing step, in addition to forming multiple through holes 310 in the first region of the etched mask 300 as described above, a recess 320 is also formed in the second region of the etched mask 300. The recess 320 is as follows... Figure 6 As shown, a portion of the surface S20 of the etching mask 300 is formed to recess towards the workpiece 70. The recessed portion of the surface of the etching mask 300 is distinguished from surface S20 and will be referred to as "surface S21" below. The effect of forming this recess 320 and the specific method of forming it will be explained below.

[0066] In this way, the mask processing step becomes the following steps, namely, forming a plurality of through holes 310 from the surface S20 of the etching mask 300 to the surface S11 of the workpiece 70 in a first region that is part of the etching mask 300, and forming a recess 320 in a second region of the etching mask 300 adjacent to the first region, such that a part of the surface S20 of the etching mask 300 is concavely recessed toward the workpiece 70.

[0067] <Recess Formation Step> In the recess formation step performed after the mask processing step, for example, the recess 71 that becomes the memory hole MH is formed by RIE (Reactive Ion Etching). Figure 7The value in the middle indicates that the recess formation step has been completed. In the recess formation step, the workpiece 70 is etched by causing ions to reach a position directly below the through hole 310 in the workpiece 70, thereby forming the recess 71.

[0068] The recess 71 is formed from the surface S11 of the workpiece 70 to a position midway into the semiconductor layer 20. Thus, the recess forming step becomes the step of forming the recess 71, which penetrates the workpiece 70 and reaches the midway into the semiconductor layer 20 located below the workpiece 70. In the recess forming step, the semiconductor layer 20 functions as an etch stop layer when forming the recess 71.

[0069] In the recess formation step, the etching mask 300 is also slightly etched. Therefore, the thickness of each portion of the etching mask 300 at the point when the recess formation step is completed is thinner than its initial thickness at the point when the mask processing step is completed. However, the second region of the etching mask 300, including the recess 320, still covers the entire second region of the processed portion 70 at the point when the recess formation step is completed. Therefore, in the recess formation step, the surface S11 of the second region in the processed portion 70 is not etched. When the recess formation step is completed, the etching mask 300 is removed by ashing.

[0070] <Memory Pillar Formation Step> In the memory pillar formation step, which follows the recess formation step, a barrier insulating film, a charge storage film, and a tunnel insulating film are sequentially formed on the inner peripheral surface of the recess 71, thereby forming a memory film 120. Then, a semiconductor layer 110 is formed further inside the memory film 120, thereby forming a memory pillar. Figure 8 The value in the image indicates that the memory pillar formation step has been completed. The formation of the memory film 120 and the semiconductor layer 110 are both performed by, for example, CVD.

[0071] <Slit Forming Step> In the slit forming step performed after the memory column forming step, a slit-shaped recess 72, which becomes a slit ST after being formed, is formed in the second region of the processed portion 70, for example by RIE. Figure 1 The center indicates that the slit formation step is complete. The shape of the recess 72 is consistent with the reference. Figure 9 The shape of the slit ST described is the same.

[0072] Although the illustration is omitted, in the slit formation step, similar to the recess formation step, an etching mask is pre-formed on the surface S11 of the workpiece 70, and a portion of the workpiece 70 is etched through the opening of the etching mask. The recess 72 is formed from the surface S11 of the workpiece 70 to a position that becomes the middle of the semiconductor layer 20.

[0073] <Replacement Step> In the replacement step performed after the slit formation step, the sacrificial layer 60, in which multiple layers are formed in the processed part 70, is replaced with the conductor layer 40. Figure 1 The value in the image indicates that the replacement step has been completed. In the replacement step, all sacrificial layers 60 are removed by wet etching via the recess 72. Then, a metal material, such as tungsten, is filled into the space where the sacrificial layers 60 are formed, thereby forming a conductor layer 40. The metal material is filled, for example, by CVD. By replacing the sacrificial layers 60 with the conductor layer 40, the processed portion 70 becomes the stacked portion 50. In addition, the recess 71 formed in the processed portion 70 becomes the memory hole MH of the stacked portion 50, and the recess 72 formed in the processed portion 70 becomes the slit ST of the stacked portion 50.

[0074] <Separation Part Formation Step> In the separation part formation step performed after the replacement step, an insulating film 220 is formed on the inner peripheral surface of the slit ST. Then, a semiconductor 210 is formed further inside the insulating film 220, thereby forming the separation part 200. Thus, Figure 10 The semiconductor memory device 10 shown is now complete. The insulating film 220 and the semiconductor 210 are both formed by, for example, CVD.

[0075] The reason for forming the recess 320 in the second region of the etched mask 300 during the mask processing step will be explained. First, an example where the recess 320 is not formed during the mask processing step, as in conventional manufacturing methods, will be described as a comparative example of this embodiment. Figure 5 In the comparative example, the state where the mask processing step has been completed is indicated. At the point in time when the mask processing step in the comparative example has been completed, in the first region of the etched mask 300, and... Figure 5 The example also forms multiple through holes 310. On the other hand, in the second region of the etched mask 300, unlike... Figure 10 In the example, the recess 320 was not formed.

[0076] If in like Figure 6 After processing the etching mask 300, the subsequent recess formation step is performed, which is also considered to be able to form a recess that is similar to... Figure 11 The same recess 71. However, in this case, it is difficult to form each recess 71 evenly. Figure 10 In the middle, it is indicated schematically that then Figure 11 The state during the midway through the concave machining step. For example... Figure 11 As shown, in this comparative example, the etching rate of the recess 71 formed at the location closest to the boundary BD is lower than the etching rate of the recess 71 formed at other locations.

[0077] The reason is as follows. As is generally known, when anisotropic etching based on RIE or the like is performed, because of so-called "loading effect", the consumption rate of the etching mask 300 varies at each site depending on the density of the processed pattern. In the case of this comparative example, in the first region where a plurality of through holes 310 are densely formed, the consumption rate of the etching mask 300 relatively becomes large, on the other hand, in the second region where no through hole 310 is formed, the consumption rate of the etching mask 300 relatively becomes small.

[0078] Therefore, as in the portion enclosed by the dotted line DL1, in the vicinity of the boundary BD, a step is generated in the surface S20 of the etching mask 300. Specifically, the height position of the surface S20 in the second region is higher than the height position of the surface S20 in the first region. Figure 12

[0079] In RIE, the carbon fluoride ions (CF+) that have reached the processed portion 70 through the through hole 310 do not all proceed in a direction perpendicular to the surface S20, but there are also carbon fluoride ions that proceed in a direction inclined with respect to this direction. That is, with respect to the direction in which the carbon fluoride ions proceed, there is a specified angular distribution.

[0080] Therefore, for example, a portion of the carbon fluoride ions that have reached the surface S20 in a space on the second region side with respect to the boundary BD is blocked by the step portion enclosed by the dotted line DL1 in the etching mask 300 by so-called "shadow effect", and thus cannot reach the processed portion 70. As a result, the etching rate of the recess 71 formed at a position closest to the boundary BD is lower than the etching rate of the recess 71 formed at other positions.

[0081] In addition, in the second region, as a large area of the etching mask 300 is etched, components that have separated from the etching mask 300 temporarily float. A portion of the components enters the inside of the through hole 310 located in the vicinity of the boundary BD, and thus hinders etching of the processed portion 70 by carbon fluoride ions. It is considered that this phenomenon also causes the etching rate of the recess 71 formed at a position closest to the boundary BD to decrease.

[0082] If it is intended to process all the recesses 71 to reach the semiconductor layer 20 from the state of Figure 11 , it is necessary to excessively perform RIE in the recess formation step. However, if it is intended to form all the recesses 71 by excessively performing RIE, the inner diameter of each recess 71 can become excessively large in at least a portion. In recent years, in order to achieve high integration, there is a tendency to increase the number of accumulations in the processed portion 70, but the more the number of accumulations in the processed portion 70 increases, the more the problem described above is obviously present, and it is difficult to form the recess 71 by excessive RIE.

[0083] ​As a countermeasure to prevent a decrease in the etching rate of the recess 71 formed at the location closest to the boundary BD, for example, consider... Figure 12 As shown in the example, the inner diameter D21 of the recess 71 formed closest to the boundary BD is made larger than the inner diameter D20 of the other recesses 71. Specifically, by performing, for example, OPC correction in the mask processing step, the inner diameter D21 of the through hole 310 formed closest to the boundary BD is made larger than the inner diameter D20 of the other through holes 310, and then the subsequent recess forming step is performed.

[0084] In this case, the etching rate of the recess 71 formed at the location closest to the boundary BD is higher than that of the recess 71. Figure 12 The etching rate is high, therefore, even under conditions where the loading effect described above occurs, the etching rate of each recess 71 can be made nearly uniform. However, given the high demands for miniaturization and high integration of semiconductor memory devices in recent years, increasing the shape of some recesses 71 is not ideal.

[0085] For example, in Figure 13 The shape of the recess 72 formed in the subsequent slit-forming step is indicated by the dashed line DL2. When the inner diameter of the recess 71 formed at the position closest to the boundary BD is increased, the recess 71 becomes excessively close to the dashed line DL2 (i.e., the recess 72). In addition, the more layers are added in the processed portion 70, the more difficult it becomes to make the inner diameter of the recess 71 uniform in the entire vertical direction, thus making it difficult to reduce the distance between the recess 71 and the dashed line DL2.

[0086] In conventional semiconductor memory device manufacturing methods, such as... Figure 5 As in the example above, the problem of etch rate deviation in the recess formation step is solved by making the shape of the through-hole 310 formed near the boundary BD different from the shape of other through-holes. However, in the future, if semiconductor memory devices become smaller and more integrated, the solution described above will reach its limit. In order to cope with high integration, it is preferable to reduce the influence of the load effect during manufacturing and make the shape of all recesses 71 uniform.

[0087] Therefore, in this embodiment, as described above, a recess 320 is formed in the etched mask 300 during the mask processing step.

[0088] exist Figure 13 In, with Figures 15 to 23 Similarly, this indicates that the mask processing step in this embodiment has been completed. Furthermore, Figure 14 The diagram only shows a portion of the upper side of the workpiece 70. The details used in the following description... Figure 13 The same applies to China.

[0089] exist Figure 14In the drawing, the direction along which the etching mask 300 is observed Figure 13 perpendicularly to the surface S20 is indicated by the arrow A1. Figure 13 In the case where the etching mask 300 is observed in the direction perpendicular to the surface S20, the recess 320 is formed in such a manner that the end portion 321 of the first region side in the recess 320 is parallel to the boundary BD between the first region and the second region. The "end portion 321 of the first region side in the recess 320" refers to a wall surface which extends from the end portion of the first region side in the surface S21 toward the upper side as indicated by the arrow A2. Figure 14

[0090] Further, in the drawing, the height of the wall surface in the etching mask 300, that is, the depth of the recess 320 is indicated by "H11". When the thickness of the portion other than the recess 320 in the etching mask 300 is set to "H10", the thickness of the portion of the recess 320 in the etching mask 300 is indicated by (H10 - H11). Figure 14 Hereinafter, the through hole 310 formed at the position closest to the boundary BD between the first region and the second region of the etching mask 300 will be referred to as the "first through hole 310A" when the etching mask 300 is observed in the direction perpendicular to the surface S20 as indicated by the arrow A1. Further, hereinafter, the through hole 310 formed at the position adjacent to the first through hole 310A in the direction perpendicular to the boundary BD, that is, the left-right direction will be referred to as the "second through hole 310B". Furthermore, hereinafter, the through hole 310 formed at the position adjacent to the second through hole 310B in the direction and at the position on the opposite side of the first through hole 310A will be referred to as the "third through hole 310C".

[0091] Figure 13 Further, in the drawing, the height of the wall surface in the etching mask 300, that is, the depth of the recess 320 is indicated by "H11". When the thickness of the portion other than the recess 320 in the etching mask 300 is set to "H10", the thickness of the portion of the recess 320 in the etching mask 300 is indicated by (H10 - H11). Figure 13 In the mask processing step of the present embodiment, each through hole 310 is formed in such a manner that the shortest distance from the edge of the first through hole 310A to the edge of the second through hole 310B is equal to the shortest distance from the edge of the second through hole 310B to the edge of the third through hole 310C. In the drawing, these shortest distances are indicated by "L30".

[0092] Figure 13 In the mask processing step of the present embodiment, each through hole 310 is formed in such a manner that the shortest distance from the edge of the first through hole 310A to the edge of the second through hole 310B is equal to the shortest distance from the edge of the second through hole 310B to the edge of the third through hole 310C. In the drawing, these shortest distances are indicated by "L30". 14

[0093] ​​​​Furthermore, in the mask processing step of this embodiment, each through hole 310 and recess 320 is formed such that the shortest distance from the edge of the first through hole 310A to the edge of the second through hole 310B is equal to the shortest distance from the edge of the first through hole 310A to the recess 320. In other words, in the mask processing step of this embodiment, the recess 320 is formed such that the shortest distance from the edge of the first through hole 310A to the recess 320 is L30.

[0094] Furthermore, in the mask processing step of this embodiment, each through hole 310 is formed in such a way that, when viewed along a direction perpendicular to the surface S20 of the etched mask 300, the shapes of the first through hole 310A and the second through hole 310B are identical. Figure 13 , 14 In this embodiment, the inner diameter of each through hole 310 is recorded as "D30". In the mask processing step of this embodiment, each through hole 310 is formed in such a way that not only the first through hole 310A and the second through hole 310B, but all through holes 310 have the same inner diameter, which is D30.

[0095] Furthermore, the inner diameter of the first through hole 310A and the inner diameter of the second through hole 310B do not necessarily have to be exactly the same. It is sufficient that at least the width of the first through hole 310A and the width of the second through hole 310B are the same at the same height. Additionally, the term "width" above refers, for example, along the direction perpendicular to the boundary BD. Figure 11 The inner diameter of the first through hole 310A or the second through hole 310B (in the left and right directions).

[0096] Focus on Figure 13 A first through-hole 310A is formed at the position closest to the boundary BD. To the left of the first through-hole 310A, there is an etch mask 300 with a width of L30 and a height of H10. In addition, to the right of the first through-hole 310A, there is an etch mask 300 with a width of L30 and a height of H10.

[0097] Next, focusing on the second through-hole 310B located next to the first through-hole 310A in the figure, there is an etching mask 300 with a width of L30 and a height of H10 on the left side of the second through-hole 310B. Additionally, there is an etching mask 300 with a width of L30 and a height of H10 on the right side of the second through-hole 310B.

[0098] In other words, when comparing the shape of the etching mask 300 surrounding the first through-hole 310A with the shape of the etching mask 300 surrounding the second through-hole 310B, the two are identical. Because the shapes of the etching masks 300 surrounding the first through-hole 310A and the second through-hole 310B are identical, the ease with which the loading effect occurs is also identical.

[0099] Therefore, if the etch mask 300 is pre-processed in the mask processing step to form the shape described above, the effect of the load effect can be reduced in the subsequent recess formation step. That is, the consumption rate of the etch mask 300 is uniform throughout the portion including the first through-hole 310A and the recess 320. As a result, it does not produce effects like... Figure 4 The step difference enclosed by the dashed line DL1 allows all recesses 71 to be processed at the same etching rate. If the inner diameter of all through holes 310 formed in the etching mask 300 is uniformly D30 as in this embodiment, then the inner diameter of the recesses 71 formed in the recess forming step can be the same size for all recesses 71.

[0100] Furthermore, during the recess formation step, the surface S21 of the recess 320 is also etched. Therefore, it is considered that the components separated from the surface S21 may be temporarily suspended, thereby affecting the etching of the work-processed portion 70 located below the first through-hole 310A. However, the components separated from S21 are blocked by the end 321 on the first region side of the recess 320, so the influence of these components can be suppressed to a negligible level. Experiments conducted by the inventors have confirmed that if the depth H11 of the recess 320 is set to approximately 500 nm, the etching rate of the recess 71 can be made uniform. This size can be adjusted appropriately according to the number of layers of the insulating layer 30 and the sacrificial layer 60 in the work-processed portion 70, the material of the etching mask 300, and the etching conditions.

[0101] The following describes the process of fabricating the etching mask 300. Figure 15 , 14 The details of the mask fabrication steps for the shape shown will be explained. Furthermore, the following description is merely one example of the mask fabrication steps. In the mask fabrication steps, the etching mask 300 can also be processed using methods different from those described below.

[0102] <Antireflective film formation step> Perform a mask formation step to form a mask as shown in the image. Figure 16After the thickness-equal etching mask 300 is shown, an antireflection film forming step is performed. In the antireflection film forming step, an antireflection film 410 is formed so as to cover the surface S20 of the etching mask 300. The antireflection film 410 is, for example, an antireflection film formed of a material containing silicon oxide. The antireflection film 410 is formed, for example, by CVD. In Figure 17 A state in which the antireflection film forming step has been completed is shown in

[0103] In the first resist forming step performed after the antireflection film forming step, a resist film 420 is formed so as to cover the surface of the antireflection film 410. Then, by performing exposure and etching on the resist film 420, the portion of the resist film 420 corresponding to the recess 320 is removed. In Figure 17 A state in which the first resist forming step has been completed is shown in

[0104] Hereinafter, the opening formed in the resist film 420 by the etching will also be described as "opening 421". The portion of the etching mask 300 located directly below the opening 421 is processed into the recess 320 in the mask processing step later.

[0105] In the mask recess forming step performed after the first resist forming step, anisotropic etching is performed on the etching mask 300 and the antireflection film 410. Thereby, the portion directly below the opening 421 is etched, and the recess 320 is formed in the etching mask 300. After the recess 320 is formed, the resist film 420 is removed by ashing. In Figure 17 A state in which the mask recess forming step has been completed is shown in

[0106] In the superposition step performed after the mask recess forming step, the antireflection film 410 is formed by, for example, CVD on the entire surface exposed on the upper side in the state of Figure 18 Thereby, the portion where the antireflection film 410 is formed in advance is thickened by the superposition of the antireflection film 410. In addition, the portion where the antireflection film 410 is not formed in advance, that is, the surface S21 of the recess 320 or the end portion 321 exposed in Figure 18 The surface S21 of the recess 320 or the end portion 321 exposed in Figure 19 A state in which the superposition step has been completed is shown in

[0107] In the coating film forming step performed after the superposition step, a coating film is formed on the entire surface exposed on the upper side in the state of Figure 20 In the present embodiment, as the coating film, a spin on carbon (SOC) film 430 and a spin on glass (SOG) film 440 are formed in this order.Figure 21 indicates a state in which the coating film forming step has been completed.

[0108] The SOC film 430 is a carbon-based coating type hard mask, and the SOG film 440 is a silicon-based coating type hard mask. The surface of the SOG film 440 formed on the uppermost side also includes a portion covering the recess 320, and the entire surface becomes a flat surface.

[0109] In the second resist forming step performed after the coating film forming step, a resist film 450 is formed so as to cover the surface of the SOG film 440. Then, by performing exposure and etching on the resist film 450, each portion of the resist film 450 corresponding to the through-hole 310 is removed. In Figure 21 indicates a state in which the first resist forming step has been completed. Further, the "portion of the resist film 450 corresponding to the through-hole 310" is a portion directly above the portion in which the through-hole 310 is formed in the etching mask 300 in the mask processing step described later. Hereinafter, the opening formed in the resist film 450 by the etching described above will also be referred to as "opening 451".

[0110] In the coating film processing step performed after the second resist forming step, anisotropic etching is performed on the SOC film 430 and the SOG film 440, which are coating films. Thereby, the portion of the SOG film 440 exposed directly below the opening 451 is etched, and a through-hole 441 is formed. In addition, the portion of the SOC film 430 directly below the opening 451 is also etched, and a through-hole 431 is formed. In Figure 22 indicates a state in which the coating film processing step has been completed.

[0111] Further, as the material of the resist film 450, the same carbon-based material as the SOC film 430 is used. Therefore, in the coating film processing step, the resist film 450 on the surface is also etched together with the SOC film 430. At the point in time at which the coating film processing step has been completed, as Figure 22 indicates, a state in which the resist film 450 has been completely removed.

[0112] In the antireflection film processing step performed after the coating film processing step, anisotropic etching is performed on the antireflection film 410. Thereby, the portion of the antireflection film 410 exposed directly below the through-hole 431 is etched, and a through-hole 411 is formed. In Figure 23 indicates a state in which the antireflection film processing step has been completed.

[0113] Further, as the material of the SOG film 440, a silicon-based material is used, and therefore, in the antireflection film processing step, the SOG film 440 on the surface is also etched together with the antireflection film 410. At the point in time at which the antireflection film processing step has been completed, asFigure 23 As shown, the state where the SOG film 440 has been completely removed is reached.

[0114] In the mask through-hole processing step, which is performed after the anti-reflective film processing step, anisotropic etching is performed on the etching mask 300. Thereby, the portion of the etching mask 300 that is exposed directly below the through-hole 411 is etched, forming the through-hole 310. In the mask through-hole processing step, the anti-reflective film 410 is also etched. As shown, the state where the anti-reflective film 410 has been completely removed is reached. Figure 5 As shown, the state where the SOG film 440 has been completely removed is reached.

[0115] Further, as the material of the SOG film 430, the same carbon-based material as the etching mask 300 is used. Therefore, in the mask through-hole processing step, the surface SOG film 430 is also etched together with the etching mask 300. At the point in time where the mask through-hole processing step has been completed, as shown, the state where the SOG film 430 has been completely removed is reached. However, even if the SOG film 430 has been completely removed, the entire surface S21 of the recess 320 in the etching mask 300 is protected by the anti-reflective film 410. Therefore, the surface S21 is not etched during the course of performing the mask through-hole processing step. Figure 14 As shown, the state where the SOG film 440 has been completely removed is reached.

[0116] After the mask through-hole processing step is completed, the entire anti-reflective film 410 is removed by etching back. Thereby, the entire mask processing step is completed, and the etching mask 300 becomes the state shown. Figure 14 As shown, the state where the SOG film 440 has been completely removed is reached.

[0117] As described above, in the mask processing step of the present embodiment, the anti-reflective film formation step, the first resist formation step, the mask recess formation step, the superposition step, the coating film formation step, the second resist formation step, the coating film processing step, the anti-reflective film processing step, and the mask through-hole processing step, which have been described thus far, are sequentially performed, whereby the through-hole 310 and the recess 320 are formed in the etching mask 300, respectively. In the mask processing step of the present embodiment, the recess 320 is formed first, and then the through-hole 310 is formed, but the order in which the recess 320 and the through-hole 310 are formed can be different from this.

[0118] In the present embodiment, the recess 320 is formed in the etching mask 300 by the mask processing step as described above. Thereby, as described above, the influence of the loading effect can be suppressed, and in the recess formation step, a plurality of recesses 71 can be processed at substantially equal etching rates.

[0119] As described above, in the mask processing step of the present embodiment, the anti-reflective film formation step, the first resist formation step, the mask recess formation step, the superposition step, the coating film formation step, the second resist formation step, the coating film processing step, the anti-reflective film processing step, and the mask through-hole processing step, which have been described thus far, are sequentially performed, whereby the through-hole 310 and the recess 320 are formed in the etching mask 300, respectively. In the mask processing step of the present embodiment, the recess 320 is formed first, and then the through-hole 310 is formed, but the order in which the recess 320 and the through-hole 310 are formed can be different from this. Figure 14As explained, in the mask processing step of this embodiment, the recess 320 is formed such that, when viewed along a direction perpendicular to the surface S20 of the etched mask 300, the end 321 on the first region side of the recess 320 is parallel to the boundary BD between the first region and the second region. Therefore, the distance between all the first through holes 310A, which are easily affected by the load effect, and the recess 320 is ( Figure 13 In the example, L30) are all equal. As a result, the etching rates of all through holes 310 containing each first through hole 310A can be made closer to being equal.

[0120] Additionally, as mentioned above... Figure 2 As explained, in the mask processing step of this embodiment, each through-hole 310 and recess 320 is formed such that the shortest distance from the edge of the first through-hole 310A to the edge of the second through-hole 310B is equal to the shortest distance from the edge of the first through-hole 310A to the recess 320. With this configuration, the shape of the etching mask 300 surrounding the first through-hole 310A is consistent with the shape of the etching mask 300 surrounding the second through-hole 310B, thus making the etching rate of all through-holes 310 more uniform.

[0121] According to the manufacturing method of this embodiment, the effect of the load effect in the recess forming step is suppressed, therefore, it is not necessary to make the shape of the first through hole 310A different from the shapes of the other through holes 310. Therefore, as shown in the reference... Figure 2 , 14 As explained, in the mask processing step, each through hole 310 can be formed in such a way that the shape of the first through hole 310A and the shape of the second through hole 310B are the same. Alternatively, each through hole 310 can be formed such that, when viewed along a direction perpendicular to the surface S20 of the etch mask 300, the shortest distance from the edge of the first through hole 310A to the edge of the second through hole 310B is equal to the shortest distance from the edge of the second through hole 310B to the edge of the third through hole 310C.

[0122] Refer again Figure 2 The configuration of the semiconductor memory device 10 manufactured through the manufacturing steps described above will be explained below. Hereinafter, it will also be described as follows... Figure 2The memory pillar 100 formed at a position closest to the boundary BD of the first region and the second region of the lamination part 50 is referred to as "first memory pillar 100A" when viewed in a direction perpendicular to the surface S10 of the lamination part 50. Also, hereinafter, the memory pillar 100 formed at a position adjacent to the first memory pillar 100A in a direction perpendicular to the boundary BD is referred to as "second memory pillar 100B". Further, hereinafter, the memory pillar 100 formed at a position adjacent to the second memory pillar 100B in the direction and at a position on the opposite side of the first memory pillar 100A is referred to as "third memory pillar 100C".

[0123] In the present embodiment, in the mask processing step, each through-hole 310 is formed in the same shape as each other, and as a result, each memory hole MH for arranging the memory pillar 100 is also formed in the same shape as each other.

[0124] Therefore, in the semiconductor memory device 10, as shown in Figure 14 the shape of the first memory pillar 100A in the surface S10 of the lamination part 50 is the same as the shape of the second memory pillar 100B in the surface S10. Figure 2 In the present embodiment, the diameter of each memory pillar 100 in the surface S10 is referred to as "D10". In the semiconductor memory device 10, the diameter of all the memory pillars 100, not only the first memory pillar 100A and the second memory pillar 100B, is equal in the surface S10, and is D10. The D10 is a dimension substantially equal to the inner diameter D30 of the through-hole 310 formed in the etching mask 300 (refer to Figure 2 ).

[0125] Further, the shape of the first memory pillar 100A in the surface S10 and the shape of the second memory pillar 100B in the surface S10 can not be completely the same. As long as at least the width of the first memory pillar 100A and the width of the second memory pillar 100B are the same as each other in the surface S10. Further, the "width" in the above, for example, refers to the outer diameter dimension of the first memory pillar 100A or the second memory pillar 100B in the direction perpendicular to the boundary BD (the left-right direction in Figure 2 ).

[0126] In the present embodiment, in the mask processing step, each through-hole 310 is formed in such a manner that the distance between the through-holes 310 adjacent to each other in the direction perpendicular to the boundary BD is equal to each other. As a result, the distance between each memory hole MH for arranging the memory pillar 100 also becomes a distance equal to each other.

[0127] Therefore, in the semiconductor memory device 10, as shown in Figure 14As shown, in the surface S10, the shortest distance from the edge of the first memory pillar 100A to the edge of the second memory pillar 100B is equal to the shortest distance from the edge of the second memory pillar 100B to the edge of the third memory pillar 100C.

[0128] In ​ , the distance between the memory pillars 100 is denoted as "L10". In the semiconductor storage device 10, not only the distance between the first memory pillar 100A and the second memory pillar 100B and the distance between the second memory pillar 100B and the third memory pillar 100C are equal, but also the distance between the through holes 310 adjacent to each other in the direction perpendicular to the boundary BD is equal, and is L10. This L10 is a dimension substantially equal to the distance between the through holes 310 formed adjacent to each other in the etching mask 300, that is, L30 (refer to ​ ).

[0129] As described above, in the semiconductor storage device 10 of the present embodiment, all of the memory pillars 100 including the first memory pillar 100A formed at the position closest to the boundary BD are made to have the same shape, and are arranged in a manner of being arranged at equal intervals. Therefore, compared to the conventional configuration in which the shape or arrangement of a part of the memory pillars 100 is made different from the other memory pillars 100 in consideration of the effect of the loading effect, it is possible to suppress the increase in size of the semiconductor storage device 10.

[0130] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Examples obtained by appropriately applying design changes to these specific examples are also included in the scope of the present disclosure as long as they have the features of the present disclosure. The elements, arrangement, conditions, shape, and the like possessed by each of the specific examples are not limited to the illustrated content, and can be appropriately changed. The elements possessed by each of the specific examples can be appropriately changed as long as no technical contradiction occurs.

[0131] [Explanation of Symbols]

[0132] 10 semiconductor storage device

[0133] 30 insulating layer

[0134] 40 conductor layer

[0135] 50 build-up portion

[0136] 60 sacrificial layer

[0137] 70 processed portion

[0138] 71 recessed portion

[0139] 100 memory pillar

[0140] S10 surface

[0141] S11 surface

[0142] S20 surface

[0143] S21 surface

[0144] BD boundary.

Claims

1. A method of manufacturing a semiconductor memory device, comprising the steps of: forming a processed portion by alternately laminating an insulating layer and a sacrificial layer; forming an etching mask on a surface of the processed portion; forming a plurality of through-holes reaching a surface of the processed portion from a surface of the etching mask in a first region that is a part of the etching mask; and forming a recess in which a part of the surface of the etching mask is concavely recessed toward the processed portion in a second region that is adjacent to the first region in the etching mask; and wherein the step of forming the recess in the second region includes: forming an anti-reflection film on the surface of the etching mask; forming a resist film on a surface of the anti-reflection film; forming an opening corresponding to the recess in the resist film by removing a part of the resist film corresponding to the recess; etching the etching mask and the anti-reflection film, and etching a part of the etching mask and the anti-reflection film directly below the opening of the resist film, thereby forming the recess in the etching mask; the plurality of through-holes are formed in the first region of the etching mask in which the recess is formed in the second region; when viewed in a direction perpendicular to the surface of the etching mask, an end portion of the recess on the first region side is parallel to a boundary between the first region and the second region, the through-hole formed at a position closest to the boundary between the first region and the second region is a first through-hole, the through-hole formed at a position adjacent to the first through-hole in a direction perpendicular to the boundary is a second through-hole, and each of the through-holes and the recess is formed in such a manner that a shortest distance from a rim of the first through-hole to a rim of the second through-hole is equal to a shortest distance from the rim of the first through-hole to the recess, and a width of the first through-hole is equal to a width of the second through-hole at the same height position.

2. The method of manufacturing a semiconductor memory device according to claim 1, wherein each of the through-holes is formed in such a manner that, when viewed in a direction perpendicular to the surface of the etching mask, a through-hole formed at a position adjacent to the second through-hole in a direction perpendicular to the boundary and at a position on the opposite side of the first through-hole is a third through-hole, and a shortest distance from the rim of the first through-hole to the rim of the second through-hole is equal to a shortest distance from the rim of the second through-hole to the rim of the third through-hole.

3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the step of forming the through-holes in the first region includes: forming a second anti-reflection film on a surface of the etching mask in which the recess is formed, the surface including the first region and the second region; forming a coating film on a surface of the second anti-reflection film; forming a second resist film on a surface of the coating film; forming a second opening corresponding to the through-holes in the second resist film by removing a part of the second resist film corresponding to the through-holes; and etching the etching mask and the second anti-reflection film, and etching a part of the etching mask and the second anti-reflection film directly below the second opening of the second resist film, thereby forming the through-holes in the etching mask. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The coating film, the second antireflection film, and the etching mask are etched, and a portion of the coating film, the second antireflection film, and the etching mask directly below the second opening of the second resist film is etched, thereby forming the through-hole in the etching mask. The coating film, the second antireflection film, and the etching mask are etched, and a portion of the coating film, the second antireflection film, and the etching mask directly below the second opening of the second resist film is etched, thereby forming the through-hole in the etching mask.

Images