Power conversion device

Abstract

The present invention provides a power conversion device comprising a totem pole power factor improvement circuit and a control circuit. The totem pole power factor improvement circuit includes: a coil connected to a first terminal of an AC power supply; a first half-wave switch, whose source terminal is connected to the coil via a first current detector; a second half-wave switch, whose drain terminal is connected to the coil via a second current detector; a first diode, whose cathode is connected to the drain terminal of the first half-wave switch and whose anode is connected to the second terminal of the AC power supply; a second diode, whose anode is connected to the source terminal of the second half-wave switch and whose cathode is connected to the second terminal of the AC power supply; and a smoothing capacitor connected between the cathode of the first diode and the anode of the second diode. The control circuit performs pulse width control for turning the first and second half-wave switches on and off based on the total value of the DC voltage detection results of the first and second current detectors.

Description

Technical Field

[0001] Embodiments of the present invention relate to a power conversion device. Background Art

[0002] A power conversion device converts the AC voltage from an AC power supply into a DC voltage and supplies power to a load. When converting the AC voltage from the AC power supply into a DC voltage, the AC current flowing through the AC power supply is converted into a sinusoidal wave in phase with the AC voltage, resulting in an optimal power factor and minimal harmonic noise. For example, the power conversion device includes a totem pole power factor improvement circuit that converts the input current into a sinusoidal wave.

[0003] In order to control the totem pole type power factor improvement circuit as described above, it is necessary to detect the AC current flowing through the input AC voltage. For example, a power conversion device equipped with a current transformer for detecting current has been put into practical use. However, in this structure, the detection result of the AC current is output as a positive or negative signal. Therefore, in the control IC for controlling the totem pole type power factor improvement circuit, the result of the current detection cannot be used directly. Therefore, it is necessary to convert the current detection result into a signal based on an arbitrary GND as a reference, that is, to perform insulation, which has the problem of complicating the circuit. In addition, since the current transformer is expensive, there is a problem of increased cost. Summary of the Invention

[0004] An object of the present invention is to provide a power conversion device including a totem pole power factor improvement circuit capable of performing efficient power conversion with a simple structure.

[0005] A power conversion device according to one embodiment includes a totem-pole power factor improvement circuit and a control circuit. The totem-pole power factor improvement circuit includes: a coil connected to a first terminal of an AC power supply; a first half-wave switch having a source terminal connected to the coil via a first current detector; a second half-wave switch having a drain terminal connected to the coil via a second current detector; a first diode having a cathode connected to the drain terminal of the first half-wave switch and an anode connected to the second terminal of the AC power supply; a second diode having an anode connected to the source terminal of the second half-wave switch and a cathode connected to the second terminal of the AC power supply; and a smoothing capacitor connected between the cathode of the first diode and the anode of the second diode. The control circuit performs pulse width control for turning the first and second half-wave switches on and off based on the sum of the DC voltage detection results of the first and second current detectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1It is a diagram for explaining an example of the structure of a power conversion device according to one embodiment.

[0007] Figure 2 This is a diagram for explaining an example of the operation of the totem pole PFC according to one embodiment.

[0008] Figure 3 This is a diagram for explaining an example of the configuration of a control circuit according to one embodiment.

[0009] Figure 4 This is a diagram for explaining an example of the configuration of a reference voltage conversion circuit according to one embodiment.

[0010] Figure 5 This is a diagram for explaining an example of the configuration of a control circuit according to one embodiment.

[0011] Figure 6 This is a diagram for explaining an example of the structure of a first insulating driver and a second insulating driver according to one embodiment.

[0012] Figure 7 This is a diagram for explaining control of a totem pole PFC according to one embodiment.

[0013] Figure 8 This is a diagram for explaining another configuration example of the polarity detection circuit according to one embodiment.

[0014] Figure 9 This is a diagram for explaining another configuration example of a control circuit according to one embodiment.

[0015] Description of Reference Numerals

[0016] 1…Power conversion device, 2…Load circuit, 11…Filter circuit, 12…Totem pole power factor improvement circuit, 13…LLC resonant circuit, 14…Insulated ACDC circuit, 15…AC voltage detection circuit, 16…Control circuit, 17…Current detection circuit, 21…Reference voltage conversion circuit, 22…PFC control circuit, 23…First isolation driver, 24…Second isolation driver, 31…Low-pass filter, 32…First comparator, 33…Polarity detection circuit, 34…Voltage detection circuit, 35…Absolute value conversion circuit, 36…Multiplier, 37…Current determiner, 38…Second comparator , 39…PWM converter, 40…selector, 41…pulse transformer, 51…logic circuit, C1…first smoothing capacitor, C2…second smoothing capacitor, C3…third smoothing capacitor, D1…first diode, D2…second diode, D3…third diode, D4…fourth diode, L1…first coil, L2…second coil, L3…third coil, L4…fourth coil, L5…fifth coil, R1…first resistor, R2…second resistor, S1…first half-wave switch, S2…second half-wave switch, S3…switching element, S4…switching element, S5…switching element, S6…switching element. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0018] Figure 1 1 is a diagram showing a structural example of a power conversion device 1 involved in one embodiment. The power conversion device 1 includes a totem pole power factor improvement circuit and an isolation converter. The power conversion device 1 equipped with the totem pole power factor improvement circuit is connected to an alternating current power supply AC as an input power supply. The totem pole power factor improvement circuit converts the AC voltage of the AC power supply AC (for example, 100V) into a high-voltage (for example, 400V) DC voltage. The isolation converter is a so-called DC-DC converter, that is, it switches the DC voltage from the totem pole power factor improvement circuit at a high frequency and converts it into a DC low voltage (for example, about 24V). The power conversion device 1 outputs the DC power converted by the isolation converter to the load circuit 2, thereby operating the load circuit 2.

[0019] First, the structure of the power converter 1 will be described. The power converter 1 includes a filter circuit 11 , a totem pole power factor correction circuit (totem pole PFC) 12 , an LLC resonant circuit 13 , an isolated ACDC circuit 14 , an AC voltage detection circuit 15 , and a control circuit 16 .

[0020] The filter circuit 11 removes noise that leaks from the power converter 1 to the AC power supply AC. For example, the filter circuit 11 is an EMC filter. The filter circuit 11 receives an AC voltage with a commercial frequency component of 50 Hz from its input terminals and outputs it from its output terminals. The filter circuit 11 blocks high-frequency noise generated by the power converter 1 from reaching the output terminals and prevents it from being transmitted to the input terminals. Furthermore, the filter circuit 11 includes a first terminal AC1 and a second terminal AC2 as output terminals. In other words, AC power is output from the first and second terminals AC1 and AC2. Furthermore, the first and second terminals AC2 of the filter circuit 11 are each connected to an isolated ACDC circuit 14.

[0021] The totem-pole PFC 12 converts the AC voltage obtained from the AC power source AC via the filter circuit 11 into a boosted DC voltage, which is then supplied to the LLC resonant circuit 13. The totem-pole PFC 12 boosts the voltage to a DC voltage higher than the peak value of the AC voltage. This allows the totem-pole PFC 12 to control the AC current to a sinusoidal waveform. For example, the totem-pole PFC 12 boosts the AC voltage to a DC voltage of 400V. This allows the totem-pole PFC 12 to control the current even with AC voltages between 90V and 256V. This allows the totem-pole PFC 12 to form a universal power converter.

[0022] The totem pole PFC 12 includes a first coil L1 , a first half-wave switch S1 , a second half-wave switch S2 , a first diode D1 , a second diode D2 , a first smoothing capacitor C1 , a first resistor R1 , and a second resistor R2 .

[0023] The first coil L1 is connected to a first terminal of the alternating current power source AC via the filter circuit 11. For example, the first coil L1 is connected to a first terminal AC1 of the filter circuit 11.

[0024] The first half-wave switch S1 and the second half-wave switch S2 are switching elements that are turned on and off by the control of the control circuit 16. The first half-wave switch S1 and the second half-wave switch S2 are formed of, for example, a wide-bandgap semiconductor such as SiC, GaN, gallium oxide, or diamond. Elements formed of such semiconductors have faster switching speeds than silicon MOSFETs and have lower stray capacitance between the drain and source, resulting in lower switching losses.

[0025] The first half-wave switch S1 is turned on and off by a gate signal G1 supplied from the control circuit 16. The second half-wave switch S2 is turned on and off by a gate signal G2 supplied from the control circuit 16.

[0026] The source terminal of the first half-wave switch S1 is connected to the first coil L1 via the first resistor R1. The drain terminal of the second half-wave switch S2 is connected to the first coil L1 via the second resistor R2. That is, the first resistor R1 and the second resistor R2 are connected in series between the source terminal of the first half-wave switch S1 and the drain terminal of the second half-wave switch S2. That is, the drain terminal of the second half-wave switch S2 is connected to the source terminal of the first half-wave switch S1 via the series connection of the first resistor R1 and the second resistor R2.

[0027] The resistance values ​​of the first resistor R1 and the second resistor R2 are, for example, a minimum value of approximately 0.01Ω. The connection point between the first resistor R1 and the second resistor R2 is referred to as a connection point M. Connection point M is connected to the first coil L1. Furthermore, the connection point between the second resistor R2 and the drain terminal of the second half-wave switch S2 is referred to as a reference point GND. The following description assumes that the potential of the reference point GND is the reference potential (potential 0V) for various control signals described later.

[0028] The connection point between the first resistor R1 and the source terminal of the first half-wave switch S1 is connected to the control circuit 16. Signal IS is supplied from the connection point between the first resistor R1 and the source terminal of the first half-wave switch S1 to the control circuit 16. Signal IS is a signal generated across the series resistance of the first resistor R1 and the second resistor R2. Specifically, Signal IS represents the potential at the connection point between the first resistor R1 and the source terminal of the first half-wave switch S1, with reference to GND, the connection point between the second resistor R2 and the drain terminal of the second half-wave switch S2. In other words, Signal IS represents the sum of the detection results of the DC voltage applied to the first resistor R1 and the DC voltage applied to the second resistor R2. Specifically, the control circuit 16 sets the potential at the connection point between the drain terminal of the second half-wave switch S2 and the second resistor R2 to GND and obtains the potential at the connection point between the source terminal of the first half-wave switch S1 and the first resistor R1 relative to GND as Signal IS.

[0029] When current flows from connection point M to GND, the potential at connection point M is positive relative to GND. In this case, the potential difference between connection point M and the source terminal of first half-wave switch S1 is zero. That is, the voltage of signal IS equals the voltage at connection point M, and signal IS is positive relative to GND.

[0030] Furthermore, when current flows from the source terminal of first half-wave switch S1 to connection point M, signal IS becomes a positive voltage relative to connection point M. In this case, the potential difference between connection point M and GND becomes zero. That is, the voltage at connection point M equals the voltage at GND, and signal IS becomes positive relative to GND.

[0031] Furthermore, when current flows from connection point M to the source terminal of first half-wave switch S1 via first resistor R1, the potential at connection point M becomes negative relative to the source terminal of first half-wave switch S1. In this case, the potential difference between connection point M and GND becomes zero. Signal IS becomes negative relative to GND.

[0032] Furthermore, when current flows from GND to connection point M, the potential at connection point M becomes negative relative to GND. In this case, the potential difference between connection point M and the source terminal of first half-wave switch S1 becomes zero. That is, the voltage of signal IS equals the voltage at connection point M, and signal IS becomes negative relative to GND.

[0033] With this configuration, the first resistor R1 and the second resistor R2 form a current detection circuit 17, which supplies a signal IS indicating the value of the current flowing through the first coil L1 to the control circuit 16. Furthermore, the first resistor R1 functions as a first current detector (or a first voltage detector). Furthermore, the second resistor R2 functions as a second current detector (or a second voltage detector).

[0034] The cathode of the first diode D1 is connected to the drain terminal of the first half-wave switch S1, and the anode is connected to the second terminal of the AC power source AC via the filter circuit 11. The anode of the second diode D2 is connected to the source terminal of the second half-wave switch, and the cathode is connected to the anode of the first diode D1. In addition, the connection point between the anode of the first diode D1 and the cathode of the second diode D2 is connected to the second terminal AC2 of the filter circuit 11.

[0035] The first smoothing capacitor C1 is connected between the cathode of the first diode D1 and the anode of the second diode D2. The positive and negative terminals of the first smoothing capacitor C1 constitute the output terminals of the high-voltage DC output of the totem-pole PFC 12. Furthermore, the positive and negative terminals of the first smoothing capacitor C1 are each connected to the control circuit 16. This provides a signal DC1 corresponding to the potential of the positive terminal of the first smoothing capacitor C1 to the control circuit 16. Furthermore, a signal DC2 corresponding to the potential of the negative terminal of the first smoothing capacitor C1 is also provided to the control circuit 16.

[0036] The LLC resonant circuit 13 is a DC-DC converter circuit that supplies the DC voltage required by the load circuit 2 from the high-voltage DC voltage supplied by the totem-pole PFC 12. The LLC resonant circuit 13 includes a switching element S3, a switching element S4, a switching element S5, a switching element S6, a second coil L2, a first winding L3, a second winding L4, a third winding L5, a second smoothing capacitor C2, and a third smoothing capacitor C3.

[0037] Switching elements S3, S4, S5, and S6 are switched on and off by control of control circuit 16. Switching elements S3, S4, S5, and S6 are, for example, silicon MOSFETs. In LLC resonant circuit 13, since resonance is utilized, high-frequency operation can be achieved without using high-speed components. Therefore, unlike totem-pole PFC 12, silicon MOSFETs can be used.

[0038] The switching element S3 is turned on and off by a gate signal G3 supplied from the control circuit 16. The switching element S4 is turned on and off by a gate signal G4 supplied from the control circuit 16. The switching element S5 is turned on and off by a gate signal G5 supplied from the control circuit 16. The switching element S6 is turned on and off by a gate signal G6 supplied from the control circuit 16.

[0039] The drain terminal of switching element S3 is connected to one output terminal of the totem pole PFC 12 (the positive terminal of the first smoothing capacitor C1). The source terminal of switching element S4 is connected to the other output terminal of the totem pole PFC 12 (the negative terminal of the first smoothing capacitor C1), and the drain terminal is connected to the source terminal of switching element S3. Furthermore, the second coil L2, the second smoothing capacitor C2, and the first winding L3 are connected in series between the connection point of switching element S3 and switching element S4 and the source terminal of switching element S4.

[0040] The first winding L3, the second winding L4, and the third winding L5 form an isolation transformer T1. The second winding L4 and the third winding L5 are insulated from the first winding L3 and are excited by the magnetic field generated in the first winding L3. The second winding L4 and the third winding L5 are connected to each other. The isolation transformer T1 is configured so that the ratio (turns ratio) of the number of turns (T: turns) between the first winding L3 and the second winding L4 is equal to the turns ratio between the first winding L3 and the third winding L5. Furthermore, the isolation transformer T1 determines the turns ratio (L3:L4) between the first winding L3 and the second winding L4, and the turns ratio (L3:L5) between the first winding L3 and the third winding L5, depending on whether the LLC resonant circuit 13 is a step-up or step-down circuit. For example, when the LLC resonant circuit 13 is configured as a step-down circuit, the turns ratio is determined so that the turns ratio (L3:L4) and the turns ratio (L3:L5) are 20T:5T, and the number of windings of the second winding L4 and the third winding L5 on the secondary side are reduced relative to the first winding L3 on the primary side.

[0041] According to the above configuration, by turning on and off the switching elements S3 and S4, an alternating current flows into the second coil L2. Furthermore, an alternating current equal to that flowing into the second coil L2 flows into the first winding L3 of the isolation transformer T1. This generates a magnetic field in the isolation transformer T1 that changes in accordance with the alternating current. The changes in the magnetic field (magnetic flux) generated within the isolation transformer T1 induce voltages in the second and third windings L4 and L5. This induced voltage causes alternating currents to flow into the second and third windings L4 and L5. Specifically, the positive half-wave portion of the alternating current flows into the second winding L4, while the negative half-wave portion flows into the third winding L5. In other words, currents with opposite phases flow into the second and third windings L4 and L5, respectively. These currents are rectified by the synchronous rectifier switching elements S5 and S6 and charged as positive current into the third smoothing capacitor C3.

[0042] The source terminal of switching element S5 is connected to the second winding L4, and the drain terminal is connected to the positive terminal of the third smoothing capacitor C3. The source terminal of switching element S6 is connected to the third winding L5, and the drain terminal is connected to the positive terminal of the third smoothing capacitor C3. The negative terminal of the third smoothing capacitor C3 is connected to the connection point between the second winding L4 and the third winding L5. In addition, load circuit 2 is connected in parallel with the third smoothing capacitor C3.

[0043] With the above configuration, the switching element S5 functions as a body diode for allowing current to flow from the second winding L4 to the positive terminal of the third smoothing capacitor C3. The switching element S6 also functions as a body diode for allowing current to flow from the third winding L5 to the positive terminal of the third smoothing capacitor C3.

[0044] With the above configuration, even when switching elements S5 and S6 are off, current flows through their body diodes. Therefore, when alternating current flows into first winding L3, current also flows into second winding L4 and third winding L5. The current flowing through the body diodes of switching elements S5 and S6 charges third smoothing capacitor C3. This supplies DC power to load circuit 2 connected to third smoothing capacitor C3.

[0045] Note that in this example, since current flows through the body diodes of switching elements S5 and S6 , there is a forward voltage difference of approximately 1 V. For example, if a current of 10 A flows, loss = forward voltage × current = 10 [W].

[0046] In contrast, if the on-resistance of switching element S5 and switching element S6 when each is on is 0.01Ω, then the loss = current squared × resistance = 10 × 10 × 0.01 = 1 [W]. Therefore, the control circuit 16 can also be configured to turn on switching element S5 and switching element S6 using gate signals G5 and G6 based on the timing at which current flows into the body diodes of switching element S5 and switching element S6, respectively. This reduces conduction loss and enables a highly efficient power converter.

[0047] The isolated ACDC circuit 14 generates a DC voltage VCC, which is insulated from the AC power source AC, based on the AC voltage of the AC power source AC. The DC voltage VCC is a relatively small (several watts) power source used to operate the control circuit 16. The isolated ACDC circuit 14 is connected to the first terminal AC1 and the second terminal AC2 of the filter circuit 11. The isolated ACDC circuit 14 receives a portion of the AC voltage supplied from the first terminal AC1 and the second terminal AC2 of the filter circuit 11 and uses the voltage required for the operation of the control circuit 16 to generate the DC voltage VCC.

[0048] The AC voltage detection circuit 15 detects the AC voltage of the AC power supply AC and supplies the detection result to the control circuit 16. The AC voltage detection circuit 15 is connected to the first terminal AC1 and the second terminal AC2 of the filter circuit 11. That is, the AC voltage detection circuit 15 detects a signal ACV (Alternating Current Voltage) representing the voltage of the AC power supply AC based on the potential of the first terminal AC1 of the filter circuit 11 and the potential of the second terminal AC2 of the filter circuit 11, and supplies it to the control circuit 16. The AC voltage detection circuit 15 can be configured to supply the signal ACV as an analog value to the control circuit 16, or it can be configured to supply the signal ACV as a digital value to the control circuit 16. It should be noted that hereinafter, the potential of the first terminal AC1 of the filter circuit 11 is referred to as AC1, and the potential of the second terminal AC2 of the filter circuit 11 is referred to as AC2.

[0049] The control circuit 16 controls the switching elements of the totem-pole PFC 12 and the LLC resonant circuit 13. The control circuit 16 is comprised of, for example, a microcomputer or a digital signal processor (DSP). The control circuit 16 receives an operating DC voltage VCC from the isolated ACDC circuit 14. Furthermore, the control circuit 16 receives a signal ACV from the AC voltage detection circuit 15. Furthermore, the control circuit 16 receives a signal IS from the current detection circuit 17. As described above, the signal IS represents the potential at the connection point between the first resistor R1 and the source terminal of the first half-wave switch S1, with reference to the connection point GND between the second resistor R2 and the drain terminal of the second half-wave switch S2. Furthermore, the control circuit 16 receives signals DC1 and DC2 from the output terminals of the totem-pole PFC 12.

[0050] Based on the signals ACV, IS, DC1, and DC2, the control circuit 16 generates gate signals G1 and G2 for turning on and off the first half-wave switch S1 and the second half-wave switch S2, and inputs these signals to the totem pole PFC 12. Thus, the control circuit 16 controls the pulse widths of the gate signals G1 and G2 so that the current flowing into the first coil L1 becomes a sinusoidal wave in phase with the input AC voltage.

[0051] Furthermore, the control circuit 16 generates gate signals G3 to G6 for turning on and off the switching elements S3 , S4 , S5 , and S6 based on the output voltage of the LLC resonant circuit 13 , and inputs the gate signals G3 to G6 to the LLC resonant circuit 13 .

[0052] Next, the operation of the totem pole PFC 12 will be described.

[0053] As described above, the totem pole PFC 12 operates based on the gate signal G1 and the gate signal G2 from the control circuit 16. For example, the totem pole PFC 12 Figure 2 The operation is performed while switching between the four states shown.

[0054] The first state is a state where AC1>AC2 (AC1 is positive relative to AC2) and the first half-wave switch S1 is turned off by the gate signal G1 (gate signal G1 is off), and the second half-wave switch S2 is turned on by the gate signal G2 (gate signal G2 is on). In this case, Figure 2As shown, the current flows successively through the first terminal AC1, the first coil L1, the second resistor R2, the second half-wave switch S2, the second diode D2, the first resistor R1, and the second terminal AC2. In this case, the voltage of the first resistor R1 is 0, and the voltage of the second resistor R2 is positive. That is, the potential of the second resistor R2 is positive with respect to the reference point GND. Additionally, since the potential of the first resistor R1 can be regarded as almost the same as that of the second resistor R2, it is positive with respect to the reference point GND. In this case, the signal IS is positive.

[0055] The second state is a state where AC1 > AC2 (AC1 is positive with respect to AC2) and the first half-wave switch S1 is turned off (gate signal G1 is off), and the second half-wave switch S2 is turned off (gate signal G2 is off). In this case, the first half-wave switch S1 functions as a body diode from the source terminal towards the drain terminal. Thus, as Figure 2 shown, the current flows successively through the first terminal AC1, the first coil L1, the first resistor R1, the first half-wave switch S1, the first smoothing capacitor C1, the second diode D2, and the second terminal AC2. In this case, the voltage of the second resistor R2 is 0, and the voltage of the first resistor R1 is negative. That is, the potential of the first resistor R1 is negative with respect to the reference point GND. In this case, the signal IS is negative.

[0056] The totem-pole PFC12 maintains the first half-wave switch S1 in the off state during the period when AC1 > AC2 (AC1 is positive with respect to AC2), and repeatedly turns on and off the second half-wave switch S2 at a high frequency according to the signal G2. Thus, the totem-pole PFC12 repeatedly switches between the first state and the second state during the period when AC1 > AC2 (AC1 is positive with respect to AC2).

[0057] The third state is a state where AC1 < AC2 (AC1 is negative with respect to AC2) and the first half-wave switch S1 is turned on (gate signal G1 is on), and the second half-wave switch S2 is turned off (gate signal G2 is off). In this case, as Figure 2 shown, the current flows successively through the second terminal AC2, the first diode D1, the first half-wave switch S1, the first resistor R1, the first coil L1, and the first terminal AC1. In this case, the voltage of the second resistor R2 is 0, and the voltage of the first resistor R1 is positive. That is, the potential of the first resistor R1 is positive with respect to the reference point GND. In this case, the signal IS is positive.

[0058] The fourth state is a state where AC1 < AC2 (AC1 is negative with respect to AC2) and the first half-wave switch S1 is turned off by the gate signal G1 (the gate signal G1 is off), and the second half-wave switch S2 is turned off by the gate signal G2 (the gate signal G2 is off). In this case, the second half-wave switch S2 functions as a body diode from the source terminal toward the drain terminal. Therefore, as Figure 2 shown, the current flows successively through the second terminal AC2, the first diode D1, the first smoothing capacitor C1, the second half-wave switch S2, the second resistor R2, the first coil L1, and the first terminal AC1. In this case, the voltage of the first resistor R1 is 0, and the voltage of the second resistor R2 is negative. That is, the potential of the second resistor R2 is negative with respect to the reference point GND. In this case, the signal IS is negative.

[0059] During the period when AC1 < AC2 (AC1 is negative with respect to AC2), the totem-pole PFC12 maintains the second half-wave switch S2 in the off state and repeatedly turns on and off the first half-wave switch S1 at a high frequency according to the signal G1. Thus, during the period when AC1 < AC2 (AC1 is negative with respect to AC2), the totem-pole PFC12 repeatedly switches between the third state and the fourth state.

[0060] When AC1 > AC2 (AC1 is positive with respect to AC2), the control circuit 16 turns on and off the second half-wave switch S2. Thus, the control circuit 16 controls so that during the period when AC1 is positive with respect to AC2, the current flowing into the first coil L1 becomes a sine-wave current in phase with the AC voltage ACV of the AC power supply AC. In addition, when AC1 < AC2 (AC1 is negative with respect to AC2), the control circuit 16 turns on and off the first half-wave switch S1. Thus, the control circuit 16 controls so that during the period when AC1 is negative with respect to AC2, the current flowing into the first coil L1 becomes a sine-wave current in phase with the AC voltage ACV of the AC power supply AC. Thereby, the generation of current high-order harmonic noise can be suppressed.

[0061] Next, an example of the detailed structure of the control circuit 16 will be described.

[0062] Figure 3 is an explanatory diagram for explaining an example of the structure of the control circuit 16.

[0063] The control circuit 16 includes a reference voltage conversion circuit 21, a PFC control circuit 22, a first isolation driver 23, and a second isolation driver 24.

[0064] The reference voltage conversion circuit 21 outputs the output voltage of the totem-pole PFC 12 and a signal VFB representing a voltage referenced to GND. In the totem-pole PFC 12, when AC1 > AC2, AC2 and DC2 are at the same potential. Furthermore, when AC1 < AC2, AC1 and DC1 are at the same potential. This causes fluctuations in the reference voltage at the output of the totem-pole PFC 12. Therefore, the reference voltage conversion circuit 21 converts the signals DC1 and DC2 received from the output terminals of the totem-pole PFC 12 into a signal VFB representing a voltage referenced to GND.

[0065] Figure 4 This is an illustrative diagram illustrating an example of the structure of the reference voltage conversion circuit 21. The reference voltage conversion circuit 21 includes multiple resistors and an operational amplifier. The reference voltage conversion circuit 21 divides the potentials of signals DC1 and DC2 using a GND reference, and inputs the divided signals DCD1 and DCD2 into two terminals of the operational amplifier. It should be noted that in this case, the resistor values ​​are determined so that the voltage values ​​after the divided signals do not exceed the DC voltage VCC. That is, signals DCD1 and DCD2 exhibit potentials above GND and below VCC. The operational amplifier outputs the difference between signals DCD1 and DCD2 as signal VFB.

[0066] The reference voltage conversion circuit 21 may also be configured to output the signal VFB using other methods. For example, the reference voltage conversion circuit 21 converts the potential difference between the signals DC1 and DC2 into a pulse width and inputs this pulse into an optocoupler, etc. This generates a pulsed on-current referenced to GND. A voltage corresponding to this pulse width is then generated based on the GND reference. Thus, the potential difference between locations with different potentials can be converted into a GND-referenced signal.

[0067] Figure 5 1 is an explanatory diagram illustrating an example of the configuration of the PFC control circuit 22. The PFC control circuit 22 outputs signals G1G and G2G for controlling the first half-wave switch S1 and the second half-wave switch S2 of the totem pole PFC 12 based on the signals VFB, ACV, and IS. Signals G1G and G2G are signals for controlling the first half-wave switch S1 and the second half-wave switch S2 with reference to the potential of the reference point GND.

[0068] The PFC control circuit 22 includes a low-pass filter 31 , a first comparator 32 , a polarity detection circuit 33 , a voltage detection circuit 34 , an absolute value conversion circuit 35 , a multiplier 36 , a current determiner 37 , a second comparator 38 , a PWM converter 39 , and a selector 40 .

[0069] Signal VFB is input to a low-pass filter 31. Low-pass filter 31 filters (removes) high-frequency components from input signal VFB and inputs the signal to a first comparator 32. Low-pass filter 31 is set to a frequency lower than the AC power supply's 50 Hz frequency, for example. For example, low-pass filter 31 is set to transmit frequency components below 20 Hz. In other words, low-pass filter 31 is configured to filter out frequency components above 20 Hz. This configuration allows low-pass filter 31 to eliminate the 100 Hz (50 Hz full-wave) component generated in first smoothing capacitor C1 and output the average value of the voltage across first smoothing capacitor C1.

[0070] The output of low-pass filter 31 and the reference voltage are input to first comparator 32. First comparator 32 outputs the comparison result between the output of low-pass filter 31 and the reference voltage to multiplier 36. Specifically, first comparator 32 outputs signal VDIF, which is the result of comparing the low-frequency component of signal VFB with the reference voltage. Specifically, first comparator 32 subtracts the reference voltage from the low-frequency component of signal VFB and outputs the result as signal VDIF. In other words, signal VDIF represents the displacement of signal VFB relative to the reference voltage.

[0071] The reference voltage can be set to any value. For example, the reference voltage can be set to 400V. By setting the reference voltage to 400V, it can be compatible with AC voltages worldwide. Since the highest AC voltage in the world is 264V, its peak value is 372V, which is 1.41 times 264V. By setting a higher voltage as the reference voltage, universal power conversion can be achieved.

[0072] Polarity detection circuit 33 detects the polarity of the AC voltage supplied from AC power supply AC based on signal ACV and outputs the detection result as signal ACP. Polarity detection circuit 33 outputs signal ACP to current determiner 37 and selector 40. Polarity detection circuit 33 outputs a logical value, either "0" or "1," as signal ACP, based on whether the value of signal ACV is positive or negative. For example, assume that signal ACV represents the potential of first terminal AC1 of filter circuit 11 relative to second terminal AC2. In this case, polarity detection circuit 33 outputs signal ACP of "1" when signal ACV is positive and outputs signal ACP of "0" when signal ACV is negative. That is, polarity detection circuit 33 outputs signal ACP of "1" when the potential of first terminal AC1 is greater than the potential of second terminal AC2, and outputs signal ACP of "0" when the potential of first terminal AC1 is less than the potential of second terminal AC2.

[0073] The voltage detection circuit 34 converts the signal ACV into a voltage signal of arbitrary amplitude and outputs it to the absolute value conversion circuit 35. When the AC power source AC has an effective value of 100V, the instantaneous value of the signal ACV input to the voltage detection circuit 34 is between -141V and 141V. The voltage detection circuit 34 converts the instantaneous value of the AC voltage of the AC power source AC, indicated by the signal ACV, to a value within a predetermined range. In other words, the voltage detection circuit 34 normalizes the instantaneous value of the AC voltage of the AC power source AC, indicated by the signal ACV. Specifically, the voltage detection circuit 34 converts the instantaneous value of the AC voltage of the AC power source AC, indicated by the signal ACV, to an instantaneous value within the range of -1 to 1. Based on the signal ACV converted by the voltage detection circuit 34, the phase of the sinusoidal waveform can be determined. In other words, the signal ACV normalized by the voltage detection circuit 34 can be referred to as sinusoidal phase information, indicating the phase of the sinusoidal wave.

[0074] Absolute value conversion circuit 35 converts signal ACV output from voltage detection circuit 34 into signal ABS, which is an absolute value signal, and outputs signal ABS to multiplier 36. Absolute value conversion circuit 35 converts signal ACV output from voltage detection circuit 34 into an absolute value, thereby converting it into a signal with a value of 0 to 1 (a full-wave rectified signal).

[0075] The multiplier 36 multiplies the signal VDIF supplied from the first comparator 32 by the signal ABS supplied from the absolute value conversion circuit 35. The multiplier 36 outputs the result of the multiplication of the signals VDIF and ABS as a signal AIM to the second comparator 38. The signal AIM indicates a target current value.

[0076] Signals ACP, IS, G1G, and G2G are input to current determiner 37. Current determiner 37 detects signal IS when signal G1G or G2G pulses. Specifically, current determiner 37 extracts a signal from input signal IS during the period when signal G1G or G2G is on, and obtains extracted signal ISE. Extracted signal ISE is the value of signal IS when signal G1G or G2G is on. In other words, extracted signal ISE is a positive value relative to the GND voltage of signal IS. Therefore, extracted signal ISE has a discrete waveform. That is, there are times when extracted signal ISE has no value.

[0077] Current determiner 37 performs interpolation processing based on extracted signal ISE to obtain interpolated signal ISI as a continuous waveform. Specifically, current determiner 37 interpolates values ​​at times when extracted signal ISE is absent, and calculates interpolated signal ISI. In other words, current determiner 37 calculates values ​​at times when extracted signal ISE is absent by performing linear interpolation or some other mathematical approximation based on past values ​​of extracted signal ISE. As a result, interpolated signal ISI approximates the current actually flowing into first coil L1. Current determiner 37 outputs interpolated signal ISI to second comparator 38.

[0078] Signal AIM and interpolation signal ISI are input to second comparator 38. Second comparator 38 outputs signal IDIF, which is a comparison result of signal AIM and interpolation signal ISI, to PWM converter 39. Signal IDIF represents the difference between signal AIM, which is a target current value, and interpolation signal ISI, which approximates the actual current flowing.

[0079] PWM converter 39 generates signal PWM, which is a pulse width modulation signal, based on the value of signal IDIF, and outputs signal PWM to selector 40. For example, PWM converter 39 performs modulation such that the pulse width is increased when the actual current flowing is smaller than the target current value, and the pulse width is decreased when the actual current flowing is larger than the target current value.

[0080] The signal ACP and the signal PWM are input to the selector 40. Based on the signal ACP, the selector 40 switches between outputting the signal PWM as the signal G1G to the first insulation driver 23 and the current determiner 37, or outputting the signal PWM as the signal G2G to the second insulation driver 24 and the current determiner 37. Specifically, when the signal ACP is "1", the selector 40 outputs the signal PWM as the signal G2G to the second insulation driver 24 and the current determiner 37. In addition, when the signal ACP is "0", the selector 40 outputs the signal PWM as the signal G1G to the first insulation driver 23 and the current determiner 37. It should be noted that the signal PWM, i.e., the signal G1G and the signal G2G, are GND reference signals. The signal supplied to the side of the first insulation driver 23 and the second insulation driver 24 to which the signal PWM is not output is "0 (stop signal)".

[0081] The first isolation driver 23 and the second isolation driver 24 isolate a signal input to the primary side and output it from the secondary side.

[0082] Figure 61 is an explanatory diagram for explaining an example of the structure of the first insulating driver 23 and the second insulating driver 24. The first insulating driver 23 and the second insulating driver 24 each include a pulse transformer 41. The pulse transformer 41 includes a primary winding, a secondary winding, and a magnetic core.

[0083] like Figure 6 As shown, the primary winding of the pulse transformer 41 of the first isolation driver 23 is connected to G1G and GND, which are GND references. The secondary winding of the pulse transformer 41 is connected to G1, which is G1GND reference. Specifically, the selector 40 of the totem pole PFC 12 and GND are connected to the primary winding of the pulse transformer 41. Furthermore, the gate terminal and source terminal of the first half-wave switch S1 are connected to the secondary winding of the pulse transformer 41.

[0084] According to the above configuration, signal G1G, a pulsed signal with a GND reference output from the totem-pole PFC 12, is input to the primary winding of the pulse transformer 41 of the first isolation driver 23. When signal G1G, with a GND reference, is input to the primary winding of the pulse transformer 41, an induced voltage is generated in the secondary winding of the pulse transformer 41. This induced voltage causes signal G1, a pulsed signal corresponding to signal G1G and with a reference to the potential G1GND at the source terminal of the first half-wave switch S1, to be input from the secondary winding of the pulse transformer 41 to the gate terminal of the first half-wave switch S1. Consequently, the first half-wave switch S1 is turned on and off based on signal G1.

[0085] like Figure 6 As shown, the primary winding of the pulse transformer 41 of the second isolation driver 24 is connected to G2G and GND, which are GND references. The secondary winding of the pulse transformer 41 is connected to G2, which is G2GND reference. Specifically, the selector 40 of the totem pole PFC 12 and GND are connected to the primary winding of the pulse transformer 41. Furthermore, the gate terminal and source terminal of the second half-wave switch S2 are connected to the secondary winding of the pulse transformer 41.

[0086] According to the above configuration, signal G2G, a pulse signal with a GND reference output from totem-pole PFC 12, is input to the primary winding of pulse transformer 41 of second isolation driver 24. When signal G2G, with a GND reference, is input to the primary winding of pulse transformer 41, an induced voltage is generated in the secondary winding of pulse transformer 41. This induced voltage causes signal G2, a pulse signal corresponding to signal G2G and with a reference to the potential G2GND at the source terminal of second half-wave switch S2, to be input from the secondary winding of pulse transformer 41 to the gate terminal of second half-wave switch S2.

[0087] In addition, the first insulating driver 23 and the second insulating driver 24 may further include a filter capacitor, which is connected in series with the winding on the primary side of the pulse transformer 41 and filters out a DC component.

[0088] Signals G1 and G2 are positive and negative signals centered around G1GND and G2GND, respectively. Therefore, the turns ratio of the pulse transformer 41 coil can be adjusted to double the values ​​of signals G1 and G2 (to the same voltage as the primary side).

[0089] In addition, the first insulating driver 23 and the second insulating driver 24 may further include a filter capacitor, which is connected in series with the coil on the secondary side of the pulse transformer 41 and filters out a DC component.

[0090] Alternatively, the first and second isolation drivers 23 and 24 may use photocouplers to convert signals G1G and G2G into signals G1 and G2 based on G1GND and G2GND. Since the signals output from the photocouplers are weak, buffer circuits may be further provided.

[0091] In addition, the first insulating driver 23 and the second insulating driver 24 can also use a bootstrap method to boost the signal output from the photocoupler through a DC power supply for boosting, and input it to the gate terminal of the second half-wave switch S2. For example, when the signal G2 is turned on, the potential of G1GND is equal to the potential of G2GND. When a DC power supply for boosting is connected to the G2GND side, the potential of the DC power supply for boosting is also supplied to G1GND via the body diode of the second half-wave switch S2. Then, when the signal G2 is turned off, the potential of G1GND is different from the potential of G2GND, but the potential of the G1GND reference is retained. This potential can also be used to amplify the signal output from the photocoupler and input it to the gate terminal of the first half-wave switch S1.

[0092] Figure 7 1 is an explanatory diagram for explaining the relationship between the voltage of the AC power supply AC and the current flowing through the totem pole PFC 12. Figure 7 , there are shown examples of a signal ACV indicating the voltage of an AC power source AC, a signal ACP indicating a polarity detection result, a signal G1 (G1G) input to the gate terminal of a first half-wave switch S1, a signal G2 (G2G) input to the gate terminal of a second half-wave switch S2, a voltage applied to a first resistor R1, a voltage applied to a second resistor R2, a signal IS, an extraction signal ISE, and an interpolation signal ISI. Figure 7In the example, between time t0 and time t1, the polarity is positive (AC1 > AC2), between time t1 and time t2, the polarity is negative (AC1 < AC2), and after time t2, the polarity is positive again (AC1 > AC2).

[0093] As described above, the polarity detection circuit 33 outputs a signal ACP with a logic value of "1" during the period when AC1 > AC2, and outputs a signal ACP with a logic value of "0" during the period when AC1 < AC2.

[0094] In addition, the control circuit 16 of the totem-pole PFC 12 sequentially calculates a signal AIM representing the target current based on a signal VFB representing the output voltage of the totem-pole PFC 12 and an ACV representing the AC voltage.

[0095] During the period when AC1 > AC2, the control circuit 16 generates a signal PWM based on a signal IDIF which is the comparison result between the signal AIM and the above-mentioned interpolation signal ISI. That is, the control circuit 16 generates the signal PWM to make the difference between the signal AIM and the interpolation signal ISI smaller, and inputs the signal PWM as a signal G2 to the gate terminal of the second half-wave switch S2. Thus, during the period when AC1 > AC2, the totem-pole PFC 12 turns on and off the second half-wave switch S2 through the signal G2. Thus, the totem-pole PFC 12 switches between the first state and the second state according to the signal G2 in Figure 2 the first state and the second state shown.

[0096] The totem-pole PFC 12 controls the lengths of the first state and the second state by performing pulse-width control. Specifically, the totem-pole PFC 12 has a fixed frequency, and controls the ON duty ratio of the signal G2 corresponding to the length of the first state within one period. Thus, the length of the second state obtained by subtracting the length of the first state from the length within one period is also determined at the same time. In this way, the totem-pole PFC 12 can switch between the first state and the second state multiple times while making the signal AIM, which is the target waveform of the interpolation signal ISI, close to the interpolation signal ISI.

[0097] In addition, during the period when AC1 < AC2, the control circuit 16 generates a signal PWM based on a signal IDIF which is the comparison result between the signal AIM and the above-mentioned interpolation signal ISI. That is, the control circuit 16 generates the signal PWM to make the difference between the signal AIM and the interpolation signal ISI smaller, and inputs the signal PWM as a signal G1 to the gate terminal of the first half-wave switch S1. Thus, during the period when AC1 < AC2, the totem-pole PFC 12 turns on and off the first half-wave switch S1 through the signal G1. Thus, the totem-pole PFC 12 switches between the third state and the fourth state according to the signal G1 in Figure 2

[0098] In addition, the totem-pole PFC 12 controls the lengths of the third state and the fourth state by performing pulse-width control. Specifically, the totem-pole PFC 12 has a fixed frequency and controls the ON duty ratio of the signal G1, which corresponds to the length of the third state within one period. Thereby, the length of the fourth state, which is obtained by subtracting the length of the third state from the length within one period, is also determined simultaneously.

[0099] In the first state, the voltage of the first resistor R1 is 0, and the voltage of the second resistor R2 is positive. In the second state, the voltage of the second resistor R2 is 0, and the voltage of the first resistor R1 is negative. In the third state, the voltage of the second resistor R2 is 0, and the voltage of the first resistor R1 is positive. In the fourth state, the voltage of the first resistor R1 is 0, and the voltage of the second resistor R2 is negative. That is, as Figure 7 shown, the positive component of the detection results of the voltages of the first resistor R1 as the first current detector and the second resistor R2 as the second current detector is a half-wave pulsating voltage (half-wave pulsating voltage). In addition, the positive component of the detection result of the first resistor R1 as the first current detector and the positive component of the voltage detection result of the second resistor R2 differ in phase by 180 degrees. The signal IS is a signal generated at both ends of the series combination resistance of the first resistor R1 and the second resistor R2. Therefore, as Figure 7 shown, it is a waveform (double-wave pulsating voltage) synthesized by adding the voltages of the first resistor R1 and the second resistor R2. That is, the signal IS is a signal obtained by adding the detection result of the first resistor R1 as the first current detector and the voltage detection result of the second resistor R2 as the second current detector, and the positive component is a full-wave pulsating voltage.

[0100] The extraction signal ISE is the signal IS during the period when the signal G1G is on or the signal G2G is on. During the period when AC1 < AC2, the signal G1G is off, and the power conversion device 1 operates by the on and off of the signal G2G. The current determiner 37 obtains the signal IS during the period when the signal G2G is on as the extraction signal ISE during the period when AC1 < AC2. During the period when AC1 < AC2 and the signal G2G is on, the signal IS is positive. Thereby, the current determiner 37 can extract the positive value of the signal IS as the extraction signal ISE.

[0101] In addition, during the period when AC1 > AC2, the signal G2G is off, and the power conversion device 1 operates by the on and off of the signal G1G. The current determiner 37 obtains the signal IS during the period when the signal G1G is on as the extraction signal ISE during the period when AC1 > AC2. During the period when AC1 > AC2 and the signal G1G is on, the signal IS is positive. Thereby, the current determiner 37 can extract the positive value of the signal IS as the extraction signal ISE.

[0102] Furthermore, current determiner 37 includes a structure (circuitry) for performing interpolation processing based on extracted signal ISE to obtain (generate) interpolated signal ISI as a continuous waveform. For example, current determiner 37 interpolates the blank values ​​in extracted signal ISE using linear interpolation or some other mathematical approximation. This allows current determiner 37 to output a signal corresponding to the actual current flowing into first coil L1 as interpolated signal ISI.

[0103] As described above, the power conversion device 1 includes the totem pole power factor correction circuit (totem pole PFC) 12 , the current detection circuit 17 , and the control circuit 16 .

[0104] The totem-pole PFC 12 includes a first coil L1 connected to a first terminal AC1 of an AC power source AC, and a first half-wave switch S1 having its source terminal connected to the first coil L1 via a first resistor R1 serving as a first current detector. The totem-pole PFC 12 includes a second half-wave switch S2 having its drain terminal connected to the first coil L1 via a second resistor R2 serving as a second current detector. The first resistor R1 and the second resistor R2 constitute a current detection circuit 17. The totem-pole PFC 12 includes a first diode D1, whose cathode is connected to the drain terminal of the first half-wave switch S1 and whose anode is connected to a second terminal AC2 of the AC power source AC; and a second diode D2, whose anode is connected to the source terminal of the second half-wave switch S2 and whose cathode is connected to the second terminal AC2 of the AC power source AC. The totem-pole PFC 12 includes a first smoothing capacitor C1 connected between the cathode of the first diode D1 and the anode of the second diode D2.

[0105] The control circuit 16 performs pulse width control for turning on and off the first half-wave switch S1 and the second half-wave switch S2 based on a signal IS indicating the total value of the DC voltage applied to the first resistor R1 and the DC voltage applied to the second resistor R2.

[0106] With this configuration, the current flowing through first coil L1 appears at the positive side of signal IS. By controlling the on and off of first and second half-wave switches S1 and S2 based on signal IS, control circuit 16 can control the current flowing into first coil L1 to a sinusoidal wave with the same phase as the voltage of AC power supply AC. As a result, power converter 1 can achieve high-efficiency power conversion with a simple configuration.

[0107] In addition, the control circuit 16 obtains the signal IS, which is the sum of the DC voltage detection results of the first resistor R1 and the second resistor R2, based on the voltage GND voltage at the connection point of the drain terminal of the second half-wave switch S2 and the second resistor R2.

[0108] In addition, the control circuit 16 extracts a positive-side value based on the GND voltage as an extraction signal according to the total value, and performs pulse-width control of turning on and off the first half-wave switch S1 and the second half-wave switch S2 based on the extraction signal.

[0109] In addition, in the case where there is no value of the extraction signal, the control circuit 16 calculates an interpolation signal through interpolation processing based on the value of the past extraction signal, and performs pulse-width control of turning on and off the first half-wave switch S1 and the second half-wave switch S2 based on the interpolation signal. Thereby, the power conversion device 1 can perform efficient power conversion with a simple structure.

[0110] It should be noted that although it is described in the above embodiment that the second half-wave switch S2 is turned on and off during the period when AC1>AC2, and the first half-wave switch S2 is turned on and off during the period when AC1<AC2, the present invention is not limited to this structure. The control circuit 16 can be configured to turn on the first half-wave switch S1 during the period when AC1>AC2 and the second half-wave switch S2 is off, and turn on the second half-wave switch S2 during the period when AC1<AC2 and the first half-wave switch S1 is off. That is, the control circuit 16 can be configured to perform synchronous rectification through the first half-wave switch S1 and the second half-wave switch S2.

[0111] During the period when AC1>AC2 and the second half-wave switch S2 is off, the first half-wave switch S1 functions as a body diode from the source terminal toward the drain terminal. In addition, during the period when AC1<AC2 and the first half-wave switch S1 is off, the second half-wave switch S2 functions as a body diode from the source terminal toward the drain terminal.

[0112] However, the loss when the first half-wave switch S1 is on is smaller than the loss of the body diode of the first half-wave switch S1. In addition, the loss when the second half-wave switch S2 is on is smaller than the loss of the body diode of the second half-wave switch S2. Therefore, as described above, during the period when AC1>AC2 and the second half-wave switch S2 is off, the first half-wave switch S1 is turned on, and during the period when AC1<AC2 and the first half-wave switch S1 is off, the second half-wave switch S2 is turned on, thereby reducing the circuit loss of the totem-pole PFC 12.

[0113] It should be noted that in the case of performing synchronous rectification as described above, pulses appear alternately in the signals G1G and the signal G2G. Therefore, the current determiner 37 of the control circuit 16 cannot extract the extraction signal ISE from the signal IS based on the signals G1G and G2G. Therefore, the current determiner 37 switches whether to use the signal G1G or the signal G2G to extract the extraction signal ISE based on the signal ACP from the polarity detection circuit 33.

[0114] Specifically, during the period when the first terminal AC1 of the AC power supply AC is at a positive potential and the second half-wave switch S2 is turned on, the current determiner 37 extracts an extraction signal ISE from the signal IS. Additionally, during the period when the second terminal AC2 of the AC power supply AC is at a positive potential and the first half-wave switch S1 is turned on, the current determiner 37 extracts an extraction signal ISE from the signal IS. Thus, the control circuit 16 can extract an extraction signal ISE from the signal IS.

[0115] Additionally, similarly, the first diode D1 and the second diode D2 can be respectively replaced with MOSFETs. Specifically, the first diode D1 can be configured as the body diode of a FET that is turned on during the period when AC1 > AC2 and turned off during the period when AC1 < AC2. Additionally, specifically, the second diode D2 can be configured as the body diode of a FET that is turned off during the period when AC1 > AC2 and turned on during the period when AC1 < AC2. With such a structure, the circuit loss of the totem-pole PFC12 can also be reduced.

[0116] It should be noted that the first half-wave switch S1 and the second half-wave switch S2 in the above-described embodiment need to be composed of a wide-bandgap semiconductor for high-speed switching. However, since the current flowing into the first diode D1 and the second diode D2 is a 50 Hz component, which is the frequency of the AC power supply AC, in the case of using synchronous rectification FETs instead of the first diode D1 and the second diode D2, FETs composed of a slower-responding silicon semiconductor can be used.

[0117] In the case of using synchronous rectification FETs instead of the first diode D1 and the second diode D2, the cathode side of the first diode D1 and the second diode D2 is replaced with the drain terminal of the FET, and the anode side of the first diode D1 and the second diode D2 is replaced with the source terminal of the FET.

[0118] It should be noted that in the above-described embodiment, it is described that the polarity detection circuit 33 is configured to detect the polarity of the AC voltage supplied from the AC power supply AC based on the signal ACV and output the detection result as the signal ACP. The polarity detection circuit 33 can be implemented either by a combination of a processor and a memory storing a program or by an analog circuit.

[0119] When the polarity detection circuit 33 is configured as an analog circuit, for example, it becomes Figure 8 the structure shown. In Figure 8 the example, the polarity detection circuit 33 is provided outside the control circuit 16 and outputs the signal ACP to the current determiner 37 and the selector 40 of the control circuit 16. The polarity detection circuit 33 includes, for example, a third diode D3, a fourth diode D4, a first opto-coupler PC1, a second opto-coupler PC2, and a logic circuit 51.

[0120] The cathode of the third diode D3 is connected to the first terminal AC1 of the filter circuit 11, and the anode is connected to the cathode of the first opto-coupler PC1. The anode of the first opto-coupler PC1 is connected to the second terminal AC2 of the filter circuit 11 via a resistor, the collector is connected to GND, and the emitter is connected to the logic circuit 51.

[0121] The anode of the fourth diode D4 is connected to the first terminal AC1 of the filter circuit 11, and the cathode is connected to the anode of the second opto-coupler PC2. The cathode of the second opto-coupler PC2 is connected to the second terminal AC2 of the filter circuit 11 via a resistor, the collector is connected to GND, and the emitter is connected to the logic circuit 51.

[0122] According to the above structure, when AC1 < AC2, the first opto-coupler PC1 allows current to flow from the anode to the cathode and outputs the signal P1 to the logic circuit 51. When AC1 > AC2, the second opto-coupler PC2 allows current to flow from the anode to the cathode and outputs the signal P2 to the logic circuit 51.

[0123] The logic circuit 51 is a circuit that outputs the signal ACP representing "1" during the period when the signal P2 is supplied from the second opto-coupler PC2, and outputs the signal ACP representing "0" during the period when the signal P1 is supplied from the first opto-coupler PC1. For example, the logic circuit 51 includes one NAND and two ANDs. The signals P1 and P2 are input to the NAND. The output of the NAND and the signal P2 are input to the first AND. The output of the NAND and the signal P1 are input to the second AND.

[0124] According to this structure, when the signal P2 is input and the signal P1 is not input, the first AND outputs "1". When the signal P1 is input and the signal P2 is not input, the first AND outputs "0". That is, the output of the first AND is supplied as the signal ACP to the current determiner 37 and the selector 40 of the control circuit 16. In addition, when the signal P1 is input and the signal P2 is not input, the second AND outputs "1". When the signal P2 is input and the signal P1 is not input, the first AND outputs "0". That is, the output of the first AND becomes the inverse of the signal ACP.

[0125] In addition, for other circuits of the control circuit 16, they can also be implemented by a combination of a logic circuit or a processor and a program instead of an analog circuit.

[0126] For example, the first comparator 32 and the second comparator 38 can also be configured to convert the two input signals into digital signals respectively using AD conversion or the like, and calculate the difference through digital values. The first comparator 32 and the second comparator 38 are implemented by the following code, for example.

[0127] Sout = f(Sin1, Sin2)

[0128] {

[0129] Sout = Sin1 - Sin2;

[0130] }

[0131] In addition, the multiplier 36 can also be configured to convert the two input signals into digital signals respectively using AD conversion or the like, and perform a multiplication operation using digital values. The multiplier 36 is implemented by the following code, for example.

[0132] MUL = f(Sin1, Sin2)

[0133] {

[0134] MUL = Sin1 * Sin2;

[0135] } [[ID=二十六]]

[0136] As described above, in the case of implementation by a combination of a processor and a program, the input signal is converted into a digital signal using AD conversion or the like, and an operation is performed based on the digital value. Furthermore, in the case where the subsequent circuit is an analog circuit, the digital signal can also be converted into an analog signal and output using DA conversion or the like.

[0137] In addition, in the above-described embodiment, the control circuit 16 is described as an arithmetic IC such as a microcomputer or a digital signal processor. Therefore, the signal IS input to the control circuit 16 is limited to the voltage between GND and VCC. That is, the control circuit 16 cannot process the negative value of the signal IS.

[0138] However, for example, as Figure 9 shown, when the GND of the control circuit 16 is not 0V but a negative value (for example, -5V), that is, the control circuit 16 is configured as an IC that operates within the range of VCC (+5V) to NVCC (-5V). In this case, if the signal IS satisfies NVCC < IS < VCC, the control circuit 16 can calculate the absolute value of the signal IS, and based on the calculated absolute value of the signal IS, perform pulse width control for turning on and off the first half-wave switch S1 and the second half-wave switch S2.

[0139] Although several embodiments of the present invention have been described, these embodiments are presented only as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the invention described in the claims and its equivalents.

Claims

1. A power conversion device, characterized in that: include: A totem pole power factor improvement circuit includes: a coil connected to a first terminal of an AC power supply; a first half-wave switch, a source terminal of the first half-wave switch connected to the coil via a first current detector; a second half-wave switch, a drain terminal of the second half-wave switch connected to the coil via a second current detector; a first diode, a cathode of the first diode connected to the drain terminal of the first half-wave switch, and an anode of the first diode connected to the second terminal of the AC power supply; a second diode, an anode of the second diode connected to the source terminal of the second half-wave switch, and a cathode of the second diode connected to the second terminal of the AC power supply; and a smoothing capacitor connected between the cathode of the first diode and the anode of the second diode; and a control circuit that performs pulse width control for turning on and off the first half-wave switch and the second half-wave switch based on a total value of a DC voltage detection result of the first current detector and a DC voltage detection result of the second current detector, The control circuit obtains the detection results of the DC voltage of the first current detector and the detection results of the DC voltage of the second current detector based on the voltage of the connection point between the drain terminal of the second half-wave switch and the second current detector, that is, the GND voltage, as a reference. The control circuit extracts a positive value based on the GND voltage as an extraction signal from the total value, and performs pulse width control for turning on and off the first half-wave switch and the second half-wave switch based on the extraction signal.

2. The power conversion device according to claim 1, wherein: In the absence of the value of the extraction signal, the control circuit calculates an interpolation signal through interpolation processing based on past values ​​of the extraction signal, and performs pulse width control to turn on and off the first half-wave switch and the second half-wave switch based on the interpolation signal.

3. The power conversion device according to claim 1 or 2, characterized in that: The power conversion device includes a polarity detection circuit that detects the polarity of the AC voltage supplied from the AC power supply. The control circuit extracts the extraction signal based on the total value during a period when the first terminal of the AC power supply is at a positive potential and the second half-wave switch is turned on, or during a period when the second terminal of the AC power supply is at a positive potential and the first half-wave switch is turned on. During a period when the first terminal of the AC power supply is at a positive potential and the second half-wave switch is off, the control circuit turns on the first half-wave switch. The control circuit turns on the second half-wave switch during a period in which the second terminal of the AC power supply is at a positive potential and the first half-wave switch is turned off.

4. The power conversion device according to claim 1, wherein: The control circuit calculates an absolute value of the total value based on the positive or negative sign of the total value with reference to the GND voltage, and performs pulse width control for turning on and off the first half-wave switch and the second half-wave switch based on the absolute value.

5. The power conversion device according to claim 1, wherein: The control circuit converts the voltage across the smoothing capacitor into a voltage based on the GND voltage, and performs the pulse width control based on the converted voltage.

6. The power conversion device according to claim 1, wherein: A positive terminal and a negative terminal of the smoothing capacitor are connected to the control circuit, respectively.

7. The power conversion device according to claim 1, wherein: The totem pole power factor improvement circuit includes a current detection circuit that supplies a signal indicating a value of a current flowing in the first coil to the control circuit.

8. The power conversion device according to claim 7, characterized in that: The current detection circuit includes a first resistor functioning as the first current detector and a second resistor functioning as the second current detector.

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