Voltage comparator and method

Abstract

A voltage comparator and method are disclosed. One embodiment of the electronic device includes: a first circuit including a first transistor and a second transistor series coupled between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through the first node; and a second circuit configured to compare a first voltage at the first node with a first voltage threshold and a second voltage threshold.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Application No. 2008088, filed on July 30, 2020, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic devices, and more specifically, to devices including circuitry configured to determine whether a voltage is within a determined range, such as a switch-mode power supply type DC / DC voltage converter including such circuitry, converting a DC power supply voltage to a DC output voltage, such as a buck DC / DC voltage converter, wherein the value of the DC output voltage is lower than the value of the DC power supply voltage. Background Technology

[0004] In a switch-mode power converter, the DC voltage used to power the converter is chopped by switching, in order to achieve a power storage phase in the components including inductive and capacitive elements and a phase of transferring the power stored in the components to the load connected to the converter output.

[0005] In a pulse frequency modulation (PFM) type switch-mode converter, each operating cycle of the converter includes a phase of storing power in the components, followed by a phase of delivering power to the load connected to the converter. During the power storage phase, the current flowing through the inductor increases. During the power delivery phase, the current flowing through the inductor decreases. For each operating cycle, it is desirable that the current flowing through the inductor is zero at the beginning of the power storage phase and at the end of the power delivery phase.

[0006] Known switch-mode converters, especially PFM converters, have various drawbacks. Summary of the Invention

[0007] One embodiment overcomes all or part of the disadvantages of known devices that include circuits configured to determine the sign of a current.

[0008] An embodiment of an electronic device includes: a first circuit including a first transistor and a second transistor series coupled between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through the first node; and a second circuit configured to compare a first voltage at the first node with a first voltage threshold and a second voltage threshold.

[0009] An embodiment of a method for controlling an electronic device includes: a first circuit including a first transistor and a second transistor series coupled between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through the first node; and a second circuit for comparing a first voltage at the first node with a first voltage threshold and a second voltage threshold.

[0010] According to one embodiment, the second circuit includes a third transistor and a fourth transistor coupled in series between a second node and a third node, the third transistor and the fourth transistor being coupled to each other through a fourth node, the fourth node being coupled to the first node.

[0011] According to one embodiment, the second node is coupled to the node to which the power supply voltage is applied via a first resistive element, and the third node is coupled to the node to which the reference voltage is applied via a second resistive element.

[0012] According to one embodiment, the control terminal of the third transistor is coupled to the node to which the second voltage threshold is applied, and the control terminal of the fourth transistor is coupled to the node to which the first voltage threshold is applied.

[0013] According to one embodiment, the first voltage threshold is the power supply voltage, and the second voltage threshold is a reference voltage.

[0014] According to one embodiment, the second circuit includes: a first output node having a signal that takes a first value when a first voltage is greater than a first voltage threshold and takes a second value when the first voltage is less than the first voltage threshold; and a second output node having a signal that takes a first value when the first voltage is less than the second voltage threshold and takes a second value when the first voltage is greater than the second voltage threshold.

[0015] According to one embodiment, the first output node is coupled to the second node, and the second output node is coupled to the third node.

[0016] According to one embodiment, the first output node is coupled to the second node via an inverter circuit, and the second output node is coupled to the third node via two inverter circuits.

[0017] According to one embodiment, a first transistor is connected in parallel with a first diode, a second transistor is connected in parallel with a second diode, and the anode of the first diode and the cathode of the second diode are connected to a first node.

[0018] According to one embodiment, the device is a switch-mode power supply.

[0019] According to one embodiment, the device includes a third circuit configured to compare a first voltage with a second voltage, the second voltage being variable and dependent on signals at the first and second output nodes.

[0020] According to one embodiment, the device includes a fourth circuit configured to control a first transistor and a second transistor in such a way that each operating cycle continuously includes: a first phase during which the first transistor is turned on and the second transistor is turned off; a second phase during which the first transistor and the second transistor are turned off; a third phase during which the first transistor is turned off and the second transistor is turned on; and a fourth phase during which the first transistor and the second transistor are turned off.

[0021] According to one embodiment, the change in the second voltage depends on the signals at the first and second output nodes during the fourth phase. Attached Figure Description

[0022] The above-described features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration rather than limitation with reference to the accompanying drawings, in which:

[0023] Figure 1 An embodiment of an electronic device is shown, including circuitry configured to determine whether a voltage is within a voltage range;

[0024] Figure 2 It shows Figure 1 A timing diagram of the operation of an embodiment;

[0025] Figure 3 It shows Figure 1 A timing diagram of the operation of an embodiment;

[0026] Figure 4 An embodiment of a DC / DC voltage converter is schematically illustrated;

[0027] Figure 5 The timing diagram is shown, illustrating... Figure 4 Example of converter operation;

[0028] Figure 6 Other timing diagrams are shown, illustrating Figure 4 The expected or theoretical operation and the actual or practical operation of the converter;

[0029] Figure 7 Shown include Figure 1 An embodiment of the DC / DC voltage converter; and

[0030] Figure 8 It shows Figure 7 A timing diagram of an operational example of an embodiment. Detailed Implementation

[0031] In different figures, the same features are designated by the same reference. In particular, common structural and / or functional features in various embodiments may have the same reference and may be provided with the same structure, dimensions, and material properties.

[0032] For clarity, only the steps and elements useful for understanding the embodiments described herein are described in detail.

[0033] Unless otherwise stated, when referring to two elements connected together, it means there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected, or they can be coupled through one or more other elements.

[0034] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative position qualifiers such as the terms “above,” “below,” “higher,” “lower,” etc., or orientation qualifiers such as “horizontal,” “vertical,” etc., the orientation shown in the figure shall be used.

[0035] Unless otherwise stated, “about,” “approximately,” “substantially,” and “approximately” mean within 10%, preferably within 5%.

[0036] Figure 1 An electronic device including an embodiment of circuit 10 is shown, the circuit 10 being configured to determine whether an input voltage is within a voltage range. In other words, circuit 10 is configured to compare the input voltage with a first voltage threshold and a second voltage threshold, which are different from each other.

[0037] The device includes circuit 20, such as a power stage. Circuit 20 is an example of a circuit configured to generate the input voltage of circuit 10. Circuit 20 includes two transistors 202 and 204. Transistors 202 and 204 are coupled (preferably in series) between rail 3, where a supply voltage Vbat is applied, and rail 5, where a reference voltage (e.g., ground GND) is applied. In other words, one conductive terminal (source or drain) of transistor 202 is coupled (preferably connected) to rail 3, while the other conductive terminal (drain or source) is coupled (preferably connected) to center node 206. One conductive terminal (source or drain) of transistor 204 is coupled (preferably connected) to node 206, and its other conductive terminal (drain or source) is coupled (preferably connected) to rail 5.

[0038] Preferably, transistor 202 is a P-type field-effect transistor or a PMOS transistor, and transistor 204 is an N-type field-effect transistor or an NMOS transistor.

[0039] Circuit 20 includes two inputs, 208 and 210. Input 208 receives a signal GP for controlling transistor 202. Therefore, input 208 is coupled (preferably connected) to the control terminal or gate of transistor 202. Input 210 receives a control signal GN of transistor 204. Therefore, input 210 is coupled (preferably connected) to the control terminal or gate of transistor 204.

[0040] Node 206 is coupled (preferably connected) to input node 102 of circuit 10. A current Ic is supplied to the input of circuit 10 through nodes 206 and 102. Similarly, a voltage VLX at node 206 is supplied to input node 102 of circuit 10. In operation, node 206 may be coupled to a load, for example, powered by circuit 20.

[0041] Circuit 20 also includes two diodes, 218 and 220. Diodes 218 and 220 are coupled in series between rails 3 and 5. More specifically, the first terminal (anode or cathode) of diode 220 is coupled (preferably connected) to rail 5, and the second terminal (cathode or anode) of diode 220 is coupled (preferably connected) to node 206. The first terminal (anode or cathode) of diode 218 is coupled (preferably connected) to node 206, and the second terminal (cathode or anode) of diode 218 is coupled (preferably connected) to rail 3. Figure 1 In the example, the first terminals of diodes 218 and 220 are anodes, and the second terminals of diodes 218 and 220 are cathodes. Node 206 is thus coupled to the anode of one diode and the cathode of the other diode.

[0042] In other words, each diode is coupled (preferably connected) in parallel with one of transistors 202 and 204. For example, the anode of diode 218 is coupled (preferably connected) to the source of transistor 202, and the cathode of diode 218 is coupled (preferably connected) to the drain of transistor 202. Similarly, the anode of diode 220 is coupled (preferably connected) to the source of transistor 204, and the cathode of diode 220 is coupled (preferably connected) to the drain of transistor 204. For example, the cathode of diode 218 is also coupled (preferably connected) to the substrate of transistor 202. The anode of diode 220 is also, for example, coupled (preferably connected) to the substrate of transistor 204. Preferably, diodes 218 and 220 are intrinsic diodes of transistors 202 and 204, respectively.

[0043] Circuit 10 includes an input 102 and two outputs 104 and 106. Input 102 receives a voltage VLX to be compared with a voltage range, more specifically, a voltage VLX to be compared with a first voltage threshold and a second voltage threshold. Figure 1In the example, the first threshold and the second threshold are the device's positive power supply voltage Vbat and reference voltage GND (preferably ground), respectively. Output 104 provides a signal POS (preferably binary), and output 106 provides a signal NEG (preferably binary). When circuit 10 determines that the input voltage is greater than the first threshold Vbat within the range, signal NEG takes a first value, such as a high value. If the input voltage is less than the first threshold Vbat, then voltage NEG takes a second value, such as a low value. When circuit 10 determines that the input voltage is less than the second threshold within the range, signal POS takes a first value, such as a high value. If the input voltage is greater than the second threshold, then voltage POS takes a second value, such as a low value.

[0044] Therefore, if both signals POS and NEG have low values, this means the input voltage is between the first and second thresholds. If signal NEG has a high value and signal POS has a low value, the input voltage has a value greater than the first threshold. If signal NEG has a low value and signal POS has a high value, the input voltage has a value less than the second threshold.

[0045] Circuit 10 includes two transistors 108 and 110 connected in series between rails 3 and 5. More specifically, one of the conductive terminals (source or drain) of transistor 108 is coupled (preferably connected) to node 112. The other conductive terminal (drain or source) of transistor 108 is coupled (preferably connected) to input node 102. One of the conductive terminals (source or drain) of transistor 110 is coupled (preferably connected) to node 102. The other conductive terminal (drain or source) of transistor 110 is coupled (preferably connected) to node 114.

[0046] Preferably, transistor 110 is a P-type field-effect or PMOS transistor, and transistor 108 is an N-type field-effect or NMOS transistor. Preferably, transistors 108 and 110 are coupled (preferably connected) to node 102 through their respective source terminals.

[0047] Transistor 108 is voltage-controlled, the value of which is substantially equal to (preferably equal to) a second voltage threshold, here being the reference voltage GND. In other words, the control terminal or gate of transistor 108 is coupled to track 5, to which the voltage GND is applied. Transistor 110 is voltage-controlled, the value of which is substantially equal to (preferably equal to) a first voltage threshold, here being the power supply voltage Vbat. In other words, the control terminal or gate of transistor 110 is coupled to track 3, to which the voltage Vbat is applied.

[0048] Node 112 is preferably coupled to track 3 via a resistive element or resistor 116. Node 112 is also preferably coupled to output node 104 via a circuit or inverter 117 configured to invert a binary signal. Thus, when circuit 117 receives a low input value, it provides a high output voltage, and vice versa.

[0049] Node 114 is preferably coupled to track 5 via a resistive element or resistor 118. Node 114 is also coupled, preferably via two circuits or inverters 120 and 122 in series, to output node 106, which are configured to invert the binary signal.

[0050] Therefore, resistor 116, transistor 108, transistor 110 and resistor 118 are coupled in series between rails 3 and 5 in this order.

[0051] Circuits 117, 120, and 122 ensure that signals POS and NEG are binary signals with identifiable high and low values.

[0052] Figure 2 Explanation is shown Figure 1 A timing diagram of the operation of an embodiment. More specifically, Figure 2 Shown in Figure 1 The behavior of the current Ic, voltage VX, control signals GN and GP, and signals POS and NEG at node 206 during the operating cycle of circuit 20 and during part (E) of the next cycle. The operating cycle includes, for example, four phases: inductor element ( Figure 1 The diagram shows the power storage stage (A), intermediate stage (B), power transfer stage (C), and compensation stage (D) of a power storage stage (with terminals coupled to node 102).

[0053] During the power storage phase (A), transistor 202 is turned on while transistor 204 is turned off. Figure 1 In this embodiment, this corresponds to control signals GN and GP having low values. Therefore, the voltage VLX has a positive value V1, which is less than the value Vbat. Therefore, during stage (A), the current Ic flowing through the inductor element... Figure 1 (Not shown in the text) Add.

[0054] The voltage VLX is less than the control voltage of transistor 110, i.e., the supply voltage Vbat, and the gate-source voltage of transistor 110 is positive. Therefore, transistor 110 remains off during phase (A). Consequently, the voltage at node 114 has a low value, for example, essentially equal to the reference voltage GND. Consequently, the signal NEG at the outputs of inverters 120 and 122 has a low value.

[0055] Similarly, since voltage VLX is greater than the control voltage of transistor 108, i.e., the reference voltage GND, the gate-source voltage of transistor 108 is negative. Therefore, transistor 108 remains off during phase (A). Consequently, the voltage at node 112 has a high value, for example, essentially equal to voltage Vbat. Consequently, the signal POS at the output of inverter 117 has a low value.

[0056] During phase (B), transistors 204 and 202 are off. Figure 1 In this embodiment, this corresponds to a control signal GN with a low value and a control signal GP with a high value. Stage (B) is an intermediate stage that ensures that transistors 208 and 210 do not conduct simultaneously. During stage (B), node 206 is no longer powered by track 3. Therefore, the current Ic decreases. With current Ic positive, transistors 202 and 204 are turned off. Current Ic therefore flows through diode 220. Voltage VLX takes a negative value of V3.

[0057] The voltage VLX is less than the control voltage of transistor 110, i.e., the supply voltage Vbat, and the gate-source voltage of transistor 110 is positive. Therefore, transistor 110 remains off during phase (B). Consequently, the voltage at node 114 is low, for example, essentially equal to the reference voltage GND. Therefore, the signal NEG at the outputs of inverters 120 and 122 has a low value.

[0058] The voltage VLX is negative. In other words, the voltage VLX is less than the control voltage of transistor 108, i.e., the reference voltage GND. The gate-source voltage of transistor 108 is therefore positive. Therefore, transistor 108 is turned on during stage (B). Therefore, the voltage at node 112 has a low value, for example, it is essentially equal to the voltage V3. Therefore, the signal POS at the output of inverter 117 has a high value.

[0059] Signals POS and NEG therefore indicate that the voltage VLX is less than two thresholds, Vbat and GND. More specifically, a low value of signal NEG indicates that the voltage VLX is less than the threshold Vbat or within the range of values ​​GND and Vbat, or outside that range and less than the threshold GND. A high value of signal POS indicates that the voltage VLX is less than the threshold GND, and therefore outside the range between values ​​GND and Vbat.

[0060] During phase (C), i.e., the power transfer phase, transistor 204 is turned on while transistor 202 is turned off. Figure 1 In this embodiment, this corresponds to control signals GN and GP having high values. Voltage VLX increases but remains negative. During phase (C), current Ic decreases, and node 206 is no longer powered by track 3.

[0061] The voltage VLX is less than the control voltage of transistor 110, i.e., the supply voltage Vbat, and the gate-source voltage of transistor 110 is positive. Therefore, transistor 110 remains off during phase (C). Consequently, the voltage at node 114 has a low value, for example, essentially equal to the reference voltage GND. Therefore, the signal NEG at the outputs of inverters 120 and 122 has a low value.

[0062] The voltage VLX is negative. In other words, the voltage VLX is less than the control voltage of transistor 108, i.e., the reference voltage GND. The gate-source voltage of transistor 108 is therefore positive. Therefore, transistor 108 is turned on during stage (B). Therefore, the voltage at node 112 has a low value, for example, it is essentially equal to the voltage V3. Therefore, the signal POS at the output of inverter 117 has a high value.

[0063] During stage (D), transistor 204 is off and transistor 202 is off. Figure 1 In the embodiments, this corresponds to the control signal GN with a low value and the control signal GP with a high value.

[0064] In stage (B), the current Ic is positive and transistors 202 and 204 are off. The current Ic therefore flows through diode 220. The voltage VLX is negative, V3.

[0065] In stage (B), the voltage VLX is less than the control voltage of transistor 110, i.e., the supply voltage Vbat, and the gate-source voltage of transistor 110 is positive. Therefore, transistor 110 remains off during stage (B). Consequently, the voltage at node 114 has a low value, for example, essentially equal to the reference voltage GND. Therefore, the signal NEG at the outputs of inverters 120 and 122 has a low value.

[0066] In stage (B), the voltage VLX is negative. In other words, the voltage VLX is less than the control voltage of transistor 108, i.e., the reference voltage GND. The gate-source voltage of transistor 108 is therefore positive. Therefore, transistor 108 is turned on during stage (B). Therefore, the voltage at node 112 has a low value, for example, essentially equal to voltage V3. Therefore, the signal POS at the output of inverter 117 has a high value.

[0067] During phase (D), the current Ic continuously decreases. Phase (D) ends when the current Ic reaches zero.

[0068] For example, stage (D) is followed by stage (E), which may correspond to stage (A) of the next operating cycle or a stage in the off state.

[0069] Figure 3 Explanation is shown Figure 1A timing diagram of the operation of an embodiment. More specifically, Figure 3 Shown in Figure 1 During the operating cycle of circuit 20, the control signals GN and GP for the current Ic and voltage VLX at node 206, as well as the signals POS and NEG, are operated. Figure 2 As shown, the operating cycle includes four stages: the power storage stage in the inductor (A), the intermediate stage (B), the power transfer stage (C), and the compensation stage (D).

[0070] Phases (A) and (B) with Figure 2 Stages (A) and (B) are the same. They will not be described again.

[0071] During the power transfer phase (C), transistor 204 is turned on while transistor 202 is turned off. Figure 1 In the embodiments, this corresponds to control signal GN with high value and control signal GP with high value.

[0072] The voltage VLX increases during phase (C). At time tz in phase (C), the voltage VLX reaches zero and then continues to increase. The current Ic decreases during phase (C). At time tz, the current Ic reaches zero. During phase (C), the current Ic is positive before time tz and negative after time tz, while the voltage VLX is positive before time tz and negative after time tz.

[0073] During phase (C), voltage VLX is less than the first voltage threshold Vbat. Therefore, signal NEG remains low. Furthermore, voltage VLX is less than the second voltage threshold GND before time tz and greater than the second threshold after time tz. Therefore, during phase (C), signal POS takes a high value before time tz and a low value after time tz.

[0074] During stage (D), transistor 204 is off and transistor 202 is off. Figure 1 In the embodiments, this corresponds to the control signal GN with a low value and the control signal GP with a high value.

[0075] Transistors 202 and 204 are turned off, and the current Ic is negative, while diode 218 is activated. Therefore, voltage VLX becomes greater than voltage Vbat, for example, essentially equal to voltage Vbat plus the threshold voltage of diode 218. Consequently, current Ic increases to zero. When the current reaches zero, stage (D) ends.

[0076] When voltage VLX is greater than the control voltage of transistor 110, i.e., the power supply voltage Vbat, signal NEG has a high value. Furthermore, when voltage VLX is greater than the control voltage of transistor 108, i.e., the reference voltage GND, signal POS has a low value.

[0077] Phase (D) is followed by phase (E), in which the device behaves similarly to its behavior in phase (A). As a variant, phase (E) corresponds to the phase in the cutoff state.

[0078] Figure 4 An embodiment of a DC / DC voltage converter is schematically illustrated. In this example, converter 1 is a DC / DC converter that converts a DC supply voltage into a DC output voltage.

[0079] Converter 1 is configured to deliver a DC output voltage Vout. The converter includes an output node 2 with an available voltage Vout.

[0080] Converter 1 is powered by a DC power supply voltage Vbat. Converter 1 is then connected between a first conductive rail or node 3, which is set to voltage Vbat, and a second conductive rail or node 5, which is set to reference potential GND.

[0081] Converter 1 is configured to deliver voltage Vout at a value equal to the setpoint value. To this end, converter 1 receives a DC setpoint voltage Vref at input node 7, referenced to potential GND, whose value represents the setpoint value of voltage Vout, preferably equal to the setpoint value of voltage Vout.

[0082] In this example, the voltages Vout, Vbat, and Vref are positive.

[0083] In this example, converter 1 is a step-down converter, meaning the setpoint value of voltage Vout is less than the value of voltage Vbat. In other words, the value of voltage Vout is less than the value of voltage Vbat.

[0084] The converter 1 includes a first MOS (“metal-oxide-semiconductor”) transistor 9, preferably a PMOS transistor (P-channel MOS transistor). Alternatively, transistor 9 may also be an NMOS transistor associated with a bootstrap system. The MOS transistor 9 is connected between track 3 and internal node 11. In other words, a first conductive terminal (e.g., its source) of transistor 9 is connected to track 3, and a second conductive terminal (e.g., its drain) of transistor 9 is connected to node 11.

[0085] The converter 1 also includes a second MOS transistor 13, preferably an NMOS transistor (N-channel MOS transistor). Transistor 13 is connected between node 11 and track 5. In other words, the first conductive terminal (e.g., its source) of transistor 13 is connected to track 5, and the second conductive terminal (e.g., its drain) of transistor 13 is connected to node 11. As a variant, a diode or Schottky diode can be used instead of the NMOS transistor 13.

[0086] Therefore, transistors 9 and 13 are connected in series between tracks 3 and 5, and are connected to each other at the level of internal node 11.

[0087] Converter 1 includes an inductor element or inductor 15. Inductor 15 is connected between node 11 and node 2.

[0088] The converter 1 includes a control circuit 17. The circuit 17 is configured to implement or control the operating cycle of the converter 1 to adjust the voltage Vout so that its value is equal to the setpoint value Vref.

[0089] Therefore, circuit 17 includes:

[0090] Terminal 171 is coupled (preferably connected) to node 7;

[0091] Terminal 172 is coupled (preferably connected) to node 2;

[0092] Terminal 173 is coupled (preferably connected) to track 3;

[0093] - Terminal 174, coupled (preferably connected) to track 5;

[0094] Terminal 175 is coupled (preferably connected) to the control terminal or gate of transistor 9; and

[0095] Terminal 176 is coupled (preferably connected) to the control terminal or gate of transistor 13.

[0096] Converter 1 includes an output capacitor 16 connected between node 2 and track 5. For example, this capacitor is in the range of 2.2 μF to 20 μF, or even larger. Such an output capacitor acts as a filter. In other words, the converter output capacitor smooths the current present at node 2 and stores the power supplied to node 2 by the converter.

[0097] In operation, a load is connected between node 2 and track 5 to be powered by voltage Vout. This load may include, for example, an input capacitor between node 2 and track 5.

[0098] In this example, converter 1 is configured to operate in pulse frequency modulation (intermittent conduction mode). Circuit 17 is then configured to begin the operating cycle of converter 1 when the voltage Vout is less than the setpoint value Vref and both transistors 9 and 13 are in the off state. More specifically, at the beginning of each operating cycle, circuit 17 is configured to control transistor 9 to be turned on and transistor 13 to be kept off. Then, during a first time period TPon, power is stored in inductor 15 and capacitor 16, for example, while transistor 9 is kept on by circuit 17, this first time period is constant for each operating cycle, and current IL flows through inductor 15. At the end of time period TPon, circuit 17 is configured to control transistor 9 to be turned off and transistor 13 to be turned on. Power is then fed back to the load connected to the converter output through inductor 15 and capacitor 16 for a second time period TNon, for example, while circuit 17 keeps transistor 13 on, this second time period is constant for each operating cycle, and current IL in the inductor decreases. At the end of the time period TNon, circuit 17 is configured to control transistor 13 to be set to the off state.

[0099] A time period TNon is defined such that the time during which circuit 17 controls transistor 13 to be in the off state corresponds to the time when the current IL flowing through inductor 15 becomes zero. However, in practice, as will be described in further detail in the remainder of this disclosure, this is not always correct, which raises a problem.

[0100] Figure 5 The timing diagram is shown, illustrating... Figure 4 Example of expected operation of converter 1.

[0101] Timing diagram A (in) Figure 5 The top of the time series plot (B) shows the change of voltage Vout over time t, in volts (V). Figure 5 The bottom of the diagram shows the corresponding change of the current IL flowing through inductor 15 with time t.

[0102] At time t0, transistors 9 and 13 are in the off state, the current IL is zero, and the voltage Vout is greater than its setpoint value, which in this example is the voltage Vref.

[0103] Between time t0 and the subsequent time t2, the voltage Vout decreases, for example, due to the fact that the load connected to converter 1 consumes current and discharges the output capacitor.

[0104] During time t1, between times t0 and t2, the voltage Vout becomes less than its setpoint value Vref. This is detected by circuit 17 of converter 1, which then controls the transistor 9 to be turned on. Transistor 9 turns on at time t2.

[0105] Therefore, starting from time t2, inductor 15 has a terminal connected to node 2 via transistor 9 and a terminal coupled to track 3. The current IL flowing through inductor 15 increases.

[0106] Therefore, starting at time t2, current IL is supplied to node 2, and capacitor 16 between node 2 and track 5 is charged. Voltage Vout increases and becomes greater than its setpoint value Vref.

[0107] At the next time point t3, equal to t2 + TPon, circuit 17 controls transistor 13 to be turned on and transistor 9 to be turned off. At time t3, the current in the inductor has its maximum value ILP.

[0108] Therefore, starting from time t3, inductor 15 has a terminal connected to node 2 via transistor 13 and a terminal coupled to track 5. The current IL flowing through inductor 15 decreases.

[0109] Although the current IL decreases from time t3, if the current drawn by the load is less than the current IL supplied to node 2, the capacitor between node 2 and track 5 continues to charge, and the voltage Vout continues to increase.

[0110] At the next time t4, equal to t3 + TNon, circuit 17 controls transistor 13 to be set to the off state. Here, it is assumed that converter 1 operates as it should, and the current IL is zero at time t4. However, in practice, this is not always correct.

[0111] Starting from time t4, the current IL is zero and the voltage Vout decreases, similar to what happens at time t0.

[0112] Although not shown in this document, circuit 17 implements a new operating cycle as described with respect to continuous times t2, t3, and t4, when the value of potential Vout falls below its setpoint value Vref after time t4.

[0113] Figure 6 Explanation is shown Figure 4Other timing diagrams for the operation of converter 1 are provided. More specifically, timing diagram A1 shows an ideal or theoretical example of the change in current IL, timing diagram A2 shows the voltage Vout corresponding to the change in current IL in timing diagram A1, timing diagram B1 shows an example of the actual change in current IL, and timing diagram B2 shows the voltage Vout corresponding to the change in current IL in timing diagram B1. These timing diagrams illustrate an operational example in which voltage Vout is less than voltage Vref at the end of each operating cycle of converter 1 over multiple consecutive operating cycles. The current taken at the output node is assumed to be a constant current Iout.

[0114] At time t30 (timing diagrams A1 and A2), voltage Vout is less than voltage Vref. The operating cycle begins when transistor 9 switches to the on state. Therefore, current IL increases until the next time t31 equals t30 + TPon.

[0115] At time t31, the current IL reaches its maximum value ILP. Furthermore, transistors 9 and 13 switch to the off and on states, respectively. Therefore, the current decreases until the next time t32 equals t31 + TNon.

[0116] In this example of ideal operation, transistor 13 switches to the off state at time t32, and the current IL becomes zero at time t32.

[0117] At time t32, when voltage Vout is less than voltage Vref, transistor 9 switches to the on state, marking the start of a new operating cycle. The current IL then increases until the next time interval t33 equals t32 + TPon.

[0118] At time t33, the current IL reaches its value ILP. Furthermore, transistors 9 and 13 switch to the off and on states, respectively. Therefore, the current decreases until the next time t34, when it equals t33 + TNon.

[0119] In this example of ideal operation, transistor 13 switches to the off state at time t34, and the current IL becomes zero at time t34.

[0120] At time t34, when voltage Vout is less than voltage Vref, transistor 13 switches to the on state, marking the start of a new operating cycle. Current IL increases until the next time interval t35, which equals t34 + TPon.

[0121] At time t35, the current IL reaches its value ILP. Furthermore, transistors 9 and 13 switch to the off and on states, respectively. Therefore, the current decreases until the next time t36, when it equals t35 + TNon.

[0122] In this example of ideal operation, transistor 13 switches to the off state at time t36, and the current IL becomes zero at time t36.

[0123] At time t36, the voltage Vout is less than the voltage Vref, and a new operating cycle begins.

[0124] In the example of theoretical operation shown in timing diagrams A1 and A2, at the end of each operating cycle, the transistor 13 in the off state switches when the current IL becomes zero. Therefore, when one operating cycle immediately follows a new operating cycle, the current IL increases from zero in the new operating cycle.

[0125] Timing diagrams B1 and B2 illustrate corresponding examples of actual operation of converter 1. In this example of actual operation, consider the actual situation where transistor 13 does not immediately switch to the off state at the end of the time period TNon that has elapsed since its last switch to the on state.

[0126] At time t40 when voltage Vout is less than voltage Vref ( Figure 6 B1 and Figure 6 (B2), the operating cycle begins from switching to the on state of transistor 9. Therefore, the current IL increases until the next time interval t41 equals t40 + TPon.

[0127] At time t41, the current IL reaches its maximum value ILP. Furthermore, transistors 9 and 13 switch to the off and on states, respectively. Therefore, the current decreases until the next time t42, when it equals t41 + TNon. The current becomes zero at time t42. However, the switching of transistor 13 to the off state is only effective at time t43, which is after time t42. Therefore, between times t42 and t43, the current IL is negative and decreases. In other words, before time t42, the current flows through inductor 15 from node 11 to node 2, becomes zero at time t42, and after time t42, the current flows through inductor 15 from node 2 to node 11.

[0128] At time t43, the voltage Vout is less than the voltage Vref, and transistor 9 switches to the on state at time t43, marking the start of a new operating cycle. The current IL then increases until the next time t44, when it equals t43 + TPon.

[0129] At time t44, since the time interval TPon is constant in each cycle, the current IL reaches a value ILp', which is smaller than the maximum value ILp. Furthermore, transistors 9 and 13 switch to the off and on states, respectively. Therefore, the current IL decreases until the next time t46, when it equals t44 + TNon, and the current IL becomes zero during the time t45 between t44 and t46. Moreover, the switching of transistor 13 to the off state is only effective at time t47 after time t46. Therefore, between times t45 and t47, the current IL is negative and decreases to a value lower (or higher in absolute value) than the value reached at time t43.

[0130] At time t47, the voltage Vout is less than the voltage Vref, and transistor 9 switches to the on state at time t47, marking the start of a new operating cycle. The current IL then increases until the next time t48, when it equals t47 + TPon.

[0131] At time t48, the current IL reaches value ILp", which is less than value ILp'. Furthermore, transistors 9 and 13 switch to the off and on states, respectively. Therefore, the current IL decreases until the next time t50 equals t48 + TNon, and the current IL becomes zero during time t49 between t48 and t50. Additionally, the switching of transistor 13 to the off state is only effective at time t51 after time t50. Therefore, between times t49 and t51, the current IL is negative and decreases to a value lower (or higher in absolute value) than the value reached at time t47.

[0132] Because the maximum value of current IL (at times t41, t44, and t48) decreases in each operating cycle shown in timing diagrams B1 and B2, converter 1 does not provide sufficient power to node 2 to regulate voltage Vout to its value Vref, causing Vout to decrease, for example, which leads to problems. Furthermore, the negative values ​​(or absolute values) of current IL (at times t43, t47, and t51) decrease in each operating cycle shown in timing diagrams B1 and B2, causing converter 1 to sample increasingly more power from node 2, which is undesirable. In practice, the current value supplied to the load, especially the peak current value, decreases from one cycle to the next, negatively impacting the load power supply. Moreover, while theoretically the maximum value of current IL could decrease indefinitely, in practice, in some cases, transistor 13 may be damaged or destroyed by the negative value of current IL before it can conduct between its conductive terminals.

[0133] Already combined Figure 6 Timing diagrams B1 and B2 illustrate a practical example of the operation that occurs after the current IL becomes zero, switching to the off state of transistor 13.

[0134] In another practical example of the operation (not shown), in each of a series of consecutive operating cycles that immediately follow the other cycles, transistor 13 is switched to the off state while the current IL is not zero and remains positive. In this case, in each operating cycle, the current IL increases from an increasingly higher value, thereby reaching an increasingly higher maximum value, and the operating cycle ends with an increasingly higher positive non-zero value of the current IL. This operation is less disruptive than the operation described with respect to timing diagrams B1 and B2 because after several operating cycles, the voltage Vout will recover its setpoint value Vref. Therefore, the next operating cycle will not be implemented immediately, which will leave time for the current IL to become zero.

[0135] These two situations, namely regarding Figure 6 The situations described in timing diagrams B1 and B2, and other aforementioned practical issues, are typically caused, at least in part, by component-level defects, particularly those of comparators, and especially by the comparator's operating time (response or propagation time) and offsets in the comparator's voltage levels. In other words, the comparator does not compare the input signals S1 and S2, but rather compares S1 and S2+A, where A is the comparator's offset.

[0136] Figure 7 It shows Figure 1 An example of the application of circuit 10 in a DC / DC voltage converter. Figure 7 The converter includes information about Figure 4 The components described in circuit 17 will be described in more detail.

[0137] The converter includes transistors 9 and 13, inductor 15, and capacitor 16, as per [reference needed]. Figure 4 As described.

[0138] Transistors 9 and 13 are similar Figure 1 Transistors 202 and 204 are coupled (preferably connected in series) between rail 3, where a power supply voltage Vbat is applied, and rail 5, where a reference voltage (e.g., ground GND) is applied. In other words, one conductive terminal (source or drain) of transistor 9 is coupled (preferably connected) to rail 3, while the other conductive terminal (drain or source) is coupled (preferably connected) to the center node 11. One conductive terminal (source or drain) of transistor 13 is coupled (preferably connected) to node 11, and the other conductive terminal (drain or source) is coupled (preferably connected) to rail 5.

[0139] Preferably, transistor 9 is a P-type field-effect transistor or a PMOS transistor, and transistor 13 is an N-type field-effect transistor or an NMOS transistor.

[0140] Each of transistors 9 and 13 includes an intrinsic diode, not shown.

[0141] Intrinsic diode (not shown) and Figure 1 Similar to diodes 218 and 220, they are series-coupled between rails 3 and 5. More specifically, the first terminal (anode or cathode) of the intrinsic diode of transistor 13 is coupled (preferably connected) to rail 5, and the second terminal (cathode or anode) of the diode is coupled (preferably connected) to node 11. The first terminal (anode or cathode) of the intrinsic diode of transistor 9 is coupled (preferably connected) to node 11, and the second terminal (cathode or anode) of the diode is coupled (preferably connected) to rail 3. Figure 1 In the example, the first terminal of the intrinsic diode is the anode, and the second terminal of the intrinsic diode is the cathode. Node 11 is therefore coupled to the anode of one diode and the cathode of the other diode.

[0142] The converter includes circuitry 180 for generating control signals GP and GN, circuitry 182 for transmitting signals PWN that determine durations TPon and TNon, circuitry 184 configured to determine the start time of each operating cycle, and circuitry 186 for generating a variable voltage.

[0143] Circuit 180 includes a first output 180a and a second output 180b, which are coupled (preferably connected) to outputs 175 and 176 of circuit 17, respectively. Circuit 180 generates a signal GP for controlling transistor 9 at the first output 180a and a signal GN for controlling transistor 13 at the second output 180b.

[0144] Circuit 180 includes an input 180c coupled (preferably connected) to the output of circuit 182. Circuit 182 provides a signal PWN at this output that determines the durations TPon and TNon, and thereby determines the durations of the power storage phase and the power transfer phase.

[0145] Circuit 182 includes two inputs, 182a and 182b, which are coupled (preferably connected) to inputs 171 and 172 of circuit 17, respectively. Therefore, circuit 182 generates a signal PWN based on the values ​​of the voltage Vout received at input 172 and the setpoint voltage Vref received at input 171, and more specifically, based on the difference between these values. Thus, if voltage Vout is less than voltage Vref, the duration TPon increases and the duration TNon decreases. If voltage Vout is greater than voltage Vref, the duration TNon increases and the duration TPon decreases.

[0146] The converter includes circuitry 184 configured to determine the start time of each operating cycle. More specifically, circuitry 184 is configured to determine the time when the current Ic reaches zero, i.e., the end of the operating cycle. In practice, this corresponds to the detection of the voltage VLX crossing zero. Circuitry 184 includes an output coupled (preferably connected) to circuitry 180 to convey this information by a high-value signal S when the current Ic reaches zero.

[0147] Circuit 184 is, for example, a zero-crossing detection circuit (ZCD). Circuit 184 includes a comparator.

[0148] The comparator of circuit 184 is subjected to AND Figure 6 The impact of defects discussed in the B1-6B2 discussion. More specifically, propagation delay and offset of the comparator input voltage cause comparator defects, such as those related to... Figure 6 As stated in B.

[0149] Circuit 184 is coupled at its input to track 5 to pass the reference voltage GND, and coupled to node 11 to pass the voltage VLX.

[0150] Circuit 184 is coupled to track 5 via circuit 186, which is configured to modify the value compared to voltage VLX to compensate for propagation delay and offset of the comparator in circuit 184. For example, circuit 186 is a variable voltage source. Therefore, the output voltage of circuit 186, i.e., the input voltage of circuit 184 compared to voltage VLX, can be different from zero. Circuit 184 does not compare voltage VLX to the value of zero; instead, it compares voltage VLX to the output value of circuit 186. For example, the output value of circuit 186 is modified in each operating cycle.

[0151] To determine whether circuit 186 should modify its output value, circuit 186 receives signal d. Signal d is generated by a circuit combination including circuit 10 and circuit 190. Therefore, circuit 10 is coupled (preferably connected) at its input to node 11. Circuit 10 includes two outputs with signals POS and NEG generated thereon.

[0152] Circuit 190 is coupled (preferably connected) at its input to the output of circuit 10, and thus receives POS and NEG as input signals. Circuit 190 determines the sign of current IC during phase (D) and generates a signal d that modifies the output value of control circuit 186. Therefore, the voltage modification of circuit 186 depends on the sign of current Ic during phase (D), and is preferably independent of the current sign during other phases.

[0153] Figure 8 It shows Figure 7 A timing diagram of an operational example of an embodiment. Figure 8The diagram shows two operating cycles of the converter, separated by a stop phase.

[0154] During the first stop phase (E), transistors 9 and 13 are turned off. This corresponds to signals GN and GP, which have low and high values, respectively. During this phase, the current Ic is zero, and the voltage VLX is essentially equal to V2, positive, and less than voltage Vbat. Furthermore, signal S, preferably binary, has a low value, for example.

[0155] At time t60, phase (A) of the operation cycle begins. Therefore, time t60 corresponds to the end of phase (E) and the beginning of phase (A).

[0156] At time t60, transistor 9 is turned on. In other words, the control signal GP takes another binary value, which is low here. Node 11 is therefore powered by rail 3. Thus, the voltage at the node is V1, slightly less than Vbat, but greater than V2, and the current Ic increases.

[0157] At time t62, phase (A) ends and phase (B) begins. The duration of phase (A) corresponds to the duration TPon.

[0158] and Figure 2 and Figure 3 In stage (B), the situation is the same; transistor 9 is cut off, and transistor 13 is cut off. Figure 7 In this embodiment, this corresponds to a control signal GN with a low value and a control signal GP with a high value. Stage (B) is an intermediate stage that ensures that transistors 9 and 13 do not conduct simultaneously. During stage (B), node 11 is no longer powered by track 3. Therefore, the current Ic decreases.

[0159] With current Ic positive, transistors 202 and 204 are cut off. Therefore, current Ic flows through diode 220. Voltage VLX becomes negative, V3.

[0160] During phase (B), such as Figure 2 and Figure 3 As stated, signal POS takes a high value. However, during phase (B), circuit 190 does not consider signals POS and NEG.

[0161] At time t62, phase (B) ends and phase (C) begins. Transistor 13 is turned on, and transistor 9 is turned off. Figure 7 In this embodiment, this corresponds to control signals GN and GP having high values. As voltage VLX increases, current Ic decreases through inductor 15, and node 11 is no longer powered by rail 3.

[0162] At time tz1 of phase (C), i.e., after duration TNon, the current Ic and voltage VLX reach zero. However, circuit 184 has a propagation delay of value D. Therefore, the output S of circuit 184 only takes a high value at time t66, which is the time interval D with respect to tz1, indicating the zero crossing of current Ic. Between time tz1 and time t66, current Ic becomes negative.

[0163] At time t66, circuit 180 is informed by the rising edge of signal S that the current Ic has reached zero. Thus, phase (C) ends and phase (D) begins.

[0164] During phase (D), transistors 9 and 13 are off. Figure 7 In the embodiments, this corresponds to the control signal GN with a low value and the control signal GP with a high value.

[0165] Transistors 9 and 13 are turned off, and the current Ic is negative, making the intrinsic diode of transistor 9 active. Therefore, the voltage VLX becomes greater than the voltage Vbat, for example, essentially equal to the voltage Vbat plus the diode's threshold voltage. Consequently, the current Ic increases to zero at time t68. When the current reaches zero, the diode no longer conducts, and stage (D) ends.

[0166] At time t68, a phase (E) as previously described begins. The voltage VLX recovers to its value V2.

[0167] Phase (E) is followed by the second operating cycle, which includes phase (A) between time t70 and time t72, phase (B) between time t72 and time t74, phase (C) between time t74 and time t76, and phase (D) between time t76 and time t78.

[0168] The second operating cycle differs from the first operating cycle in that, before stage (C), for example during stage (A), circuit 190 provides signal d to circuit 186 to modify the value of the output signal of circuit 186. In the case of the second operating cycle, the value of the output of circuit 186 is modified to be equal to a value V4 that is smaller than the value of the reference voltage (here, ground).

[0169] Therefore, circuit 184 compares the voltage VLX with the value V4. At time tz2, the value V4 is reached, earlier than the value zero. Phase (C) ends time period D after time tz2. The negative value reached by current Ic at the end of phase (C) is closer to zero than the value reached by current Ic at the end of the previous phase (C).

[0170] The advantage of the described embodiment is that the voltage can be compared with two thresholds using a simple circuit.

[0171] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and that other variations will be derived from them.

[0172] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0173] Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the invention. Therefore, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited to what is defined in the appended claims and their equivalents.

Claims

1. An electronic device, comprising: A first circuit includes a first transistor and a second transistor, the first transistor and the second transistor being coupled in series between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, and the first transistor and the second transistor being coupled to each other through the first node; as well as The second circuit is configured to compare a first voltage at the first node with a first voltage threshold and a second voltage threshold. The second circuit includes a third transistor and a fourth transistor, which are coupled in series between a second node and a third node. The third transistor and the fourth transistor are coupled to each other through a fourth node, which is coupled to the first node. The control terminal of the third transistor is coupled to the node where the second voltage threshold is applied, and the control terminal of the fourth transistor is coupled to the node where the first voltage threshold is applied.

2. The device of claim 1, wherein the second node is coupled to the node to which the power supply voltage is applied via a first resistive element, and the third node is coupled to the node to which the reference voltage is applied via a second resistive element.

3. The device according to claim 1, wherein the first voltage threshold is the power supply voltage, and the second voltage threshold is the reference voltage.

4. The device according to claim 2, wherein the second circuit comprises: A first output node is provided with a first signal, the first signal taking a first value when the first voltage is greater than the first voltage threshold, and taking a second value when the first voltage is less than the first voltage threshold; as well as The second output node provides a second signal, which takes a third value when the first voltage is less than the second voltage threshold, and takes a fourth value when the first voltage is greater than the second voltage threshold.

5. The device of claim 4, wherein the first output node is coupled to the second node, and the second output node is coupled to the third node.

6. The device of claim 4, wherein the first output node is coupled to the second node via an inverting circuit, and the second output node is coupled to the third node via two inverting circuits.

7. The device of claim 1, wherein the first transistor is connected in parallel with the first diode, the second transistor is connected in parallel with the second diode, and the anode of the first diode and the cathode of the second diode are connected to the first node.

8. The device according to claim 4, wherein the device is a switch-mode power supply.

9. The device of claim 8, wherein the device includes a third circuit configured to compare the first voltage with a second voltage, the second voltage being variable and dependent on signals at the first output node and the second output node.

10. The device of claim 8, wherein the device includes a fourth circuit configured to control the first transistor and the second transistor in such a way that each operating cycle continuously comprises: In the first phase, during which the first transistor is turned on and the second transistor is turned off; In the second phase, during the second phase, the first transistor and the second transistor are turned off; In the third stage, during which the first transistor is turned off and the second transistor is turned on; as well as In the fourth stage, during which the first transistor and the second transistor are turned off.

11. The device according to claim 10, wherein: The device further includes a third circuit configured to compare the first voltage with a second voltage, the second voltage being variable and dependent on signals at the first output node and the second output node; as well as During the fourth phase, the change in the second voltage depends on the signals at the first output node and the second output node.

12. A method for controlling an electronic device, the electronic device comprising a first circuit including a first transistor and a second transistor, the first transistor and the second transistor being series coupled between a node to which a power supply voltage is applied and a node to which a reference voltage is applied, the first transistor and the second transistor being coupled to each other through the first node, the method comprising: In each operating cycle, each of the first and second transistors is turned on and off according to a predetermined pattern; as well as The second circuit compares the first voltage at the first node with a first voltage threshold and a second voltage threshold. The comparison is performed by a third transistor and a fourth transistor coupled to the first node and in series coupled between the second and third nodes; and The method further includes: The second voltage threshold is applied to the control terminal of the third transistor; as well as The first voltage threshold is applied to the control terminal of the fourth transistor.

13. The method of claim 12, wherein the first voltage threshold is the power supply voltage, and the second voltage threshold is the reference voltage.

14. The method of claim 12, further comprising: The first signal of the first output node of the second circuit takes a first value when the first voltage is greater than the first voltage threshold, and takes a second value when the first voltage is less than the first voltage threshold; as well as The second signal of the second output node of the second circuit takes a third value when the first voltage is less than the second voltage threshold, and takes a fourth value when the first voltage is greater than the second voltage threshold.

15. The method of claim 14, further comprising: The first voltage is compared with the second voltage by a third circuit. The second voltage is variable and depends on the signals on the first output node and the second output node.

16. The method of claim 14, further comprising: The first transistor and the second transistor are controlled by a fourth circuit in such a way that each operating cycle continuously includes: In the first phase, during which the first transistor is turned on and the second transistor is turned off; In the second phase, during the second phase, the first transistor and the second transistor are turned off; In the third stage, during which the first transistor is turned off and the second transistor is turned on; and In the fourth stage, during which the first transistor and the second transistor are turned off.

17. The method of claim 16, further comprising: The first voltage is compared with the second voltage by a third circuit. The second voltage is variable and depends on the signals on the first output node and the second output node. During the fourth stage, the change of the second voltage depends on the signals on the first output node and the second output node.

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