Pipeline arithmetic device and pipeline analog-to-digital converter

Abstract

The application discloses a kind of pipeline operation device and pipeline analog-digital converter, comprising: dynamic matching sub-analog-digital converter, sample holder, pseudo-random code generator and multiplication digital-analog converter;Multiplication digital-analog converter is connected with dynamic matching sub-analog-digital converter and sample holder respectively, and dynamic matching sub-analog-digital converter is connected with pseudo-random code generator.Based on dynamic matching sub-analog-digital converter, using pseudo-random code can change the threshold voltage of comparator, realize the dynamic matching of comparator, so as to realize the dynamic matching of capacitor array in sub-analog-digital converter in multiplication digital-analog converter, and the capacitor mismatch caused by process error, manufacturing process etc.is scattered.Due to the threshold voltage of comparator only needs to be prepared before comparison, so the dynamic matching technology of threshold voltage can be used in the holding period of entire analog-digital conversion, on the basis of not squeezing analog-digital conversion time, reduce harmonic distortion, improve the linearity of analog-digital converter.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital converters, and particularly relates to a pipeline stage operation device and a pipeline analog-to-digital converter. BACKGROUND

[0002] A pipelined analog-to-digital converter (ADC) has become one of the most widely used analog-to-digital converters at present due to its high accuracy, fast conversion speed, low power consumption and various advantages. In a signal processing process, an analog signal Vin enters a sample-and-hold circuit and is initially quantized, and then directly enters a first pipeline stage. The first pipeline stage quantizes the signal into an N bit digital code and outputs an analog residual voltage to a next pipeline stage (a second pipeline stage) for the same processing. In order to realize high-speed pipeline operation, the next stage performs sampling at the time when the previous stage performs holding, and the next stage performs holding at the time when the previous stage performs sampling. In order to ensure that the circuit is in a determined state at each time, two-phase high-level non-overlapping clocks are used. The ratio of the sampling time and the holding output time of a multiplying digital-to-analog converter (MDAC) is 1:1.

[0003] The MDAC circuit module is composed of a sub analog-to-digital converter (Sub ADC) and a residual gain circuit. An input signal simultaneously enters the sub analog-to-digital converter (Sub ADC) and the residual gain circuit for sampling. In the Sub ADC, a comparator array and an encoding circuit are used to output a coarse quantization result N bit digital code. The sub DAC connected to the Sub ADC restores the digital code into an analog quantity, performs a residual difference amplification operation with the input signal sampled through a lower plate of a capacitor, and serves as an input of a next stage. In this way, the residual difference output of each stage is used as an input of a next stage, and the analog-to-digital conversion is continuously performed.

[0004] In a pipeline analog-to-digital converter, the capacitor mismatch error in the MDAC is one of the main nonlinear sources of the whole system, which can cause the inter-stage gain error, the inconsistent height of the input and output curve jump of the stage circuit, and thus the poor linearity of the analog-to-digital converter and the reduced precision of the analog-to-digital conversion. In the existing method, in order to realize a high-precision pipeline analog-to-digital converter, the conventional structure usually adopts the pseudo-random code and the dynamic element matching (DEM) technology in the encoding circuit of the sub DAC in each MDAC, that is, the capacitor array in the MDAC is rearranged according to the random control signal under each holding clock. However, this method inevitably needs to add a logic switch control circuit module in front of the capacitor array, which not only reduces the bandwidth of the circuit, but also occupies the already tight sampling and holding time, and thus the high precision and high speed of the analog-to-digital conversion process cannot be considered together, which is not suitable for the design of the high-speed analog-to-digital converter.

[0005] In summary, it is necessary to provide a pipeline stage operation device and a pipeline analog-to-digital converter which can reduce the capacitor mismatch error and improve the analog-to-digital conversion precision while maintaining the operation speed and not reducing the circuit bandwidth. SUMMARY

[0006] To solve the above problems, the application provides a pipeline stage operation device and a pipeline analog-to-digital converter.

[0007] In one aspect, the application provides a pipeline stage operation device, which comprises:

[0008] a dynamic matching sub analog-to-digital converter, a sample-and-hold device, a pseudo-random code generator and a multiplication digital-to-analog converter;

[0009] The multiplication digital-to-analog converter is connected with the dynamic matching sub analog-to-digital converter and the sample-and-hold device respectively, and the dynamic matching sub analog-to-digital converter is connected with the pseudo-random code generator.

[0010] Preferably, the dynamic matching sub analog-to-digital converter comprises a gating switch array, a comparator array, a plurality of resistors and an encoding circuit.

[0011] The number of switches in the gating switch array is the same as and one-to-one corresponds to the number of comparators in the comparator array; and the number of resistors is one more than the number of comparators.

[0012] The plurality of resistors are connected in series; the connection end of each adjacent two resistors is connected with the first end of a different gating switch in the gating switch array, the second end of the gating switch is connected with the positive input end of the comparator corresponding to the gating switch, the negative input end of each comparator is connected with an input voltage, and the output end of the comparator is connected with the encoding circuit.

[0013] Preferably, the multiplication digital-to-analog converter comprises a sub-digital-to-analog converter and a residual error amplifier.

[0014] The input end of the sub-digital-to-analog converter is connected with a sample-and-hold device and a dynamic matching sub-digital-to-analog converter, and the output end of the sub-digital-to-analog converter is connected with the input end of the residual error amplifier.

[0015] Preferably, the sub-digital-to-analog converter comprises two groups of sampling capacitors and two groups of sampling switches.

[0016] The number of sampling capacitors in each group of sampling capacitors is the same as the number of comparators in the comparator array, and the number of switches in each group of sampling switches is the same as the number of sampling capacitors in each group of sampling capacitors; one sampling capacitor is connected after each two sampling switches are connected in parallel.

[0017] One end of each sampling capacitor is connected with two corresponding parallel sampling switches respectively, and the other end of the sampling capacitor is connected with the residual error amplifier.

[0018] Preferably, the pseudo-random code generator comprises a D flip-flop and a logic gate, and is used to obtain a pseudo-random code through logic operation.

[0019] Preferably, the pseudo-random code generator is used to generate a pseudo-random code and send the pseudo-random code to the dynamic matching sub-digital-to-analog converter.

[0020] The sample-and-hold device is used to sample and hold an input voltage to obtain an input signal and send the input signal to the multiplication digital-to-analog converter.

[0021] The dynamic matching sub-digital-to-analog converter is used to dynamically match a threshold voltage according to the pseudo-random code sent by the pseudo-random code generator, quantize the input voltage according to the dynamically matched threshold voltage to obtain a quantization result, and send the quantization result to the multiplication digital-to-analog converter.

[0022] The multiplication digital-to-analog converter is used to restore the quantization result to an analog quantity, perform a residual error amplification operation on the input signal sent by the sample-and-hold device, and obtain a residual voltage.

[0023] Preferably, the gating switch array is used to gate and dynamically match the voltage division of each comparator in the comparator array according to the pseudo-random code.

[0024] The comparator array is used to compare the obtained voltage division with the input voltage as the threshold voltage, and send the comparison result to the encoding circuit.

[0025] The encoding circuit is used to quantize the comparison result to obtain a quantization result and send the quantization result to the multiplication digital-to-analog converter.

[0026] A plurality of resistors are used for voltage division.

[0027] Preferably, the sub-digital-to-analog converter is configured to restore the quantization result to an analog quantity, perform a difference operation on the analog quantity and an input signal sent by the sample-and-hold device to obtain a difference, and send the difference to the difference amplifier.

[0028] The difference amplifier is configured to amplify the difference to obtain a residual voltage.

[0029] Preferably, the sub-digital-to-analog converter is configured to control each group of switches in the sub-digital-to-analog converter according to the quantization result, dynamically match a reference voltage of a sampling capacitor corresponding to each group of switches in the sub-digital-to-analog converter, and perform a difference operation on the reference voltage and an input signal sent by the sample-and-hold device to obtain a difference.

[0030] In a second aspect, the present application provides a pipeline analog-to-digital converter, comprising:

[0031] a register, a digital correction module, a clock circuit, and a plurality of pipeline operation devices;

[0032] The plurality of pipeline operation devices are configured to quantize an input voltage to obtain a quantization result, and send the quantization result to the register. The plurality of pipeline operation devices comprise at least one first pipeline operation device and at least one second pipeline operation device.

[0033] The plurality of pipeline operation devices are connected in series. The register is connected to the plurality of pipeline operation devices. The digital correction module is connected to the register. The clock circuit is connected to the plurality of pipeline operation devices.

[0034] The register is configured to receive and process the quantization result sent by each pipeline operation device to obtain a quantization output result, and send the quantization output result to the digital correction module.

[0035] The digital correction module is configured to determine a digital signal according to the quantization output result and output the digital signal.

[0036] The clock circuit is configured to generate a clock signal for controlling all the pipeline operation devices.

[0037] The application has the advantages that: based on the dynamic matching sub-DAC, the threshold voltage of the comparator can be changed using the pseudo-random code, the dynamic matching of the comparator is realized, the dynamic matching of the capacitor array in the sub-DAC in the multiplication D-DAC is realized, the capacitor mismatch caused by the process error, the manufacturing process, etc. can be scattered, and since the threshold voltage of the comparator only needs to be prepared before the comparison of the comparator, the dynamic matching technology of the threshold voltage can be applied to the entire holding period of the analog-digital conversion, and the comparison quantization of the multiplication D-DAC is prepared in advance, therefore, the threshold voltage of the comparator in the dynamic matching sub-DAC has sufficient time for dynamic matching, the harmonic distortion can be reduced on the basis of not occupying the analog-digital conversion time, and the linearity of the analog-digital converter is improved. BRIEF DESCRIPTION OF DRAWINGS

[0038] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred implementation, and are not intended to constrain the application. Moreover, like reference numerals are intended to represent like and similar elements throughout the various drawings. In the drawings:

[0039] Figure 1 is a schematic diagram of a flow level operation device provided by the application;

[0040] Figure 2 is a schematic diagram of a dynamic matching sub-DAC of a flow level operation device provided by the application;

[0041] Figure 3 is a schematic diagram of a multiplication D-DAC of a flow level operation device provided by the application;

[0042] Figure 4 is a schematic diagram of the working principle of a 2.5bit multiplication D-DAC of a flow level operation device provided by the application;

[0043] Figure 5 is a clock schematic diagram of a flow level operation device provided by the application;

[0044] Figure 6 is a schematic diagram of the existing dynamic element matching technology added in the encoding circuit of the sub-DAC of the multiplication D-DAC at each level;

[0045] Figure 7 is a schematic diagram of a flow level operation device provided by the application. DETAILED DESCRIPTION

[0046] Exemplary embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0047] In a first aspect, according to an embodiment of the present disclosure, a stream stage operation device is provided, as shown in Figure 1 The stream stage operation device comprises a Pseudo-Random Binary Sequence (PRBS) generator 101, a sample-and-hold circuit 102, a dynamic matching sub-ADC DEM 103, and a multiplying digital-to-analog converter 104. The multiplying digital-to-analog converter is connected to the dynamic matching sub-ADC DEM and the sample-and-hold circuit, respectively. The dynamic matching sub-ADC DEM is connected to the PRBS generator.

[0048] As shown in Figure 2 The dynamic matching sub-ADC DEM comprises a gating switch array, a comparator array, a plurality of resistors, and a coding circuit. The number of switches in the gating switch array is the same as and one-to-one corresponds to the number of comparators in the comparator array. The number of resistors is one more than the number of comparators. The plurality of resistors are connected in series. The connection ends of each adjacent two resistors are connected to the first ends of different gating switches in the gating switch array. The second ends of the gating switches are connected to the positive input ends of the comparators corresponding to the gating switches. The negative input ends of each comparator are connected to an input voltage. The output ends of the comparators are connected to the coding circuit.

[0049] The multiplying digital-to-analog converter comprises a sub-DAC and a residue amplifier. The input end of the sub-DAC is connected to the sample-and-hold circuit and the dynamic matching sub-ADC DEM. The output end of the sub-DAC is connected to the input end of the residue amplifier.

[0050] The sub-DAC comprises two groups of sampling capacitors and two groups of sampling switches. The number of sampling capacitors in each group of sampling capacitors is the same as the number of comparators in the comparator array. The number of switches in each group of sampling switches is the same as the number of sampling capacitors in each group of sampling capacitors. Each two sampling switches are connected in parallel to connect a sampling capacitor. One end of each sampling capacitor is connected to two corresponding parallel sampling switches, respectively. The other end of the sampling capacitor is connected to the residue amplifier. As shown in Figure 2 One group of sampling switches is connected to a reference voltage VREFP, and the other group of sampling switches is connected to a reference voltage VREFN. Each sampling capacitor corresponds to a pair of sampling switches, one of which is connected to the reference voltage VREFP, and the other of which is connected to the reference voltage VREFN.

[0051] As shown in Figure 1As shown, the pseudo-random code generator 101 is used to generate pseudo-random codes and send them to the dynamic matching sub-analog-to-digital converter.

[0052] The sample-and-hold circuit 102 is used to sample and hold the input voltage to obtain the input signal, which is then sent to the multiplication digital-to-analog converter.

[0053] The dynamic matching sub-analog-to-digital converter 103 is used to dynamically match the threshold voltage of the comparator according to the pseudo-random code sent by the pseudo-random code generator, quantize the input voltage according to the dynamically matched threshold voltage, obtain the quantization result, and send it to the multiplication digital-to-analog converter.

[0054] The multiplier-to-analog converter 104 is used to restore the quantization result to an analog quantity, and perform a residual amplification operation with the input signal sent by the sample-and-hold circuit to obtain the residual voltage.

[0055] like Figure 2 As shown, the gating switch array is used to select the switches between the comparator array and multiple resistors according to the pseudo-random code, and dynamically match the voltage division of each comparator in the comparator array.

[0056] A comparator array is used to compare the obtained voltage division with the input voltage as a threshold voltage to obtain the comparison result (D). <0> To D <5> ), and send it to the encoding circuit.

[0057] The encoding circuit is used to quantize the comparison results, obtain the quantized results, and send them to the multiplication digital-to-analog converter.

[0058] Multiple resistors are used for voltage division.

[0059] like Figure 3 As shown, the multiplication digital-to-analog converter includes:

[0060] The sub-ADC is used to restore the quantization result to an analog quantity. It performs a residual difference operation on the analog quantity and the input signal sent by the sample-and-hold circuit to obtain the residual difference, which is then sent to the residual difference amplifier.

[0061] A residual amplifier is used to amplify the residual voltage to obtain the residual voltage.

[0062] The sub-digital-to-analog converter, specifically, is used to control each group of switches in the sub-digital-to-analog converter according to the quantization result, dynamically match the reference voltage of the capacitor corresponding to each group of switches, and perform residual difference calculation on the reference voltage and the input signal sent by the sample-and-hold circuit to obtain the residual difference.

[0063] A pseudo-random code generator, consisting of D flip-flops and logic gates, is used to generate pseudo-random codes through logical operations. The generator produces a random code sequence within a certain period; this sequence exhibits no regularity and serves as the pseudo-random code.

[0064] The application will be further described below with reference to the embodiments of the application, as shown in Figure 4

[0065] Figure 4 The working principle of a 2.5-bit multiplying digital-to-analog converter is shown in the figure. The input voltage is a differential power supply Vinn and Vinp. The quantization result of the dynamic matching sub-analog-to-digital converter is input to the sub-digital-to-analog converter. The switch in the sub-digital-to-analog converter is turned on or off according to the quantization result, thereby changing the reference voltage V REFP and V REFN .

[0066] The output thermometer code digital signal of the comparator controls the working of the multiplying digital-to-analog converter. The output of each comparator determines whether the reference voltage connected to the upper plate of the corresponding sampling capacitor is vref or -vref, and outputs the residual signal through the operational amplifier in a closed loop.

[0067] In the dynamic matching sub-analog-to-digital converter, the threshold voltage of each comparator is obtained by voltage division of the resistor string. Each comparator corresponds to a threshold voltage. The input signal (input voltage) is compared with different threshold voltages respectively, and the quantization result (N-bit thermometer code) is output. The comparator corresponding to a higher threshold voltage outputs a high bit of the thermometer code, and the comparator corresponding to a lower threshold voltage outputs a low bit of the thermometer code.

[0068] Generally, the threshold voltage in the sub-analog-to-digital converter corresponds to the comparator, and the sampling capacitor in the sub-digital-to-analog converter is one-to-one and remains unchanged, that is, threshold voltage A corresponds to comparator A, comparator A corresponds to sampling capacitor A, threshold voltage B (threshold voltage B is different from threshold voltage A) corresponds to comparator B, and comparator B corresponds to sampling capacitor B. However, due to the process, the actual capacitance value of each sampling capacitor is different, thereby causing capacitor mismatch. Since the threshold voltage corresponding to the comparator is fixed, and the corresponding relationship between each comparator and the sampling capacitor is fixed, a fixed error is generated. The fixed error generates a harmonic wave, thereby affecting the performance of the analog-to-digital converter.

[0069] The embodiments of the application add a gating switch array controlled by a pseudo-random code between the threshold voltage generated by the resistor string and the comparator, thereby breaking the corresponding relationship between the threshold voltage and the comparator. Since each comparator corresponds to a sampling capacitor in the sub-digital-to-analog converter, it is equivalent to breaking the corresponding relationship between each comparator in the comparator array and the sampling capacitor during each working of the sub-digital-to-analog converter.

[0070] ​Since the corresponding sampling capacitance is randomly determined by each quantization, the mismatch between different sampling capacitances can be averaged in each quantization, the dynamic element matching of the sampling capacitance is realized, and the harmonic distortion is averaged as the bottom noise in the frequency spectrum obtained by Fourier transform of the output digital code of the digital-to-analog converter. The linearity and total harmonic distortion parameters of the entire ADC system are effectively improved.

[0071] As shown in Figure 5 , clock signals CLKS and CLKF are sampling clock and holding clock of the multiplication digital-to-analog converter in the pipeline, respectively, wherein the downward arrow indicates that sampling is performed at the falling edge of the clock. The two clocks are two-phase non-overlapping clocks. When CLKS is high, the analog-to-digital converter of the pipeline stage is at the sampling time, the sampling switch is turned on, the input signal is sampled, and the comparator threshold voltage selection process is performed; when CLKF is high, the analog-to-digital converter of the pipeline stage is at the output holding time, the comparator compares, outputs the coarse quantization digital code (quantization result), and controls the multiplication digital-to-analog converter to work.

[0072] Compared with the existing method as shown in Figure 6 , a dynamic element matching technology (DEM) is added to the encoding circuit of the sub digital-to-analog converter (sub DAC) of the multiplication digital-to-analog converter at each stage. In the embodiment of the application, a gating switch array controlled by a pseudo-random code is added between the threshold voltage generated by the resistor string and the comparator, which disrupts the correspondence between the threshold voltage and the comparator, which is equivalent to disrupting the correspondence between the comparator array and the sampling capacitance during the operation of each sub ADC. The pseudo-random code array includes a D flip-flop and a logic gate, and a random code column in a certain period is obtained through logic operation. The code column has no regularity. Perfecting the pseudo-random algorithm can as long as possible to extend the repetition period, and realize the random code column in a long period of time.

[0073] Since the threshold voltage of the comparator only needs to be prepared before the comparator compares, and is in an idle state at other times, the dynamic matching technology of the threshold voltage can be applied to the entire analog-to-digital conversion holding period, and the comparison and quantization of the sub digital-to-analog converter are prepared in advance, so that there is sufficient time for dynamic matching, and the valuable time margin for small signal establishment of the operational amplifier is not occupied, which is crucial in high-speed digital-to-analog conversion.

[0074] In a second aspect, according to the embodiment of the application, a pipeline analog-to-digital converter is also provided, as shown in Figure 7 , comprising: a register, a digital correction module, a clock circuit, and a plurality of pipeline stage operation devices;

[0075] A plurality of pipeline operation devices are configured to quantize the input voltage to obtain quantization results and send the quantization results to a register.

[0076] The plurality of pipeline operation devices are connected in series, the register is connected to the plurality of pipeline operation devices, the digital correction module is connected to the register, and the clock circuit is connected to the plurality of pipeline operation devices.

[0077] The register is configured to receive and process the quantization results sent by the pipeline operation devices to obtain quantization output results and send the quantization output results to the digital correction module.

[0078] The digital correction module is configured to determine a digital signal according to the quantization output results and output the digital signal.

[0079] The clock circuit is configured to generate a clock signal for controlling all the pipeline operation devices.

[0080] The first pipeline operation device is the pipeline operation device described above and includes a dynamic matching sub-ADC, a sample-and-hold device, a pseudo-random code generator, and a multiplying D / A converter, and the dynamic matching sub-ADC is connected to the pseudo-random code generator.

[0081] The second pipeline includes:

[0082] The sample-and-hold device is configured to sample and hold the input voltage to obtain an input signal and send the input signal to the sub-ADC.

[0083] The sub-ADC is configured to quantize the input voltage according to the threshold voltage of the comparator to obtain quantization results and send the quantization results to the sub-ADC.

[0084] The sub-ADC is configured to restore the quantization results to an analog quantity, perform a residual difference amplification operation on the input signal sent by the sample-and-hold device to obtain a residual voltage, and send the residual voltage to the next pipeline.

[0085] The pipeline ADC provided by the embodiments of the present application can be configured with a corresponding number of pipeline operation devices including a sample-and-hold device, a pseudo-random code generator, a dynamic matching sub-ADC, and a multiplying D / A converter in each pipeline as needed, and does not need to include a sample-and-hold device, a pseudo-random code generator, a dynamic matching sub-ADC, and a multiplying D / A converter in each pipeline.

[0086] In the method of the present application, a pseudo-random code is generated by a pseudo-random code generator, a dynamic element matching technique is used to break the original correspondence of the device, a random control code is used to rearrange the distribution of the device, the resonance frequency generated by the system due to the mismatch of the device is reduced, the threshold voltage of the comparator array of the dynamic matching sub-ADC in the pipeline stage is controlled, and then the dynamic matching of each capacitor (sampling capacitor) in the capacitor array in the multiplication D / A converter is realized. Since the threshold voltage of the comparator only needs to be prepared before the comparison of the comparator, the dynamic matching technology of the threshold voltage can be used in the entire holding period of the analog-to-digital conversion, and the comparison quantization of the multiplication D / A converter is prepared in advance, so that the capacitor mismatch caused by the process error, the manufacturing process, etc. can be scattered without occupying the analog-to-digital conversion time, thereby reducing the harmonic distortion and improving the linearity of the analog-to-digital converter.

[0087] The above merely describes the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A flow water level operation device characterized by, The application relates to a pipeline operation device. The pipeline operation device comprises a dynamic matching sub-analog-digital converter, a sample-and-hold device, a pseudo-random code generator and a multiplication digital-analog converter. The multiplication digital-analog converter is connected with the dynamic matching sub-analog-digital converter and the sample-and-hold device respectively, and the dynamic matching sub-analog-digital converter is connected with the pseudo-random code generator. The dynamic matching sub-analog-digital converter comprises a gating switch array, a comparator array, a plurality of resistors and a coding circuit. The number of switches in the gating switch array is the same as and corresponds to the number of comparators in the comparator array; and the number of the resistors is one more than the number of the comparators. The plurality of resistors are connected in series; the connection ends of each two adjacent resistors are connected with the first ends of different gating switches in the gating switch array; the second ends of the gating switches are connected with the positive input ends of the comparators corresponding to the gating switches; the negative input ends of each comparator are connected with an input voltage; and the output ends of the comparators are connected with the coding circuit.

2. The flow stage operation device according to claim 1, wherein The multiplication digital-analog converter comprises a sub-digital-analog converter and a residual error amplifier. The input end of the sub-digital-analog converter is connected with the sample-and-hold device and the dynamic matching sub-analog-digital converter; and the output end of the sub-digital-analog converter is connected with the input end of the residual error amplifier.

3. The flow stage arithmetic device according to claim 2, wherein The sub-digital-analog converter comprises two groups of sampling capacitors and two groups of sampling switches. The number of sampling capacitors in each group of the sampling capacitors is the same as the number of comparators in the comparator array; the number of switches in each group of the sampling switches is the same as the number of sampling capacitors in each group of the sampling capacitors; and each two sampling switches are connected with a sampling capacitor in parallel. One end of each sampling capacitor is connected with two corresponding parallel sampling switches respectively; and the other end of the sampling capacitor is connected with the residual error amplifier.

4. The flow stage operation device according to claim 1, wherein The pseudo-random code generator comprises a D flip-flop and a logic gate, and is used for obtaining a pseudo-random code through logic operation.

5. The pipeline operation device according to claim 1, wherein the pseudo-random code generator is used for generating a pseudo-random code and sending the pseudo-random code to the dynamic matching sub-analog-digital converter; the sample-and-hold device is used for sampling and holding an input voltage to obtain an input signal and sending the input signal to the multiplication digital-analog converter; the dynamic matching sub-analog-digital converter is used for dynamically matching a threshold voltage according to the pseudo-random code sent by the pseudo-random code generator, quantizing the input voltage according to the threshold voltage after dynamic matching to obtain a quantization result and sending the quantization result to the multiplication digital-analog converter; and the multiplication digital-analog converter is used for restoring the quantization result to an analog quantity and performing residual error amplification operation on the input signal sent by the sample-and-hold device to obtain a residual voltage.

6. The pipeline operation device according to claim 1, wherein the gating switch array is used for dynamically matching the voltage division of each comparator in the comparator array according to the gating of the pseudo-random code; the comparator array is used for taking the obtained voltage division as a threshold voltage, comparing the threshold voltage with the input voltage and sending the comparison result to the coding circuit; the coding circuit is used for quantizing the comparison result to obtain a quantization result and sending the quantization result to the multiplication digital-analog converter; and the plurality of resistors are used for voltage division.

7. The pipeline operation device according to claim 2, wherein The sub-digital-to-analog converter is configured to restore the quantization result to an analog quantity, perform a difference operation on the analog quantity and an input signal sent by the sample-and-hold device, obtain a difference, and send the difference to the difference amplifier. The difference amplifier is configured to amplify the difference to obtain a difference voltage.

8. The flow stage arithmetic device according to claim 7, wherein The sub-digital-to-analog converter is configured to control groups of switches in the sub-digital-to-analog converter according to the quantization result, dynamically match a reference voltage of a sampling capacitor corresponding to each group of switches in the sub-digital-to-analog converter, perform a difference operation on the reference voltage and an input signal sent by the sample-and-hold device, and obtain a difference.

9. A pipelined analog-to-digital converter, characterized by The device comprises: a register, a digital correction module, a clock circuit, and a plurality of pipeline operation devices; The plurality of pipeline operation devices are configured to quantize an input voltage to obtain a quantization result, and send the quantization result to the register. The plurality of pipeline operation devices are connected in series. The register is connected to the plurality of pipeline operation devices. The digital correction module is connected to the register. The clock circuit is connected to the plurality of pipeline operation devices. The register is configured to receive and process the quantization result sent by each pipeline operation device to obtain a quantization output result, and send the quantization output result to the digital correction module. The digital correction module is configured to determine a digital signal according to the quantization output result and output the digital signal. The clock circuit is configured to generate a clock signal for controlling all the pipeline operation devices. The first pipeline operation device is the pipeline operation device comprising the dynamically matching sub-digital-to-analog converter, the sample-and-hold device, the pseudo-random code generator, and the multiplication digital-to-analog converter, and the dynamically matching sub-digital-to-analog converter is connected to the pseudo-random code generator.

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