Display panel, driving method thereof, and display device

Abstract

A display panel, a driving method thereof and a display device, wherein the display panel comprises a display area (110) and a non-display area (120); the non-display area (120) comprises a first binding area (210), and further comprises a first connecting line (220) connected with a plurality of gate lines (111) and a second connecting line (230) connected with a plurality of data lines (112); the display panel further comprises at least one chip on film (240), which comprises a second binding area (241), a first area (242) and a second area (243) between the second binding area (241) and the first area (242); wherein the first area (242) is respectively bound with a scan driving integrated circuit (250) and a data driving integrated circuit (260), the scan driving integrated circuit (250) is connected with the second binding area (241) through a first wire (251), and the data driving integrated circuit (260) is connected with the second binding area (241) through a second wire (261); the first wire (251) and the second wire (261) are arranged in layers in the second area (243). The display panel, the driving method thereof and the display device can facilitate the narrow frame design of the display device as a whole.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device. Background Art

[0002] With the continuous advancement of science and technology, people's pursuit of beauty is becoming increasingly strong, and the development and maturity of narrow-border or even borderless technology for display devices is imminent.

[0003] In related art, by concentrating the driver integrated circuits of each display device on one side of the display area, narrow bezels can be achieved on the other three sides of the display area. However, the bezel width on the side where the driver integrated circuits are located increases, and the overall narrow bezel or bezel-free effect is poor. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel, a driving method thereof, and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the plurality of gate lines and the plurality of data lines intersect to define a plurality of pixel areas;

[0006] The non-display area includes at least one first binding area located on one side of the display area, the non-display area also including first connecting lines correspondingly connected to a plurality of gate lines and second connecting lines correspondingly connected to a plurality of data lines, at least a portion of each of the first connecting lines and at least a portion of each of the second connecting lines being used for binding connection, and portions of the first connecting lines and the second connecting lines used for binding connection being located in the first binding area;

[0007] The display panel also includes at least one chip-on-chip film, which includes a second binding area, and the second binding area is bound and connected to the first binding area; the chip-on-chip film also includes a first area and a second area located between the second binding area and the first area; wherein, a scan driver integrated circuit and a data driver integrated circuit are respectively bound in the first area, the scan driver integrated circuit is connected to the second binding area through a first routing line, and the data driver integrated circuit is connected to the second binding area through a second routing line; the first routing line and the second routing line are layered in the second area.

[0008] Furthermore, a plurality of binding electrodes are provided in the second binding area, and the binding electrodes include a first binding electrode and a second binding electrode. The first binding electrode is connected to the first routing line in a one-to-one correspondence, and the second binding electrode is connected to the second routing line in a one-to-one correspondence. The first binding electrode and the second binding electrode are located on the same side of the flip chip film.

[0009] Furthermore, the binding electrode, the scan driver integrated circuit, and the data driver integrated circuit are located on the same side of the chip-on-film;

[0010] The third trace is located on the same side of the COF as the scan driver integrated circuit and the data driver integrated circuit; the COF further includes a third region located between the first region and the second region, and a fourth region located between the second binding region and the second region, the third region having a first via hole and the fourth region having a second via hole;

[0011] The fourth trace includes a first distribution segment connected to the second binding region, a second distribution segment connected to the target driver integrated circuit, and a third distribution segment connected to the second distribution segment through the first via and connected to the first distribution segment through the second via, wherein the second distribution segment and the third distribution segment are located on the same side of the chip-on-film as the third trace;

[0012] The third routing is the first routing, the fourth routing is the second routing, and the target driver integrated circuit is the data driver integrated circuit; or the third routing is the second routing, the fourth routing is the first routing, and the target driver integrated circuit is the scan driver integrated circuit.

[0013] Furthermore, the scan driver integrated circuit and the data driver integrated circuit are located on the same side of the chip-on-film, and the binding electrode is located on the other side of the chip-on-film;

[0014] The chip-on-film further includes a third region located between the first region and the second region, and a fourth region located between the second binding region and the second region, the third region is provided with a first via hole, and the fourth region is provided with a second via hole;

[0015] The third trace includes a first distribution segment connecting the first driver integrated circuit and the second via, and a second distribution segment connecting the first distribution segment and the second binding area through the second via;

[0016] The fourth trace includes a third distribution segment connecting the second binding area and the first via, and a fourth distribution segment connecting the third distribution segment and the second driver integrated circuit through the first via, wherein the first distribution segment and the third distribution segment are arranged in layers;

[0017] The third routing is the first routing, the fourth routing is the second routing, the first driver integrated circuit is the scan driver integrated circuit, and the second driver integrated circuit is the data driver integrated circuit; or, the third routing is the second routing, the fourth routing is the first routing, the first driver integrated circuit is the data driver integrated circuit, and the second driver integrated circuit is the scan driver integrated circuit.

[0018] Furthermore, the binding electrode and the first driver integrated circuit are located on the same side of the chip-on-film, and the second driver integrated circuit is located on the other side of the chip-on-film;

[0019] The third trace, the binding electrode, and the first driver integrated circuit are located on the same side of the COF; the COF further includes a third region located between the first region and the second region, and a fourth region located between the second binding region and the second region, wherein a third via is formed in the fourth region;

[0020] The fourth trace includes a first distribution segment connecting the second driver integrated circuit and the third via, and a second distribution segment connecting the first distribution segment and the second binding area through the third via;

[0021] The third routing is the first routing, the fourth routing is the second routing, the first driver integrated circuit is the scan driver integrated circuit, and the second driver integrated circuit is the data driver integrated circuit; or, the third routing is the second routing, the fourth routing is the first routing, the first driver integrated circuit is the data driver integrated circuit, and the second driver integrated circuit is the scan driver integrated circuit.

[0022] Furthermore, the second binding area includes a plurality of repeating units, wherein each repeating unit includes a first low-potential signal electrode, at least one first binding electrode and at least one second binding electrode.

[0023] Furthermore, each of the repeating units includes P first binding electrodes and Q second binding electrodes.

[0024] Furthermore, the chip-on-film further includes first low-potential signal lines connected to the first low-potential signal electrodes in a one-to-one correspondence;

[0025] The first low-potential signal line is arranged in the second area on the same layer as the first routing line, and the first low-potential signal line is electrically connected to the scan driver integrated circuit; or, the first low-potential signal line is arranged in the second area on the same layer as the second routing line, and the first low-potential signal line is electrically connected to the data driver integrated circuit.

[0026] Furthermore, the first binding area includes a plurality of second low-potential signal electrodes, and Z signal transmission lines are provided between two adjacent second low-potential signal electrodes. The Z signal transmission lines include first connecting lines and / or second connecting lines.

[0027] Furthermore, the Z signal transmission lines include X first connecting lines and Y second connecting lines.

[0028] Furthermore, two scan driver integrated circuits on two adjacent chip-on-films are connected via scan input / output signal lines, and two data driver integrated circuits on two adjacent chip-on-films are connected via data input / output signal lines.

[0029] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel as described above.

[0030] Furthermore, the display device further includes a power management circuit and a timing control circuit, wherein the power management circuit is used to provide an operating voltage to the timing control circuit;

[0031] The timing control circuit is used to provide a timing signal to the chip-on-film;

[0032] The power management circuit is further configured to provide a digital voltage signal and an analog voltage signal to the chip-on-film.

[0033] In a third aspect, an embodiment of the present disclosure further provides a method for driving a display panel, the method comprising:

[0034] The scan driver integrated circuit on the at least one flip chip film sequentially provides a gate scan signal to each gate line through the first routing line, the second binding area, the first binding area and the first connecting line in a time-sharing manner, wherein when the gate scan signal is provided to one gate line, the data driver integrated circuit on the at least one flip chip film sequentially provides a data signal to each data line through the second routing line, the second binding area, the first binding area and the second connecting line.

[0035] Furthermore, two scan driver integrated circuits on two adjacent chip-on-films are connected via scan input / output signal lines, and two data driver integrated circuits on two adjacent chip-on-films are connected via data input / output signal lines.

[0036] The step of providing gate scanning signals to each gate line in a time-sharing manner in sequence through the first wiring, the second binding area, the first binding area and the first connecting line comprises:

[0037] After the scan drive circuit in the first chip on film sequentially provides a gate scan signal to the first gate line through the first routing line, the second binding area, the first binding area, and the first connecting line in a time-sharing manner, the first chip on film sends a scan start signal to the second chip on film through the scan input and output signal line; the first chip on film and the second chip on film are two adjacent chip films, and the first gate line is a gate line electrically connected to the scan drive circuit in the first chip on film;

[0038] After the second chip-on-film receives the scan start signal, the scan drive circuit in the second chip-on-film provides a gate scan signal to the second gate line in a time-sharing manner through the first routing line, the second binding area, the first binding area and the first connecting line. The second gate line is a gate line electrically connected to the scan drive circuit in the second chip-on-film.

[0039] Furthermore, the step of providing data signals to the data lines via the second wiring, the second binding area, the first binding area and the second connection line in sequence comprises:

[0040] After the data driver integrated circuit on the first chip on film provides a data signal to the first data line through the second routing line, the second binding area, the first binding area, and the second connecting line, the first chip on film sends a data start signal to the second chip on film through the data input and output signal line; the first data line is a data line electrically connected to the data driver circuit in the first chip on film;

[0041] After the second chip-on-film receives the data-on signal, the data driving circuit in the second chip-on-film provides a data signal to the second data line in a time-sharing manner through the second routing line, the second binding area, the first binding area and the second connecting line. The second data line is a data line electrically connected to the data driving circuit in the second chip-on-film. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic structural diagram of a display substrate in a display panel provided in an embodiment of the present disclosure;

[0043] Figure 2 A schematic structural diagram of a chip-on-film in a display panel provided by another embodiment of the present disclosure;

[0044] Figure 3 A schematic structural diagram of a chip-on-film in a display panel provided by another embodiment of the present disclosure;

[0045] Figure 4 To correspond Figure 3 Schematic diagram of the wiring;

[0046] Figure 5 A schematic structural diagram of a chip-on-film in a display panel provided by another embodiment of the present disclosure;

[0047] Figure 6 To correspond Figure 5 Schematic diagram of the wiring;

[0048] Figure 7 A schematic structural diagram of a chip-on-film in a display panel provided by another embodiment of the present disclosure;

[0049] Figure 8 To correspond Figure 7 Schematic diagram of the wiring;

[0050] Figure 9 A schematic structural diagram of a chip-on-film in a display panel provided by another embodiment of the present disclosure;

[0051] Figure 10 A schematic structural diagram of a first binding area in a display panel provided in another embodiment of the present disclosure;

[0052] Figure 11 A schematic diagram of the connections between chip-on-films in a display panel provided by another embodiment of the present disclosure;

[0053] Figure 12 A schematic structural diagram of a display device provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] The present disclosure provides a display panel. Figure 1 and Figure 2 As shown, it includes a display area 110 and a non-display area 120, wherein the display area 110 includes a plurality of gate lines 111 extending along a first direction and a plurality of data lines 112 extending along a second direction, and the plurality of gate lines 111 and the plurality of data lines 112 intersect to define a plurality of pixel areas;

[0055] The non-display area 120 includes at least one first binding area 210 located on one side of the display area 110. The non-display area 120 also includes first connection lines 220 correspondingly connected to the plurality of gate lines 111 and second connection lines 230 correspondingly connected to the plurality of data lines 112. At least a portion of each of the first connection lines 220 and at least a portion of each of the second connection lines 230 are used for binding connection, and the portions of the first connection lines 220 and the second connection lines 230 used for binding connection are located in the first binding area 210.

[0056] The display panel also includes at least one chip-on-chip film 240, which includes a second binding area 241, which is bound and connected to the first binding area 210; the chip-on-chip film 240 also includes a first area 242 and a second area 243 located between the second binding area 241 and the first area 242; wherein, a scan driver integrated circuit 250 and a data driver integrated circuit 260 are respectively bound in the first area 242, the scan driver integrated circuit 250 is connected to the second binding area 241 through a first routing 251, and the data driver integrated circuit 260 is connected to the second binding area 241 through a second routing 261; the first routing 251 and the second routing 261 are layered in the second area 243.

[0057] In the disclosed embodiments, a scan driver integrated circuit and a data driver integrated circuit are bonded to the same chip-on-film and to a first bonding area in the non-display area, replacing the larger GOA (Growth of Array) substrate row driver unit. This allows for a narrow-frame design of the display device without affecting normal gate line scanning. Therefore, the technical solution provided by the disclosed embodiments facilitates a narrow-frame design of the display device.

[0058] like Figure 1 As shown, the non-display area 120 is located around the display area 110 and may be arranged to surround the display area 110 .

[0059] The first direction may be a row direction of the display panel, and the second direction may be a column direction of the display panel; of course, the first direction and the second direction may also be other two directions that may intersect with each other, which is not limited here.

[0060] A thin film transistor (TFT) and a pixel electrode are provided in each pixel region. The source of the TFT is connected to the data line, the drain of the TFT is connected to the pixel electrode, and the gate of the TFT is connected to the gate line.

[0061] The non-display area 120 includes at least one first binding area 210, all of which are located on the same side of the display area 110. The non-display area 120 also includes a first connection line 220 for connecting the first binding area 210 and the gate line 111, and a second connection line 230 for connecting the first binding area 210 and the data line 112. Both the first connection line 220 and the second connection line 230 include portions bound within the first binding area 210. Furthermore, the first connection line 220 may also include a portion connected to the gate line 111 within the display area 110, which serves as an on-screen trace.

[0062] The second binding area 241 in the Chip On Film (COF) 240 is bound and connected to the first binding area 210 in the non-display area 120 , thereby achieving transmission of electrical signals from the COF 240 to the display substrate.

[0063] A scan driver integrated circuit 250 and a data driver integrated circuit 260 are bound to the first region 242 of the COF 240. The scan driver integrated circuit 250 is used to generate a scan signal, which is transmitted via a first trace 251 to the second binding region 241, then to the first binding region 210, and then to the gate line via a first connection line 220, thereby turning on the source and drain electrodes of the TFTs in the pixel region. The data driver integrated circuit 260 is used to generate a data signal, which is transmitted via a second trace 261 to the second binding region 241, then to the first binding region 210, and then to the data line via a second connection line 230, thereby charging the pixel electrode connected to the drain electrode of the TFT via the source electrode of the TFT, causing each light-emitting device in the display region 110 to emit light, thereby realizing image display of the display device.

[0064] Among them, the first routing line 251 and the second routing line 261 are layered in the second area 243, which can reduce or even eliminate the signal crosstalk between the scanning signal on the first routing line 251 and the data signal on the second routing line 261, thereby improving the quality of signal transmission; in addition, it can also reduce the wiring space of the flip chip film, thereby reducing the size of the flip chip film.

[0065] The chip-on-film can be folded to the back of the display panel, so the chip-on-film itself does not occupy the space of the non-display area of ​​the display panel. It is only necessary to set a first binding area in the non-display area of ​​the display panel to bind and connect it to the chip-on-film. And because the scan driver integrated circuit and the data driver integrated circuit are set on a chip-on-film at the same time, the binding area can be set only on one side of the display panel, thereby reducing the area of ​​the non-display area, so that the width of the widest frame among the four side frames of the display area is less than 1.5mm, realizing an ultra-narrow frame of the display device.

[0066] Furthermore, a plurality of binding electrodes are provided in the second binding area 241 , and the binding electrodes include a first binding electrode 291 and a second binding electrode 292 . The first binding electrode 291 is connected to the first trace 251 in a one-to-one correspondence, and the second binding electrode 292 is connected to the second trace 261 in a one-to-one correspondence. The first binding electrode 291 and the second binding electrode 292 are located on the same side of the chip-on-film 240 .

[0067] In this embodiment, the first binding electrode 291 receives the scan signal provided by the scan driver integrated circuit 250 through the first wiring 251, and transmits the scan signal to the first binding area 210; the second binding electrode 292 receives the data signal provided by the data driver integrated circuit 260 through the second wiring 261, and transmits the data signal to the first binding area 210.

[0068] To facilitate transmission of scan signals and data signals to the first binding region 210 , the first binding electrode 291 and the second binding electrode 292 may both be disposed on a side of the COF 240 facing the first binding region 210 .

[0069] In an optional embodiment, if Figure 3 and Figure 4 As shown, the binding electrode, the scan driver integrated circuit 250 and the data driver integrated circuit 260 are located on the same side of the chip-on-film 240;

[0070] The third trace 270 is located on the same side of the COF as the scan driver integrated circuit 250 and the data driver integrated circuit 260. The COF 240 further includes a third region 244 located between the first region 242 and the second region 243, and a fourth region 245 located between the second binding region 241 and the second region 243. The third region 244 is provided with a first via hole 2441, and the fourth region 245 is provided with a second via hole 2451 (e.g., Figure 3 and Figure 4 Mark 2451 in);

[0071] The fourth trace 280 includes a first distribution segment 281 connected to the second binding region 241, a second distribution segment 282 connected to the target driver integrated circuit, and a third distribution segment 283 connected to the second distribution segment 282 through the first via 2441 and connected to the first distribution segment 281 through the second via 2451. The second distribution segment 282, the first distribution segment 281, and the third trace 270 are located on the same side of the chip-on-film.

[0072] The third routing line 270 is the first routing line 251, the fourth routing line 280 is the second routing line 261, and the target driver integrated circuit is the data driver integrated circuit 260; or, the third routing line 270 is the second routing line 261, the fourth routing line 280 is the first routing line 251, and the target driver integrated circuit is the scan driver integrated circuit 250.

[0073] In this embodiment, one of the first trace 251 and the second trace 261 is located on the same side as the binding electrode, and the other trace is located in the second region 243 on a different side from the binding electrode.

[0074] Specifically, when the third wiring 270 is the first wiring 251 , the fourth wiring 280 is the second wiring 261 , and the target driver integrated circuit is the data driver integrated circuit 260 :

[0075] The first routing line 251, the scan driver integrated circuit 250, and the data driver integrated circuit 260 are located on the same side of the chip-on-film. The second routing line 261 includes a first distribution segment connected to the second binding area 241, a second distribution segment connected to the data driver integrated circuit, and a third distribution segment connected to the second distribution segment through the first via 2441 and connected to the first distribution segment through the second via 2451. The second distribution segment and the third distribution segment are located on the same side of the chip-on-film as the first routing line 251.

[0076] When the third routing line 270 is the second routing line 261 , the fourth routing line 280 is the first routing line 251 , and the target driver integrated circuit is the scan driver integrated circuit 250 :

[0077] The second routing line 261, the scan driver integrated circuit 250, and the data driver integrated circuit 260 are located on the same side of the chip-on-chip film; the first routing line 251 includes a first distribution section connected to the second binding area 241, a second distribution section connected to the scan driver integrated circuit, and a third distribution section connected to the second distribution section through the first via 2441 and connected to the first distribution section through the second via 2451. The second distribution section and the third distribution section are located on the same side of the chip-on-chip film as the second routing line 261.

[0078] In another optional embodiment, as Figure 5 and Figure 6 As shown, the scan driver integrated circuit 250 and the data driver integrated circuit 260 are located on the same side of the chip-on-film 240 , and the binding electrode is located on the other side of the chip-on-film 240 ;

[0079] The COF 240 further includes a third region 244 located between the first region 242 and the second region 243 , and a fourth region 245 located between the second binding region 241 and the second region 243 . The third region 244 defines a first via hole 2441 , and the fourth region 245 defines a second via hole 2451 .

[0080] The third trace 270 includes a first distribution segment 271 connecting the first driver integrated circuit and the second via 2451 , and a second distribution segment 272 connecting the first distribution segment 271 and the second binding area 241 through the second via 2451 ;

[0081] The fourth trace 280 includes a third distribution segment 281 connecting the second binding area 241 and the first via 2441, and a fourth distribution segment 282 connecting the third distribution segment 281 and the second driver integrated circuit through the first via 2441. The first distribution segment 271 and the third distribution segment 281 are respectively located on both sides of the chip-on-film 240.

[0082] The third routing 270 is the first routing 251, the fourth routing 280 is the second routing 261, the first driver integrated circuit is the scan driver integrated circuit 250, and the second driver integrated circuit is the data driver integrated circuit 260; or, the third routing 270 is the second routing 261, the fourth routing 280 is the first routing 251, the first driver integrated circuit is the data driver integrated circuit 260, and the second driver integrated circuit is the scan driver integrated circuit 250.

[0083] In this embodiment, one of the first trace 251 and the second trace 261 is connected to the second binding area 241 on the other side through the first via 2441 , and the other is connected to the second binding area 241 on the other side through the second via 2451 .

[0084] Specifically, when the third wiring 270 is the first wiring 251, the fourth wiring 280 is the second wiring 261, the first driver integrated circuit is the scan driver integrated circuit 250, and the second driver integrated circuit is the data driver integrated circuit 260:

[0085] The first trace 251 includes a first distribution segment connecting the scan driver integrated circuit 250 and the second via 2451 , and a second distribution segment connecting the first distribution segment and the second binding area 241 through the second via 2451 ;

[0086] The second trace 261 includes a third distribution segment 281 connecting the second binding area 241 and the first via 2441, and a fourth distribution segment 282 connecting the third distribution segment 281 and the data driver integrated circuit 260 through the first via 2441. The first distribution segment and the third distribution segment are respectively located on both sides of the chip-on-film 240.

[0087] When the third wiring 270 is the second wiring 261, the fourth wiring 280 is the first wiring 251, the first driver integrated circuit is the data driver integrated circuit 260, and the second driver integrated circuit is the scan driver integrated circuit 250:

[0088] The second trace 261 includes a first distribution segment connecting the data driver integrated circuit 260 and the second via 2451 , and a second distribution segment connecting the first distribution segment and the second binding area 241 through the second via 2451 ;

[0089] The first trace 251 includes a third distribution segment 281 connecting the second binding area 241 and the first via 2441, and a fourth distribution segment 282 connecting the third distribution segment 281 and the scan driver integrated circuit 250 through the first via 2441. The first distribution segment and the third distribution segment are respectively located on both sides of the chip-on-film 240.

[0090] In another optional embodiment, as Figures 7 and 8 As shown, the binding electrode and the first driver integrated circuit are located on the same side of the chip-on-film 240 , and the second driver integrated circuit is located on the other side of the chip-on-film 240 ;

[0091] The third trace 270, the binding electrode, and the first driver integrated circuit are located on the same side of the COF 240; the COF 240 further includes a third region 244 located between the first region 242 and the second region 243, and a fourth region 245 located between the second binding region 241 and the second region 243, wherein the fourth region 245 is provided with a third via hole (such as Figure 7 and Figure 8 Mark 2451 in);

[0092] The fourth trace 280 includes a first distribution segment 281 connecting the second driver integrated circuit and the third via, and a second distribution segment 282 connecting the first distribution segment 281 and the second binding area 241 through the third via.

[0093] The third routing 270 is the first routing 251, the fourth routing 280 is the second routing 261, the first driver integrated circuit is the scan driver integrated circuit 250, and the second driver integrated circuit is the data driver integrated circuit 260; or, the third routing 270 is the second routing 261, the fourth routing 280 is the first routing 251, the first driver integrated circuit is the data driver integrated circuit 260, and the second driver integrated circuit is the scan driver integrated circuit 250.

[0094] In this embodiment, one of the first trace 251 and the second trace 261 is located on the same side as the binding electrode, and the other trace is located in the second region 243 on a different side from the binding electrode.

[0095] Specifically, when the third wiring 270 is the first wiring 251, the fourth wiring 280 is the second wiring 261, the first driver integrated circuit is the scan driver integrated circuit 250, and the second driver integrated circuit is the data driver integrated circuit 260:

[0096] The first trace 251 and the scan driver integrated circuit 250 are located on the same side of the chip-on-film; the second trace 261 includes a first distribution segment connecting the second binding area 241 and the third via, and a second distribution segment connecting the first distribution segment and the data driver integrated circuit 260 through the third via;

[0097] When the third wiring 270 is the second wiring 261 , the fourth wiring 280 is the first wiring 251 , the first driver integrated circuit is the data driver integrated circuit 260 , and the second driver integrated circuit is the scan driver integrated circuit 250 :

[0098] The second routing line 261 and the data driver integrated circuit 260 are located on the same side of the flip chip film; the first routing line 251 includes a first distribution segment connecting the second binding area 241 and the third via, and a second distribution segment connecting the first distribution segment and the scan driver integrated circuit 250 through the third via.

[0099] Further, if Figure 9 As shown, the second binding area 241 includes a plurality of repeating units 246 , wherein each repeating unit 246 includes a first low-potential signal electrode 293 , at least one first binding electrode 291 and at least one second binding electrode 292 .

[0100] By providing the first low-potential signal electrode 293 in each repeating unit 246 , coupling of the scan signal on the first binding electrode 291 and the data signal on the second binding electrode 292 can be prevented.

[0101] Each of the repeating units 246 includes P first binding electrodes and Q second binding electrodes, and both P and Q are positive integers.

[0102] Further, if Figure 9 As shown, the chip-on-film 240 further includes a first low-potential signal line 290 connected to the first low-potential signal electrode 293 in a one-to-one correspondence;

[0103] The first low-potential signal line 290 is arranged in the same layer as the first routing line 251 in the second area 243, and the first low-potential signal line 290 is electrically connected to the scan driver integrated circuit 250; or, the first low-potential signal line 290 is arranged in the same layer as the second routing line 261 in the second area 243, and the first low-potential signal line 290 is electrically connected to the data driver integrated circuit 260.

[0104] The first low-potential signal line 290 is used to prevent the scanning signal on the first wiring 251 and the data signal on the second wiring 261 from being coupled in the second area 243 .

[0105] Further, if Figure 10 As shown, the first binding area 210 includes a plurality of second low-potential signal electrodes 294 , and Z signal transmission lines are provided between two adjacent second low-potential signal electrodes 294 . The Z signal transmission lines include first connection lines 220 and / or second connection lines 230 .

[0106] In this embodiment, the second low-potential signal electrode 294 in the first binding area 210 may be bound and connected to the first low-potential signal electrode 293 in the second binding area 241 .

[0107] The first binding region 219 may further include a third binding electrode 295 and a fourth binding electrode 296. The third binding electrode 295 is bonded to the first binding electrode 291, and the fourth binding electrode 296 is bonded to the second binding electrode 292. The second low-potential signal electrode 294 prevents coupling between the scan signal on the third binding electrode 295 and the data signal on the fourth binding electrode 296.

[0108] Among them, the connection relationship between the third binding electrode 295 and the first connecting line 220 can be that they are electrically connected to each other after being formed separately, or the third binding electrode 295 can be the part of the first connecting line located in the first binding area 219, that is, the third binding electrode 295 and the first connecting line 220 are formed integrally; similarly, the connection relationship between the fourth binding electrode 296 and the second connecting line 230 can be that they are electrically connected to each other after being formed separately, or the fourth binding electrode 296 can be the part of the second connecting line 230 located in the first binding area 219, that is, the fourth binding electrode 296 and the second connecting line 230 are formed integrally.

[0109] In addition, the display panel may further include a second low-potential signal line 211 connected in a one-to-one correspondence with the second low-potential signal electrode 294. The second low-potential signal line 211 is used to prevent the scanning signal on the first connection line 220 and the data signal on the second connection line 230 from coupling within the non-display area 120. A first end of the second low-potential signal line 211 is electrically connected to the second low-potential signal electrode 294, and a second end of the second low-potential signal line 211 may be located at an edge of the non-display area or midway between the display area and the first binding area 210, without limitation herein.

[0110] The Z signal transmission lines include X first connection lines and Y second connection lines, and both X and Y are positive integers.

[0111] Further, if Figure 11 As shown, two scan driver integrated circuits 250 on two adjacent COFs 240 are connected via scan input / output signal lines 310 , and two data driver integrated circuits 320 on two adjacent COFs 240 are connected via data input / output signal lines 320 .

[0112] In this embodiment, in the case of a large-scale display device, it is difficult for one COF 240 to control all gate lines and data lines. Therefore, a plurality of COFs 240 may be provided to control different gate lines and data lines respectively.

[0113] In this embodiment, the gate lines connected to each COF 240 are arranged continuously, that is, these gate lines connect multiple consecutive rows of pixel areas. For example, if the display device has a resolution of 1920×1080 and there are four COFs 240, the scan driver integrated circuit 250 of each COF 240 will be responsible for providing scan signals to 270 gate lines in a time-sharing manner.

[0114] Similarly, the data lines connected to each COF 240 are arranged continuously, that is, these data lines connect to multiple consecutive columns of pixel areas. For example, if the display device has a resolution of 1920×1080 and there are four COFs 240, the data driver integrated circuit 260 of each COF 240 will be responsible for providing data signals to 480 data lines in a time-sharing manner.

[0115] The scan driver integrated circuits 250 of two adjacent COFs 240 are electrically connected via the scan input / output signal line 310 , and the data driver integrated circuits 260 of two adjacent COFs 240 are electrically connected via the data input / output signal line 320 .

[0116] After the first chip-on-chip film completes providing scanning signals to the multiple gate lines it is responsible for in time-sharing, the first chip-on-chip film provides a scan start signal to the second chip-on-chip film, so that the second chip-on-chip film starts providing scanning signals to the multiple gate lines it is responsible for in time-sharing, thereby realizing that multiple chip-on-chip films 240 provide scanning signals to the gate lines in time-sharing.

[0117] During the period when the flip chip film provides a scanning signal to a gate line, after the first flip chip film completes providing data signals to multiple data lines for which it is responsible, the first flip chip film provides a data start signal to the second flip chip film, so that the second flip chip film starts to provide data signals to multiple data lines for which it is responsible, thereby realizing that multiple flip chip films 240 provide data signals to the data lines.

[0118] An embodiment of the present disclosure further provides a display device, comprising the display panel as described above.

[0119] The display device can be a monitor, mobile phone, tablet computer, television, wearable electronic device, navigation display device, etc.

[0120] Further, if Figure 12 As shown, the display device further includes a power management circuit 510 and a timing control circuit 520, and the power management circuit 510 is used to provide an operating voltage to the timing control circuit 520;

[0121] The timing control circuit 520 is used to provide a timing signal to the chip-on-film 240;

[0122] The power management circuit 510 is further configured to provide digital voltage signals and analog voltage signals to the COF 240 .

[0123] In this embodiment, the timing control circuit 520 can provide a timing signal to the scan driver integrated circuit 250, so that the scan driver integrated circuit 250 can have the function of providing a scan signal to multiple gate lines in a time-sharing manner using the GOA unit. The timing control circuit 520 can provide a timing signal to the data driver integrated circuit 260, so that the data driver integrated circuit 260 can provide a corresponding data signal in synchronization with the timing of the scan driver integrated circuit 250.

[0124] The power management integrated circuit (PMIC) can provide the analog voltage signals and digital voltage signals required for normal operation to the scan driver integrated circuit 250 and the data driver integrated circuit 260, so that the scan driver integrated circuit 250 can provide scan signals to multiple gate lines in time-sharing according to the timing signal, and the data driver integrated circuit 260 can synchronously provide corresponding data signals to ensure normal display of the display device.

[0125] The timing signals include but are not limited to a frame start (STV) signal provided to the scan driver integrated circuit 250 , a pixel voltage polarity reversal (POL) signal provided to the data driver integrated circuit 260 , and a data source row latch signal (TP).

[0126] The digital voltage signal includes but is not limited to a TFT-on voltage signal (VGH), a TFT-off voltage signal (VGL), and a digital power signal (DVDD) provided to the scan driver integrated circuit 250 .

[0127] The analog voltage signal includes but is not limited to an analog power supply signal (AVDD) and a half-analog voltage signal (HAVDD).

[0128] The present disclosure also provides a method for driving a display panel, the method comprising:

[0129] The scan driver integrated circuit on the at least one flip chip film sequentially provides a gate scan signal to each gate line through the first routing line, the second binding area, the first binding area and the first connecting line in a time-sharing manner, wherein, during the period of providing the gate scan signal to one gate line, the data driver integrated circuit on the at least one flip chip film sequentially provides a data signal to each data line through the second routing line, the second binding area, the first binding area and the second connecting line.

[0130] In the disclosed embodiments, a scan driver integrated circuit and a data driver integrated circuit are bonded to the same chip-on-film and to a first bonding area in the non-display area, replacing the larger GOA (Growth of Array) substrate row driver unit. This allows for a narrow-frame design of the display device without affecting normal gate line scanning. Therefore, the technical solution provided by the disclosed embodiments facilitates a narrow-frame design of the display device.

[0131] like Figure 1 As shown, the non-display area 120 is located around the display area 110 and may be arranged to surround the display area 110 .

[0132] The first direction may be a row direction of the display panel, and the second direction may be a column direction of the display panel; of course, the first direction and the second direction may also be other two directions that may intersect with each other, which is not limited here.

[0133] A thin film transistor (TFT) and a pixel electrode are provided in each pixel region. The source of the TFT is connected to the data line, the drain of the TFT is connected to the pixel electrode, and the gate of the TFT is connected to the gate line.

[0134] The non-display area 120 includes at least one first binding area 210, and all first binding areas 210 are located on the same side of the display area 110. The non-display area 120 also includes a first connection line 220 for connecting the first binding area 210 and the gate line 111, and a second connection line 230 for connecting the first binding area 210 and the data line 112. The first connection line 220 and the second connection line 230 both include portions bound within the first binding area 210. Furthermore, the first connection line 220 may also include portions connected to the gate line 111 within the display area 110.

[0135] The second binding area 241 in the Chip On Film (COF) 240 is bound and connected to the first binding area 210 in the non-display area 120 , thereby achieving transmission of electrical signals from the COF 240 to the display substrate.

[0136] A scan driver integrated circuit 250 and a data driver integrated circuit 260 are bound to the first region 242 of the COF 240. The scan driver integrated circuit 250 is used to generate a scan signal, which is transmitted via a first trace 251 to the second binding region 241, then to the first binding region 210, and then to the gate line via a first connection line 220, thereby turning on the source and drain electrodes of the TFTs in the pixel region. The data driver integrated circuit 260 is used to generate a data signal, which is transmitted via a second trace 261 to the second binding region 241, then to the first binding region 210, and then to the data line via a second connection line 230, thereby charging the pixel electrode connected to the drain electrode of the TFT via the source electrode of the TFT, causing each light-emitting device in the display region 110 to emit light, thereby realizing image display of the display device.

[0137] Among them, the first routing line 251 and the second routing line 261 are layered in the second area 243, which can reduce or even eliminate the signal crosstalk between the scanning signal on the first routing line 251 and the data signal on the second routing line 261, thereby improving the quality of signal transmission; in addition, it can also reduce the wiring space of the flip chip film, thereby reducing the size of the flip chip film.

[0138] The chip-on-film can be folded to the back of the display panel, so the chip-on-film itself does not occupy the space of the non-display area of ​​the display panel. It is only necessary to set a first binding area in the non-display area of ​​the display panel to bind and connect it to the chip-on-film. And because the scan driver integrated circuit and the data driver integrated circuit are set on a chip-on-film at the same time, the binding area can be set only on one side of the display panel, thereby reducing the area of ​​the non-display area, so that the width of the widest frame among the four side frames of the display area is less than 1.5mm, realizing an ultra-narrow frame of the display device.

[0139] Further, if Figure 11In the display panel shown, two scan driver integrated circuits on two adjacent chip-on-films are connected via scan input / output signal lines, and two data driver integrated circuits on two adjacent chip-on-films are connected via data input / output signal lines.

[0140] The step of providing gate scanning signals to each gate line in a time-sharing manner in sequence through the first wiring, the second binding area, the first binding area and the first connecting line comprises:

[0141] After the scan drive circuit in the first chip on film sequentially provides a gate scan signal to the first gate line through the first routing line, the second binding area, the first binding area, and the first connecting line in a time-sharing manner, the first chip on film sends a scan start signal to the second chip on film through the scan input and output signal line; the first chip on film and the second chip on film are two adjacent chip films, and the first gate line is a gate line electrically connected to the scan drive circuit in the first chip on film;

[0142] After the second chip-on-film receives the scan start signal, the scan drive circuit in the second chip-on-film provides a gate scan signal to the second gate line in a time-sharing manner through the first routing line, the second binding area, the first binding area and the first connecting line. The second gate line is a gate line electrically connected to the scan drive circuit in the second chip-on-film.

[0143] In this embodiment, in the case of a large-scale display device, it is difficult for one COF 240 to control all gate lines and data lines. Therefore, a plurality of COFs 240 may be provided to control different gate lines and data lines respectively.

[0144] In this embodiment, the gate lines connected to each COF 240 are arranged continuously, that is, these gate lines connect multiple consecutive rows of pixel areas. For example, if the display device has a resolution of 1920×1080 and there are four COFs 240, the scan driver integrated circuit 250 of each COF 240 will be responsible for providing scan signals to 270 gate lines in a time-sharing manner.

[0145] The scan driver integrated circuits 250 of two adjacent COFs 240 are electrically connected via the scan input / output signal line 310 .

[0146] After the first chip-on-chip film completes providing scanning signals to the multiple gate lines it is responsible for in time-sharing, the first chip-on-chip film provides a scan start signal to the second chip-on-chip film, so that the second chip-on-chip film starts providing scanning signals to the multiple gate lines it is responsible for in time-sharing, thereby realizing that multiple chip-on-chip films 240 provide scanning signals to the gate lines in time-sharing.

[0147] Further, if Figure 11As shown, the step of the data driver integrated circuit on the at least one flip chip film sequentially providing a data signal to each data line through the second wiring, the second binding area, the first binding area and the second connection line includes:

[0148] After the data driver integrated circuit on the first chip on film provides a data signal to the first data line through the second routing line, the second binding area, the first binding area, and the second connecting line, the first chip on film sends a data start signal to the second chip on film through the data input and output signal line; the first data line is a data line electrically connected to the data driver circuit in the first chip on film;

[0149] After the second chip-on-film receives the data-on signal, the data driving circuit in the second chip-on-film provides a data signal to the second data line in a time-sharing manner through the second routing line, the second binding area, the first binding area and the second connecting line. The second data line is a data line electrically connected to the data driving circuit in the second chip-on-film.

[0150] In this embodiment, the data lines connected to each COF 240 are arranged continuously, that is, these data lines connect to multiple consecutive columns of pixel areas. For example, if the display device has a resolution of 1920×1080 and there are four COFs 240, the data driver integrated circuit 260 of each COF 240 will be responsible for providing data signals to 480 data lines in a time-sharing manner.

[0151] The data driver integrated circuits 260 of two adjacent COFs 240 are electrically connected via the data input / output signal line 320 .

[0152] During the period when the flip chip film provides a scanning signal to a gate line, after the first flip chip film completes providing data signals to multiple data lines for which it is responsible, the first flip chip film provides a data start signal to the second flip chip film, so that the second flip chip film starts to provide data signals to multiple data lines for which it is responsible, thereby realizing that multiple flip chip films 240 provide data signals to the data lines.

[0153] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0154] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0155] The above is only an optional implementation of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present disclosure. These improvements and modifications should also be considered within the scope of protection of the present disclosure.

Claims

1. A display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the plurality of gate lines and the plurality of data lines intersect to define a plurality of pixel areas; The non-display area includes at least one first binding area located on one side of the display area, the non-display area also including first connecting lines correspondingly connected to a plurality of gate lines and second connecting lines correspondingly connected to a plurality of data lines, at least a portion of each of the first connecting lines and at least a portion of each of the second connecting lines being used for binding connection, and portions of the first connecting lines and the second connecting lines used for binding connection being located in the first binding area; The display panel further includes at least one chip-on-film (COF), the COF including a second binding area, the second binding area being bound and connected to the first binding area; the COF also includes a first area and a second area located between the second binding area and the first area; wherein, A scan driver integrated circuit and a data driver integrated circuit are respectively bound in the first region, the scan driver integrated circuit is connected to the second binding region via a first wiring, and the data driver integrated circuit is connected to the second binding region via a second wiring; the first wiring and the second wiring are layered in the second region; The second binding area includes a plurality of repeating units, wherein each repeating unit includes a first low-potential signal electrode, at least one first binding electrode and at least one second binding electrode; The chip-on-film further includes first low-potential signal lines connected to the first low-potential signal electrodes in a one-to-one correspondence; The first low-potential signal line is arranged in the second area on the same layer as the first routing line, and the first low-potential signal line is electrically connected to the scan driver integrated circuit; or, the first low-potential signal line is arranged in the second area on the same layer as the second routing line, and the first low-potential signal line is electrically connected to the data driver integrated circuit.

2. The display panel according to claim 1, wherein A plurality of binding electrodes are provided in the second binding area, and the binding electrodes include a first binding electrode and a second binding electrode. The first binding electrode is connected to the first trace in a one-to-one correspondence, and the second binding electrode is connected to the second trace in a one-to-one correspondence. The first binding electrode and the second binding electrode are located on the same side of the flip chip film.

3. The display panel according to claim 2, wherein: The binding electrode, the scan driver integrated circuit, and the data driver integrated circuit are located on the same side of the chip-on-film; The third trace is located on the same side of the COF as the scan driver integrated circuit and the data driver integrated circuit; the COF further includes a third region located between the first region and the second region, and a fourth region located between the second binding region and the second region, the third region having a first via hole and the fourth region having a second via hole; The fourth trace includes a first distribution segment connected to the second binding region, a second distribution segment connected to the target driver integrated circuit, and a third distribution segment connected to the second distribution segment through the first via and connected to the first distribution segment through the second via, wherein the second distribution segment and the third distribution segment are located on the same side of the chip-on-film as the third trace; The third routing is the first routing, the fourth routing is the second routing, and the target driver integrated circuit is the data driver integrated circuit; or the third routing is the second routing, the fourth routing is the first routing, and the target driver integrated circuit is the scan driver integrated circuit.

4. The display panel according to claim 2, wherein: The scan driver integrated circuit and the data driver integrated circuit are located on the same side of the chip-on-film, and the binding electrode is located on the other side of the chip-on-film; The chip-on-film further includes a third region located between the first region and the second region, and a fourth region located between the second binding region and the second region, the third region is provided with a first via hole, and the fourth region is provided with a second via hole; The third trace includes a first distribution segment connecting the first driver integrated circuit and the second via, and a second distribution segment connecting the first distribution segment and the second binding area through the second via; The fourth trace includes a third distribution segment connecting the second binding area and the first via, and a fourth distribution segment connecting the third distribution segment and the second driver integrated circuit through the first via, wherein the first distribution segment and the third distribution segment are respectively located on both sides of the chip-on-film; The third routing is the first routing, the fourth routing is the second routing, the first driver integrated circuit is the scan driver integrated circuit, and the second driver integrated circuit is the data driver integrated circuit; or, the third routing is the second routing, the fourth routing is the first routing, the first driver integrated circuit is the data driver integrated circuit, and the second driver integrated circuit is the scan driver integrated circuit.

5. The display panel according to claim 2, wherein: The binding electrode and the first driver integrated circuit are located on the same side of the chip-on-film, and the second driver integrated circuit is located on the other side of the chip-on-film; The third trace, the binding electrode, and the first driver integrated circuit are located on the same side of the COF; the COF further includes a third region located between the first region and the second region, and a fourth region located between the second binding region and the second region, wherein a third via is formed in the fourth region; The fourth trace includes a first distribution segment connecting the second driver integrated circuit and the third via, and a second distribution segment connecting the first distribution segment and the second binding area through the third via; The third routing is the first routing, the fourth routing is the second routing, the first driver integrated circuit is the scan driver integrated circuit, and the second driver integrated circuit is the data driver integrated circuit; or, the third routing is the second routing, the fourth routing is the first routing, the first driver integrated circuit is the data driver integrated circuit, and the second driver integrated circuit is the scan driver integrated circuit. The display panel according to claim 1 , wherein: Each of the repeating units includes P first binding electrodes and Q second binding electrodes, where P and Q are both positive integers.

7. The display panel according to claim 1, wherein: The first binding area includes a plurality of second low-potential signal electrodes. Z signal transmission lines are provided between two adjacent second low-potential signal electrodes. The Z signal transmission lines include first connecting lines and / or second connecting lines.

8. The display panel according to claim 7, wherein: The Z signal transmission lines include X first connection lines and Y second connection lines, where X and Y are both positive integers.

9. The display panel according to claim 1, wherein: The two scan driver integrated circuits on two adjacent chip-on-films are connected via scan input / output signal lines, and the two data driver integrated circuits on two adjacent chip-on-films are connected via data input / output signal lines.

10. A display device comprising the display panel according to any one of claims 1 to 9.

11. The display device according to claim 10, wherein: The display device further includes a power management circuit and a timing control circuit, wherein the power management circuit is used to provide an operating voltage to the timing control circuit; The timing control circuit is used to provide a timing signal to the chip-on-film; The power management circuit is further configured to provide a digital voltage signal and an analog voltage signal to the chip-on-film.

12. A method for driving a display panel according to any one of claims 1 to 9, wherein: The method comprises: The scan driver integrated circuit on the at least one flip chip film sequentially provides a gate scan signal to each gate line through the first routing line, the second binding area, the first binding area and the first connecting line in a time-sharing manner, wherein when the gate scan signal is provided to one gate line, the data driver integrated circuit on the at least one flip chip film sequentially provides a data signal to each data line through the second routing line, the second binding area, the first binding area and the second connecting line.

13. The method according to claim 12, wherein: The two scan driver integrated circuits on two adjacent chip-on-films are connected via scan input / output signal lines, and the two data driver integrated circuits on two adjacent chip-on-films are connected via data input / output signal lines. The step of providing gate scanning signals to each gate line in a time-sharing manner in sequence through the first wiring, the second binding area, the first binding area and the first connecting line comprises: After the scan drive circuit in the first chip on film sequentially provides a gate scan signal to the first gate line through the first routing line, the second binding area, the first binding area, and the first connecting line in a time-sharing manner, the first chip on film sends a scan start signal to the second chip on film through the scan input and output signal line; the first chip on film and the second chip on film are two adjacent chip films, and the first gate line is a gate line electrically connected to the scan drive circuit in the first chip on film; After the second chip-on-film receives the scan start signal, the scan drive circuit in the second chip-on-film provides a gate scan signal to the second gate line in a time-sharing manner through the first routing line, the second binding area, the first binding area and the first connecting line. The second gate line is a gate line electrically connected to the scan drive circuit in the second chip-on-film.

14. The method according to claim 12, wherein: The step of providing a data signal to each data line through the second wiring, the second binding area, the first binding area and the second connection line in sequence on the at least one chip-on-film comprises: After the data driver integrated circuit on the first chip on film provides a data signal to the first data line through the second routing line, the second binding area, the first binding area, and the second connecting line, the first chip on film sends a data start signal to the second chip on film through the data input and output signal line; the first data line is a data line electrically connected to the data driver circuit in the first chip on film; After the second chip-on-film receives the data-on signal, the data driving circuit in the second chip-on-film provides a data signal to the second data line in a time-sharing manner through the second routing line, the second binding area, the first binding area and the second connecting line. The second data line is a data line electrically connected to the data driving circuit in the second chip-on-film.

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