Ring oscillator with resonant circuit

Abstract

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4) connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) whose gate is connected to an input (in) of the amplifier circuit, whose drain is connected to an internal node (x) of the amplifier circuit, and whose source is connected to the first supply terminal (s1). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (L S ) and a first capacitor (C S ), wherein the first inductor (L S ) is connected between the internal node (x) and an output (out) of the amplifier circuit, and the first capacitor (C S ) is connected between the output (out) of the amplifier circuit and one of the first and second supply terminals (s1, s2). Furthermore, each amplifier circuit (A1-A4) comprises a second resonance circuit (R2) comprising a second inductor (L P ) and a second capacitor (C P ), wherein the second inductor (L P ) and the second capacitor (C P ) are connected in parallel between the internal node (x) and the second supply terminal (s2).

Description

Technical Field

[0001] This invention relates to an oscillator circuit. Background Technology

[0002] Voltage-controlled oscillators (VCOs) are critical components in many electronic systems, especially in wireless communication transceivers, where they are used for local oscillator generation to perform frequency up / down switching. When large interferences approach the frequency of the received signal, the mixing of phase noise is often the main noise source in the receiver. Phase noise can be reduced by increasing the supply voltage and the oscillator's signal voltage swing. Unfortunately, this option is less attractive in modern CMOS technology for reliability reasons. Therefore, low supply voltage oscillators are preferred.

[0003] Quadrature VCOs are attractive because they can be used to directly generate IQ signals, thus avoiding the use of power-consuming frequency dividers. Because the series resonant unit introduces a 90° phase shift, quadrature oscillators can be easily designed by connecting four series resonant units in a ring, such as... Figure 1 As shown. This type of circuit is disclosed in F. Pepe, A. Bevilacqua, and P. Andreani's "On the Remarkable Performance of the Series-Resonance CMOS Oscillator" (IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 2, pp. 531-542, February 2018). The use of complementary devices to increase the effective transconductance at low supply voltages results in high power efficiency. Summary of the Invention

[0004] According to a first aspect, an oscillator circuit is provided. It comprises N amplifier circuits, hereinafter numbered 1 to N. For each j ∈ {1,2,…,N-1}, the output of amplifier circuit j is connected to the input of amplifier circuit j+1. Furthermore, the output of amplifier circuit N is connected to the input of amplifier circuit 1. Additionally, the oscillator circuit has a first power supply terminal and a second power supply terminal configured to receive a power supply voltage between the first power supply terminal and the second power supply terminal. Each of the N amplifier circuits includes an input transistor, the gate of which is connected to the input of the amplifier circuit, the drain of which is connected to an internal node of the amplifier circuit, and the source of which is connected to the first power supply terminal. Furthermore, each of the N amplifier circuits includes a first resonant circuit comprising a first inductor and a first capacitor, wherein the first inductor is connected between the internal node of the amplifier circuit and the output, and the first capacitor is connected between the output of the amplifier circuit and one of the first and second power supply terminals. Furthermore, each of the N amplifier circuits includes a second resonant circuit, which includes a second inductor and a second capacitor, wherein the second inductor and the second capacitor are connected in parallel between the internal node and the second power supply terminal.

[0005] In some embodiments, N = 4.

[0006] In some embodiments where N=4, the oscillator circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is connected to the output of amplifier circuit 3, the source of the first transistor is connected to the first power supply terminal, and the drain of the first transistor is connected to the drain of the input transistor of amplifier circuit 1. The gate of the second transistor is connected to the output of amplifier circuit 4, the source of the second transistor is connected to the first power supply terminal, and the drain of the second transistor is connected to the drain of the input transistor of amplifier circuit 2. The gate of the third transistor is connected to the output of amplifier circuit 1, the source of the third transistor is connected to the first power supply terminal, and the drain of the third transistor is connected to the drain of the input transistor of amplifier circuit 3. The gate of the fourth transistor is connected to the output of amplifier circuit 2, the source of the fourth transistor is connected to the first power supply terminal, and the drain of the fourth transistor is connected to the drain of the input transistor of amplifier circuit 4.

[0007] In some embodiments where N=4, each amplifier circuit includes another transistor that connects the source of the input transistor of the same amplifier circuit to the first power supply terminal. The drain of the other transistor is connected to the source of the input transistor of the same amplifier circuit, and the source of the other transistor is connected to the first power supply terminal. The gate of the other transistor in amplifier circuit 1 is connected to the output of amplifier circuit 3. The gate of the other transistor in amplifier circuit 2 is connected to the output of amplifier circuit 4. The gate of the other transistor in amplifier circuit 3 is connected to the output of amplifier circuit 1. The gate of the other transistor in amplifier circuit 4 is connected to the output of amplifier circuit 2.

[0008] In some embodiments, each of the N amplifier circuits includes an attenuator circuit that connects the gate of the input transistor to the input of the amplifier circuit.

[0009] In some embodiments, each of the N amplifier circuits includes a common-source cascode transistor that connects the drain of the input transistor to the internal node.

[0010] The first resonant circuit can be configured to have a first resonant frequency f0, and the second resonant circuit can be configured to have a second resonant frequency f0. P ≥2f0. In some embodiments, f P It is an integer multiple of f0.

[0011] The oscillator circuit can be a controlled oscillator circuit, such as a voltage-controlled oscillator circuit or a numerically controlled oscillator circuit.

[0012] According to a second aspect, a frequency synthesizer circuit is provided, which includes the oscillator circuit described in the first aspect. The frequency synthesizer circuit may, for example, be a phase-locked loop circuit.

[0013] According to a third aspect, an integrated circuit is provided that includes the oscillator circuit described in the first aspect.

[0014] According to a fourth aspect, an electronic device is provided that includes the oscillator circuit described in the first aspect. The electronic device may be, for example, a communication device, such as a wireless communication device for a cellular communication system or a base station for a cellular communication system. Attached Figure Description

[0015] Figure 1 This is the circuit diagram of a quadrature oscillator;

[0016] Figure 2-7 A schematic circuit diagram of an embodiment of the present disclosure is shown;

[0017] Figure 8 The communication environment is shown;

[0018] Figure 9 The transceiver circuit is shown;

[0019] Figure 10 An integrated circuit is shown. Detailed Implementation

[0020] It should be emphasized that, when used in this specification, the term "including / comprises" is considered to specify the presence of the stated feature, integer, step, or component, but does not exclude the presence or addition of one or more other features, integers, steps, components, or combinations thereof.

[0021] Figure 2 This is a schematic circuit diagram of an oscillator circuit 15 according to an embodiment of the present disclosure. It includes N amplifier circuits A1-A4. In the embodiment shown in this disclosure, N = 4. However, other values ​​of N, such as integer multiples of 4, may be used in other embodiments. In the following description, the amplifier circuits are numbered 1 to N. In the drawings, amplifier circuit j (or "the j-th amplifier circuit") is provided with the reference numeral A. j The amplifier circuits are connected in a ring, where for each j∈{1,2,…,N-1}, the j-th amplifier circuit A j The output terminal 'out' is connected to the (j+1)th amplifier circuit A. j+1 The input terminal is in. The Nth amplifier circuit A N The output terminal is connected to the input terminal of the first amplifier circuit A1. Furthermore, the oscillator circuit 15 includes a first power supply terminal s1 and a second power supply terminal s2, which are configured to receive the power supply voltage between the first power supply terminal s1 and the second power supply terminal s2.

[0022] The reference numerals for the first amplifier circuit A1 are shown in the accompanying drawings. As will be readily understood by those skilled in the art, the same reference numerals apply to the other amplifier circuits A2-A4. Each of the N amplifier circuits A1-A4 includes an input transistor M1, the gate of which is connected to the input terminal in of the amplifier circuit, the drain of which is connected to an internal node (labeled x), and the source of which is connected to a first power supply terminal s1. In the drawings, the input transistor M1 is an NMOS transistor, and a second power supply terminal s2 is connected to a potential (labeled V). DDThe voltage at which the first power supply terminal s1 is connected is higher than the potential to which it is connected (or "ground", indicated by the ground symbol in the figures). However, in other embodiments, the input transistor M1 may be a PMOS transistor, in which case the first power supply terminal s1 will be connected to a high potential and the second power supply terminal s2 will be connected to a low potential. This power supply voltage is the difference between the high and low potentials. Alternatively, other types of transistors, such as bipolar transistors or other types of field-effect transistors, may also be used.

[0023] Each amplifier circuit in amplifier circuits A1-A4 includes a first resonant circuit R1, which includes a first inductor L. S and the first capacitor C S First inductor L S It is connected between the internal node x and the output terminal out of the amplifier circuit. The first capacitor C... S It is connected between the output terminal out of the amplifier circuit and one of the first power supply terminal and the second power supply terminals s1 and s2. In the figure, the first capacitor CS is connected to the first power supply terminal s1, but in other embodiments, it may alternatively be connected to the second power supply terminal s2.

[0024] Furthermore, each amplifier circuit in amplifier circuits A1-A4 includes a second resonant circuit R2, which includes a second inductor L. P Second capacitor C P Second inductor L P Second capacitor C P It is connected in parallel between the internal node x and the second power supply terminal s2.

[0025] When in Figure 1 When using a CMOS inverter in an oscillator, a relatively high power supply voltage is required to start the oscillator. Figure 1 Compared to the oscillator in the present disclosure, the required supply voltage can be reduced by including a second resonant circuit R2 instead of a transistor in the embodiments of this disclosure. Simulations show that in some applications, a supply voltage only slightly higher than the threshold voltage of the input transistor M1 is sufficient. Furthermore, because the CMOS inverter has both a PMOS transistor and an NMOS transistor driven by its input, a relatively high parasitic capacitance is obtained. With the amplifier circuit used in the embodiments of this disclosure, complementary transistors (i.e., both NMOS and PMOS) are not required, thereby... Figure 1 Compared to oscillators in other circuits, parasitic capacitance can be reduced. If an NMOS transistor is used as the input transistor M1, the parasitic effect is lower compared to using a PMOS transistor, and NMOS transistors are generally faster than PMOS transistors; therefore, using an NMOS transistor as the input transistor M1 is advantageous for achieving a high oscillation frequency. Furthermore, compared to… Figure 1 Compared to the oscillator in the previous embodiment, the inclusion of a second resonant circuit R2 instead of a transistor in the embodiments of this disclosure provides more degrees of freedom to control the impedance of harmonics and to shape the drain waveform to achieve high efficiency and low phase noise.

[0026] Figure 3 This is a schematic circuit diagram of another embodiment of the oscillator circuit 15. Besides... Figure 2 In addition to the circuit shown, it includes transistor M P1 M P2 M P3 and M P4 .exist Figure 3 In the middle, transistor M P1 M P2 M P3 and M P4 It is an NMOS transistor. In the embodiment where the input transistor M1 in each amplifier circuit A1-A4 is a PMOS transistor, transistor M... P1 M P2 M P3 and M P4 It can be implemented as a PMOS transistor.

[0027] Transistor M P1 The gate of the transistor is connected to the output terminal out of the third amplifier circuit A3, its source is connected to the first power supply terminal s1, and its drain is connected to the drain of the input transistor M1 of the first amplifier circuit A1.

[0028] Transistor M P2 The gate of the transistor is connected to the output terminal out of the fourth amplifier circuit A4, its source is connected to the first power supply terminal s1, and its drain is connected to the drain of the input transistor M1 of the second amplifier circuit A2.

[0029] Transistor M P3 The gate of the transistor is connected to the output terminal out of the first amplifier circuit A1, its source is connected to the first power supply terminal s1, and its drain is connected to the drain of the input transistor M1 of the third amplifier circuit A3.

[0030] Transistor M P4 The gate of the transistor is connected to the output terminal out of the second amplifier circuit A2, its source is connected to the first power supply terminal s1, and its drain is connected to the drain of the input transistor M1 of the fourth amplifier circuit A4.

[0031] Figure 3 Additional transistor M in P1 M P2 M P3 and M P4It provides suppression of non-orthogonal oscillation modes, thus providing a more robust quadrature oscillator. Theoretically, a quadruple oscillator can generate two or four phases. Figure 3 In the middle, additional transistors M are used in parallel. P1 M P2 M P3 and M P4 This is to inject signals to ensure orthogonal phase relationships and prevent other oscillation modes, such as having only two phases instead of four in the oscillator. Figure 4 In this method, a series device is used to inject the signal, which results in a high quality factor while reducing power consumption. The goal is the same as that of a forced oscillator producing four phases spaced 90 degrees apart.

[0032] Figure 4 This is a schematic circuit diagram of another embodiment of the oscillator circuit 15. Besides... Figure 2 In addition to the circuits shown, each amplifier circuit A1-A4 includes another transistor M2, which connects the source of the input transistor M1 of the same amplifier circuit A1-A4 to the first power supply terminal s1. The drain of the other transistor M2 is connected to the source of the input transistor M1 of the same amplifier circuit A1-A4. The source of the other transistor M2 is connected to the first power supply terminal s1. The gate of the other transistor M2 of the first amplifier circuit A1 is connected to the output of the third amplifier circuit A3. The gate of the other transistor M2 of the second amplifier circuit A2 is connected to the output of the fourth amplifier circuit A4. The gate of the other transistor M2 of the third amplifier circuit A3 is connected to the output of the first amplifier circuit A1. The gate of the other transistor M2 of the fourth amplifier circuit A4 is connected to the output of the second amplifier circuit A2. Figure 4 In each amplifier circuit A1-A4, another transistor M2 provides suppression of non-quadrature oscillation modes. This function is similar to that described above. Figure 3 The functionality described in the context, but in Figure 4 Instead, another transistor M2 connected in series is used to inject the signal.

[0033] Figure 5 This demonstrates how inductors can be implemented in pairs. Figure 2 The transformer shown in the embodiment saves chip area. For simplicity, in Figure 5 Capacitors are not shown. Firstly, because the signal currents in each pair of inductors, placed together as transformers, are 180° out of phase, the mutual inductance between the inductors in the pair increases the effective inductance of each inductor in the pair. This allows for a reduction in the physical size of the inductors. Furthermore, the inductors can be implemented through an interleaved layout on the chip surface, which further contributes to space savings.

[0034] Figure 6 This is a schematic circuit diagram of another embodiment of the oscillator circuit 15. Figure 6 In the amplifier circuits A1-A4, each amplifier circuit includes an attenuator circuit ATT. in It connects the gate of the input transistor M1 to the input terminal in of the amplifier circuit. Figure 6 Only amplifier circuit A1 is shown in the diagram. The other amplifier circuits A2-A4 are implemented in the same manner. Attenuator circuit ATT in It can be implemented, for example, as a capacitive voltage divider. Attenuator circuit ATT in The supply voltage can be increased without damaging the input transistor M1. By increasing the supply voltage, improved (reduced) phase noise can be obtained.

[0035] Figure 7 This is a schematic circuit diagram of another embodiment of the oscillator circuit 15. Figure 6 In the amplifier circuits A1-A4, each amplifier circuit includes a cascode transistor M. casc It connects the drain of input transistor M1 to internal node x. The cascode transistor M... casc Same type as input transistor M1. Common-source cascode transistor M casc The source of the transistor is connected to the drain of the input transistor M1. The cascode transistor M1... casc The drain of the transistor is connected to the internal node x. The cascode transistor M... casc The gate is biased by a voltage V casc .exist Figure 7 Only amplifier circuit A1 is shown in the diagram. The other amplifier circuits A2-A4 are implemented in the same manner. This includes a common-source cascode transistor M. casc The voltage swing that the oscillator circuit 15 can handle has been increased.

[0036] In some embodiments of the oscillator circuit 15, the first resonant circuit R1 is tuned or otherwise configured to have a first resonant frequency f0. The first resonant frequency f0 is typically equal to or relatively close to the oscillation frequency of the oscillator 15.

[0037] In some embodiments of the oscillator circuit 15, the second resonant circuit R2 is also tuned or otherwise configured to have the same resonant frequency f0. This helps to keep the amount of fundamental current drawn by the second resonant circuit R2 relatively low. However, the inventors have realized that higher DC-to-RF conversion efficiency and oscillator phase noise quality factor (FoM) can be obtained through more appropriate harmonic termination. This is achieved through relatively low drain voltage and current waveform overlap, similar to a Class E power amplifier.

[0038] The frequency f has been used and is tuned to the resonant frequency. P The second resonant circuit R2 is used to simulate Figure 3 The embodiment of oscillator circuit 15 is shown. In the first simulation, f P =f0. It has been observed that the resulting drain current is rich in harmonics due to the Class C bias mechanism, but more importantly, a considerable current is conducted when the drain voltage level is high. This leads to relatively poor DC-RF conversion efficiency. Furthermore, conduction at zero crossings is a major source of unwanted phase noise.

[0039] In the subsequent simulation, f P =nf0, where n = 2, 3, 4, 5, 6. That is, the second resonant circuit R2 is tuned to one of the harmonics of f0. This leads to Class E-like operation. Under this mechanism, efficiency is improved (compared to f0) due to reduced current conduction at voltage zero crossings. P =f0) and the phase noise is improved. For example, simulations show that when the tank is tuned to the second harmonic (i.e., n=2), compared to f P Compared to f0, the phase noise is shifted by 100MHz from the 3GHz carrier, and the FoM is improved by more than 7dB. Similar results were obtained for values ​​of n≥3. Of course, the quantitative results depend on the specific component model and frequency used in the simulation. However, qualitatively, the results are also applicable to other component models and frequencies. The transistor model used in the simulation is from a low-power 22nm CMOS process, and the inductor used in the simulation has a Q value of approximately 10 at 3GHz. The component parameters used in the simulation are shown in the table below:

[0040] parameter value <![CDATA[W / L (width / length) of M1]]> 200μm / 18nm <![CDATA[W / L of M2]]> 100μm / 18nm <![CDATA[L S ]]> 1nH <![CDATA[C S ]]> 2pF <![CDATA[L P ]]> Scan from 1 nH to 166 pH <![CDATA[C P ]]> Scanning from 2pF to 333fF <![CDATA[V DD ]]> 200mV

[0041] According to some embodiments, and in view of the above, the second resonant circuit R2 is configured to have a second resonant frequency f. P ≥2f0. Specifically, in some embodiments, f P It is an integer multiple of f0.

[0042] According to some embodiments, oscillator circuit 15 is a voltage-controlled oscillator (VCO) circuit. For example, each amplifier circuit A1-A4 may include a capacitor C. S A first voltage-controlled capacitor (not shown), such as a varactor, is connected in parallel and is used to control the oscillation frequency by controlling the resonant frequency of the resonant circuit R1. The first voltage-controlled capacitor can be controlled via a control voltage. Each amplifier circuit A1-A4 may also include a capacitor C... PA second voltage-controlled capacitor (not shown), such as a variable capacitor, is connected in parallel and used to tune the resonant frequency of the resonant circuit R2. The second voltage-controlled capacitor can be controlled via a control voltage (e.g., the same control voltage used to control the first voltage-controlled capacitor).

[0043] According to some embodiments, oscillator circuit 15 is a digitally controlled oscillator (VCO) circuit. For example, each amplifier circuit A1-A4 may include a capacitor C. S The first numerically controlled capacitor connected in parallel is used to control the oscillation frequency by controlling the resonant frequency of the resonant circuit R1. Each amplifier circuit A1-A4 may also include a capacitor C. P A second digitally controlled capacitor (not shown) connected in parallel is used to tune the resonant frequency of the resonant circuit R2.

[0044] Figure 8 The diagram illustrates a communication environment in which embodiments of the invention can be employed. A wireless communication device 1 (or simply wireless device 1) of a cellular communication system communicates wirelessly with a radio base station 2 of the cellular communication system. Wireless device 1 is typically a user equipment (UE). Wireless device 1 in... Figure 8 The device shown is a mobile phone, but can be any type of device with cellular communication capabilities, such as a tablet or laptop computer, a machine-type communication (MTC) device, etc. Furthermore, a cellular communication system is used as an example in this disclosure. However, embodiments of this disclosure can also be applied to other types of systems, such as, but not limited to, WiFi systems.

[0045] Radio base station 2 and wireless device 1 are examples of communication devices in this disclosure. Embodiments are described below in the context of communication devices in the form of radio base station 2 or wireless device 1. However, other types of communication devices, such as WiFi access points or WiFi-enabled devices, are also contemplated.

[0046] Figure 9 This is a block diagram of an embodiment of transceiver circuit 10, which can be included in a communication device, such as a radio base station 2 or a wireless device 1. Figure 9 In the illustrated embodiment, the transceiver circuit 10 includes an oscillator circuit 15. For example... Figure 9 As shown, the oscillator circuit 15 can be included in the frequency synthesizer, for example, in the phase-locked loop (PLL) 17.

[0047] In addition, Figure 9In the illustrated embodiment, the transceiver circuit 10 includes a transmitter circuit 20 and a receiver circuit 30, which can utilize an oscillation signal generated by the oscillator circuit 15 as a local oscillator signal. For example, the local oscillator signal can be used to drive one or more mixer circuits in the transmitter circuit 20 and / or the receiver circuit 30. Figure 9 In this diagram, transmitter circuit 20 and receiver circuit 30 are shown connected to the same antenna 35. However, this is merely an example. In some embodiments, separate transmit and receive antennas may be used.

[0048] An embodiment of oscillator circuit 15 is suitable for integration onto an integrated circuit. This is in Figure 10 The figure schematically illustrates an integrated circuit 100 including an oscillator circuit 15.

[0049] The above disclosure relates to specific embodiments. However, other embodiments besides those described above are possible within the scope of this invention. For example, the oscillator circuit 15 can be used in electronic devices other than communication devices. Different features and steps of the embodiments can be combined in combinations different from those described.

Claims

1. An oscillator circuit (15), comprising: There are N amplifier circuits (A1-A4), numbered 1 to N below, where for each j∈{1,2,…,N-1}, amplifier circuit j(A1-A4) j The output terminal (out) of the amplifier circuit is connected to amplifier circuit j+1 (A). j+1 The input terminal (in) of the amplifier circuit N(A) N The output terminal of ) is connected to the input terminal of amplifier circuit 1 (A1); A first power supply terminal and a second power supply terminal (s1, s2) are configured to receive a power supply voltage between the first power supply terminal and the second power supply terminal (s1, s2); and Each of the N amplifier circuits (A1-A4) includes: An input transistor (M1) is provided, the gate of which is connected to the input terminal (in) of the amplifier circuit, the drain of which is connected to the internal node (x) of the amplifier circuit, and the source of which is connected to the first power supply terminal (s1). The first resonant circuit (R1) includes a first inductor (L). S ) and the first capacitor (C S ), wherein the first inductor (L S The first capacitor (C) is connected between the internal node (x) and the output terminal (out) of the amplifier circuit. S The amplifier circuit output (out) is connected between the output terminal (out) and one of the first power supply terminal and the second power supply terminal (s1, s2); and The second resonant circuit (R2) includes a second inductor (L). P ) and second capacitor (C P ), wherein the second inductor (L P ) and the second capacitor (C) P The internal node (x) is connected in parallel between the internal node (x) and the second power supply terminal (s2). The first resonant circuit (R1) is configured to have a first resonant frequency f0, and the second resonant circuit (R2) is configured to have a second resonant frequency f0. P ≥2f0.

2. The oscillator circuit (15) according to claim 1, wherein, N＝4。 3. The oscillator circuit (15) according to claim 2, comprising: First transistor (M) P1 ), the first transistor (M) P1 The gate of the first transistor (M) is connected to the output (out) of amplifier circuit 3 (A3). P1 The source of the transistor (M) is connected to the first power supply terminal (s1), and the first transistor (M) P1 The drain of the transistor is connected to the drain of the input transistor (M1) of the amplifier circuit 1 (A1); Second transistor (M) P2 ), the second transistor (M) P2 The gate of the second transistor (M) is connected to the output (out) of amplifier circuit 4 (A4). P2 The source of the second transistor (M) is connected to the first power supply terminal (S1), and the source of the second transistor (M) is connected to the first power supply terminal (S1). P2 The drain of the input transistor (M1) is connected to the drain of the amplifier circuit 2 (A2); Third transistor (M) P3 The third transistor (M) P3 The gate of the third transistor (M) is connected to the output (out) of amplifier circuit 1 (A1). P3 The source of the third transistor (M) is connected to the first power supply terminal (S1), and the source of the third transistor (M) is connected to the first power supply terminal (S1). P3 The drain of the transistor is connected to the drain of the input transistor (M1) of the amplifier circuit 3 (A3); as well as Fourth transistor (M) P4 The fourth transistor (M) P4 The gate of the fourth transistor (M) is connected to the output (out) of amplifier circuit 2 (A2). P4 The source of the fourth transistor (M) is connected to the first power supply terminal (S1), and the source of the fourth transistor (M) is connected to the first power supply terminal (S1). P4 The drain of the transistor is connected to the drain of the input transistor (M1) of the amplifier circuit 4 (A4).

4. The oscillator circuit (15) according to claim 2, wherein, Each amplifier circuit (A1-A4) includes another transistor (M2) that connects the source of the input transistor (M1) of the same amplifier circuit (A1-A4) to the first power supply terminal (s1), wherein the drain of the other transistor (M2) is connected to the source of the input transistor (M1) of the same amplifier circuit (A1-A4), and the source of the other transistor (M2) is connected to the first power supply terminal (s1), and wherein, The gate of the other transistor (M2) of amplifier circuit 1 (A1) is connected to the output terminal of amplifier circuit 3 (A3); The gate of the other transistor (M2) of amplifier circuit 2 (A2) is connected to the output terminal of amplifier circuit 4 (A4); The gate of the other transistor (M2) in amplifier circuit 3 (A3) is connected to the output terminal of amplifier circuit 1 (A1); and The gate of the other transistor (M2) of amplifier circuit 4 (A4) is connected to the output of amplifier circuit 2 (A2).

5. The oscillator circuit (15) according to claim 1, wherein, Each of the N amplifier circuits (A1-A4) includes an attenuator circuit (ATT). in ), which connects the gate of the input transistor (M1) to the amplifier circuit (A) j The input terminal (in) of ).

6. The oscillator circuit (15) according to claim 1, wherein, Each of the N amplifier circuits (A1-A4) includes a common-source cascode transistor (M). casc ), which connects the drain of the input transistor (M1) to the internal node (x).

7. The oscillator circuit (15) according to claim 1, wherein, f P It is an integer multiple of f0.

8. The oscillator circuit (15) according to claim 1, wherein, The oscillator circuit (15) is a voltage-controlled oscillator circuit.

9. The oscillator circuit (15) according to claim 1, wherein, The oscillator circuit (15) is a numerically controlled oscillator circuit.

10. A frequency synthesizer circuit (17) comprising the oscillator circuit (15) of any one of claims 1-9.

11. The frequency synthesizer circuit (17) according to claim 10, wherein, The frequency synthesizer circuit (17) is a phase-locked loop circuit.

12. An integrated circuit (100) comprising an oscillator circuit (15) according to any one of claims 1-9.

13. An electronic device (1, 2) comprising an oscillator circuit (15) according to any one of claims 1-9.

14. The electronic device (1, 2) according to claim 13, wherein, The electronic devices (1, 2) are communication devices.

15. The electronic device (1) according to claim 14, wherein, The communication device is a wireless communication device used in cellular communication systems.

16. The electronic device (2) according to claim 14, wherein, The communication device is a base station used in a cellular communication system.

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