Standard cell creation method
By setting implant separation cases and applying characteristic parameters, and optimizing channel parameters, the difficult problem of device performance evaluation in circuit simulation is solved, and accurate evaluation of device spacing and parasitic elements is achieved, thereby improving circuit performance and design accuracy.
Patent Information
- Application Number
- CN202110906983.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-08-11
- Filing Date
- 2021-08-09
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2041-08-09
AI Technical Summary
During circuit simulation, existing technologies have difficulty effectively evaluating device performance to optimize circuit performance, especially the evaluation of device spacing and parasitic elements, resulting in inaccurate designs.
By setting up implant separation cases, collecting characteristic parameters, applying them to the device delay comparison mode, optimizing channel parameters, establishing standard cells, using CV/I metric and TCAD separation methods, optimizing the metal oxide semiconductor field effect transistor (MOSFET) database, and evaluating device performance.
It enables accurate evaluation of device performance, optimizes circuit performance, and improves design accuracy and generational evolution efficiency.
Smart Images
Figure CN114077813B_ABST
Abstract
Description
Technical Field
[0001] The embodiments described in this disclosure relate to a standard cell establishment method, and more particularly to a standard cell establishment method for optimizing circuit performance. Background Art
[0002] Currently, circuit simulations require checking device performance based on current fabrication technology for speed (propagation delay) considerations. With each new fabrication generation, finding the optimal device for design and application requires a thorough evaluation of device performance, including device pitch (width / length / space) and all parasitic components (capacitors / diodes / resistors). Summary of the Invention
[0003] Some embodiments disclosed herein relate to a method for establishing a standard cell, comprising the following steps: setting a first implant separation case; obtaining a plurality of characteristic parameters based on the first implant separation case; applying the characteristic parameters to a device delay comparison mode to obtain a speed parameter; optimizing a channel parameter if the speed parameter is better than a previous speed parameter; and establishing a standard cell if the channel parameter optimization is successful.
[0004] In some embodiments, the method further comprises: setting a second implant separation case if the speed parameter is not better than the previous speed parameter; obtaining the characteristic parameters according to the second implant separation case; and applying the characteristic parameters to the device delay comparison mode to obtain the speed parameter.
[0005] In some embodiments, the method further includes: collecting at least one unit of data after setting the first implant separation case.
[0006] In some embodiments, obtaining the characteristic parameters according to the first implant separation case further includes: operating in a DC mode to obtain a saturation current value.
[0007] In some embodiments, obtaining the characteristic parameters according to the first implant separation case further includes: operating in an AC mode to obtain a parasitic capacitance value.
[0008] In some embodiments, the characteristic parameters include a saturation current value and a parasitic capacitance value.
[0009] In some embodiments, the speed parameter is obtained from a CV / I metric.
[0010] In some embodiments, the channel parameter includes a depletion region width ratio.
[0011] In some embodiments, the first implant separation profile comprises at least one of a well separation parameter, an S / D separation parameter, an LDD separation parameter, and a pocket separation parameter.
[0012] In some embodiments, the method further includes: if the channel parameter is not optimized successfully, setting a second implant separation case; obtaining the characteristic parameters according to the second implant separation case; and applying the characteristic parameters to the device delay comparison mode to obtain the speed parameter.
[0013] In summary, embodiments of the present invention provide a method for establishing standard cells to effectively evaluate device performance, including device spacing (width / length / pitch) and all parasitic components (capacitors / diodes / resistors). These embodiments encompass diverse technology applications and employ CV / I for generational evolution. Whether based on silicon isolation or computer-aided design (TCAD) isolation, they provide a simple method for establishing a metal oxide semiconductor field effect transistor (MOSFET) database and optimizing circuit performance through propagation delay. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent, the accompanying drawings are described as follows:
[0015] Figure 1 The flowchart of a method for establishing a standard cell according to some embodiments of the present invention is shown. DETAILED DESCRIPTION
[0016] As used herein, the term “coupled” may also refer to “electrically coupled,” and the term “connected” may also refer to “electrically connected.” “Coupled” and “connected” may also refer to two or more elements cooperating or interacting with each other.
[0017] See also Figure 1 . Figure 1 FIG. 1 is a flow chart illustrating a method 100 for creating a standard cell according to some embodiments of the present invention, but the implementation of the present invention is not limited thereto.
[0018] It should be noted that the above-mentioned standard cell establishment method 100 is applicable to a system or device having a processor and a memory structure.
[0019] It should be noted that in some embodiments, this method may also be implemented as a computer program and stored in a non-transitory computer-readable recording medium, so that a computer or electronic device reads this recording medium and executes the display method. The non-transitory computer-readable recording medium may be a read-only memory, a flash memory, a floppy disk, a hard disk, an optical disk, a pen drive, a magnetic tape, a database accessible via a network, or any other non-transitory computer-readable recording medium having the same functionality that can be readily conceived by those skilled in the art.
[0020] In addition, it should be understood that the operations of the method mentioned in this embodiment, except for those specifically described in terms of order, can be adjusted in order according to actual needs, and can even be executed simultaneously or partially simultaneously.
[0021] Furthermore, in different embodiments, these operations may be adaptively added, replaced, and / or omitted.
[0022] See also Figure 1 The standard cell creation method 100 includes the following operations.
[0023] In step S110 , an implant separation profile of the semiconductor unit is set. In some embodiments, the implant separation profile includes a well separation parameter, an S / D separation parameter, an LDD separation parameter, and / or a pocket separation parameter.
[0024] In step S120 , at least one unit of data is collected. In some embodiments, the at least one unit of data includes a channel length of a semiconductor unit, and short channel effects are evaluated by on / off comparison.
[0025] In step S130, multiple characteristic parameters are obtained based on the implant separation case. In some embodiments, the implant separation case includes a saturation current value and a parasitic capacitance value. In some embodiments, the saturation current value is obtained by operating the semiconductor unit in a direct current (DC) mode. In some embodiments, the parasitic capacitance value is obtained by operating the semiconductor unit in an alternating current (AC) mode.
[0026] In some embodiments, parasitic capacitance is sensitive to implant separation parameters. In some embodiments, CV / I is calculated to optimize saturation current and parasitic capacitance.
[0027] In step S140 , the characteristic parameters are applied to a device delay comparison model to obtain speed parameters. In some embodiments, the device delay comparison model includes a CV / I method. C is the parasitic capacitance value, I is the saturation current value, and V is the voltage value. In some embodiments, in step S140 , the device modeling is performed using the parasitic capacitance value and the saturation current value.
[0028] In step S150, it is determined whether the speed parameter is better than the previous speed parameter. In some embodiments, the previous speed parameter is the speed parameter before the implant separation case is set in step S110. In some embodiments, the previous speed parameter is the speed parameter of the semiconductor unit established in the previous version.
[0029] If the speed parameter obtained in step S140 is better than the previous speed parameter, step S160 is executed. On the other hand, if the speed parameter obtained in step S140 is not better than the previous speed parameter, step S110 is executed. If the speed parameter obtained in step S140 is not better than the previous speed parameter, another implant separation case of the semiconductor unit is set, data of at least one other unit is collected, and characteristic parameters are obtained based on the new implant separation case.
[0030] In step S160, channel parameters are optimized and a determination is made as to whether the optimization is successful. In some embodiments, the channel parameter is WN / WP. WN is the width of the depletion region within the P-doped region, and WP is the width of the depletion region within the N-doped region. In step S160, the optimal WP / WN ratio is determined.
[0031] If the channel parameters are successfully optimized, step S170 is executed. On the other hand, if the channel parameters are not successfully optimized, step S110 is executed. If the channel parameters are not successfully optimized, another implant separation case of the semiconductor unit is set, data of at least one additional unit is collected, and characteristic parameters are obtained based on the new implant separation case.
[0032] In step S170 , a standard cell is created. In some embodiments, the standard cell is a semiconductor cell such as an inverter, a NAND logic gate, or a Nor logic gate.
[0033] In some embodiments, the semiconductor unit is a MOSFET semiconductor unit, which includes multiple parasitic capacitors. When the well separation and / or S / D separation dose is shallow or heavy, the parasitic capacitance of some portions increases. On the other hand, when the LDD separation and / or pocket separation dose is shallow or heavy, the parasitic capacitance of other portions increases. In embodiments of the present invention, the performance of the semiconductor unit is optimized, and the effects of parasitic capacitance and saturation current are also considered.
[0034] In some embodiments, during the development of different versions, semiconductor unit data may be different, for example, the channel length may be shorter. Through the embodiments of the present invention, parasitic capacitance values and saturation current values may be optimized.
[0035] In summary, the embodiments of this case provide a method for establishing a standard cell, thereby effectively evaluating device performance, including device pitch (width / length / space) and all parasitic elements (capacitors / diodes / resistors), to find the best-performing device for design and application. The implementation of this case includes different technology applications and applies CV / I for generational evolution. Whether based on silicon separation or computer-aided design (TCAD) separation, this case provides a simple method to establish a metal oxide semiconductor field effect transistor (MOSFET) database and optimize circuit performance through propagation delay.
[0036] Furthermore, the above examples include sequential exemplary steps, but these steps do not necessarily need to be performed in the order shown. Performing these steps in a different order is contemplated within the scope of this disclosure. Steps may be added, substituted, reordered, and / or omitted as appropriate within the spirit and scope of the embodiments of this disclosure.
[0037] Although the present disclosure has been disclosed above in the form of implementation methods, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the claims.
[0038]
Explanation of symbols
[0039] 100: Standard cell establishment method
[0040] S110, S120, S130, S140: Steps
[0041] S150, S160, S170: steps.
Claims
1. A method for establishing a standard cell, wherein the standard cell is a semiconductor cell, characterized in that: Include: Set the first implant separation case; obtaining a plurality of first characteristic parameters according to the first implant separation case; Applying the first characteristic parameters to a device delay comparison mode to obtain a first speed parameter; If the first speed parameter is better than a previous speed parameter of a previously established standard unit, optimizing the first channel parameter; as well as If the first channel parameter optimization is successful, a standard unit is established; If the first speed parameter is not better than the previous speed parameter, setting a second implant separation case; obtaining a plurality of second characteristic parameters according to the second implant separation case; Applying the second characteristic parameters to the device delay comparison mode to obtain a second speed parameter; If the second speed parameter is better than a previous speed parameter of a previously established standard cell, optimizing a second channel parameter; and If the second channel parameter optimization is successful, the standard cell is established.
2. The method for establishing a standard cell according to claim 1, wherein: Also includes: After setting the first implant separation case, at least one unit of data is collected.
3. The method for establishing a standard cell according to claim 1, wherein: Wherein obtaining the first characteristic parameters according to the first implant separation case further comprises: Operate in DC mode to achieve saturation current value.
4. The method for establishing a standard cell according to claim 1, wherein: Wherein obtaining the first characteristic parameters according to the first implant separation case further comprises: Operate in AC mode to obtain the parasitic capacitance value.
5. The method for establishing a standard cell according to claim 1, wherein: The first characteristic parameters include a saturation current value and a parasitic capacitance value.
6. The method for establishing a standard cell according to claim 1, wherein: The first speed parameter is obtained by CV / I measurement.
7. The method for establishing a standard cell according to claim 1, wherein: The first channel parameter includes a depletion region width ratio.
8. The method for establishing a standard cell according to claim 1, wherein: The first implant separation case includes at least one of a well separation parameter, an S / D separation parameter, an LDD separation parameter, and a pocket separation parameter.