Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device that can suppress an increase in chip size even when multifunctionalized. The semiconductor memory device according to the embodiment includes: a memory cell section including a memory cell array composed of a plurality of memory cells; a peripheral circuit that performs voltage transfer control including write operations, read operations, and erase operations on the memory cell section; and signal lines that connect the peripheral circuit and the memory cell section, and at least a part thereof passes through a non-facing region in a peripheral region of the memory cell section excluding the memory cell array where the memory cell section and the peripheral circuit do not face each other.

Description

[0001] [Related Application(s)]

[0002] This application claims priority to Japanese Patent Application No. 2020-137608, filed on Aug. 17, 2020. This application incorporates by reference the entire contents of the priority application. Technical Field

[0003] The present invention relates to a semiconductor memory device. Background Art

[0004] In a semiconductor memory device, a memory cell array composed of a plurality of memory cells and peripheral elements for controlling the memory cell array are arranged at a specified distance from each other. In the region between the memory cell array and the peripheral elements, a row decoder or a page buffer including a plurality of block decoders is arranged, and word lines connected to the row decoder pass through, and bit lines connected to the page buffer pass through.

[0005] If the semiconductor memory device is made multifunctional and the number of row decoders or page buffers increases, the number of word lines or bit lines also increases, and the chip size will become larger. Summary of the Invention

[0006] Embodiments provide a semiconductor memory device that can suppress an increase in chip size even when made multifunctional.

[0007] The semiconductor memory device according to an embodiment includes: a memory cell section including a plurality of memory cell arrays; a peripheral circuit that performs voltage transfer control including write operations, read operations, and erase operations on the memory cell section; and signal lines connected to the peripheral circuit and the memory cell section, at least a part of which is formed in a non-facing region, which is a region in a peripheral region formed around the memory cell arrays in the memory cell section where the memory cell section and the peripheral circuit do not face each other.

[0008] According to an embodiment, a semiconductor memory device that can suppress an increase in chip size even when made multifunctional can be provided. Brief Description of the Drawings

[0009] Figure 1 is a block diagram of a NAND (Not AND) type flash memory according to an embodiment.

[0010] Figure 2 is for Figure 1 explaining the configuration of a memory plane included in the memory cell array shown.

[0011] Figure 3 is for Figure 2 explaining one memory plane of the memory cell array shown.

[0012] Figure 4 is used to illustrate Figure 3 the wiring area shown in the figure.

[0013] Figure 5 is used to illustrate Figure 3 the wiring area shown in the figure.

[0014] Figure 6 is a diagram for illustrating an example of setting a logic circuit in a wiring area.

[0015] Figure 7 is a diagram for illustrating an example of a multiplexed wiring area.

[0016] Figure 8 is used to illustrate Figure 7 an example of setting a logic circuit in the wiring area shown in the figure.

[0017] Figure 9 is a diagram for illustrating an example of wiring overlapping with a row decoder. Detailed implementation mode

[0018] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The following several embodiments are examples for embodying the technical idea of the present invention in devices and methods. The technical idea of the present invention is not determined by the shape, structure, and configuration of the constituent parts. Each functional block can be implemented as either hardware or software or a combination of both. It is not necessary to distinguish each functional block as in the following examples. For example, part of the functions can be executed by functional blocks different from the illustrated functional blocks. Furthermore, the illustrated functional blocks can be divided into more detailed functional sub-blocks. In addition, in the following description, elements having the same functions and configurations are denoted by the same reference numerals, and repeated descriptions are made only when necessary.

[0019] Refer to Figure 1 to describe the NAND flash memory as a semiconductor storage device of the present embodiment. Figure 1 is a block diagram of the NAND flash memory 2 of the embodiment.

[0020] The NAND flash memory 2 includes a storage cell section 3, an input / output circuit 21, a logic control circuit 22, a status register 23A, an address register 23B, an instruction register 23C, a sequencer 24, a voltage generation circuit 25, a row decoder 5, a column decoder 27, a sense amplifier module 28, and a data register 29.

[0021] The storage cell section 3 includes a plurality of memory planes. Figure 1Among them, as an example, four memory planes 30, 31, 32, and 33 are shown. Each of the multiple memory planes includes multiple memory cell transistors. In order to apply voltage to the memory cell transistors, multiple bit lines, multiple word lines, source lines, etc. are arranged in the memory cell section 3. The specific configuration of the memory plane will be described below.

[0022] The input / output circuit 21 and the logic control circuit 22 are connected to a memory controller (not shown) via a NAND bus (not shown). The input / output circuit 21 transmits and receives signals DQ (e.g., DQ0 to DQ7) via the NAND bus between the memory controllers.

[0023] The logic control circuit 22 receives external control signals (e.g., chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, and write protection signal WPn) from the memory controller 3 via the NAND bus. The "n" appended to the signal name indicates active low. In addition, the logic control circuit 22 sends a ready / busy signal RBn to the memory controller 3 via the NAND bus.

[0024] The signal CEn realizes the selection of the NAND flash memory 2 and takes effect when the NAND flash memory 2 is selected. The signal CLE realizes latching the instruction sent as the signal DQ in the instruction register. The signal ALE realizes latching the address sent as the signal DQ in the address register. The signal WEn realizes writing. The signal REn realizes reading. The signal WPn takes effect when writing and erasing are prohibited. The signal RBn indicates whether the NAND flash memory 2 is in a ready state (a state where it can accept commands from the outside) or a busy state (a state where it cannot accept commands from the outside). The memory controller 3 can know the state of the NAND flash memory 2 by receiving the signal RBn from the NAND flash memory 2.

[0025] The status register 23A temporarily stores the data required for the operation of the NAND flash memory 2. The address register 23B temporarily stores the address. The instruction register 23C temporarily stores the instruction. The status register 23A, the address register 23B, and the instruction register 23C include, for example, SRAM (Static Random Access Memory).

[0026] The sequencer 24 receives an instruction from the instruction register 23C and comprehensively controls the NAND flash memory 2 according to the sequence based on the instruction.

[0027] The voltage generation circuit 25 receives a power supply voltage from the outside of the NAND flash memory 2, and generates a plurality of voltages required for write operations, read operations, and erase operations using this power supply voltage. The voltage generation circuit 25 supplies the generated voltages to the memory cell section 3, the row decoder 5, the sense amplifier assembly 28, and the like.

[0028] The row decoder 5 receives a row address from the address register 23B and decodes the row address. The row decoder 5 performs a selection operation such as a word line based on the decoded row address. Then, the row decoder 5 transmits a plurality of voltages required for write operations, read operations, and erase operations to the memory cell section 3.

[0029] The column decoder 27 receives a column address from the address register 23B and decodes the column address. The column decoder 27 performs a selection operation of bit lines based on the decoded column address.

[0030] The sense amplifier assembly 28 senses and amplifies the data read from the memory cell transistors to the bit lines during a read operation. In addition, the sense amplifier assembly 28 transmits the write data to the bit lines during a write operation.

[0031] The data register 29 temporarily stores the data transmitted by the sense amplifier assembly 28 during a read operation and serially transmits it to the input / output circuit 21. In addition, the data register 29 temporarily stores the data serially transmitted by the input / output circuit 21 during a write operation and parallel-transmits it to the sense amplifier assembly 28. The data register 29 includes SRAM and the like.

[0032] The power supply voltage VCC and the ground voltage VSS are applied to the NAND flash memory 2 via corresponding terminals. In the description of the present embodiment, the input / output circuit 21, the logic control circuit 22, the status register 23A, the address register 23B, the instruction register 23C, the sequencer 24, and the voltage generation circuit 25 are also referred to as the peripheral circuit 6. In addition, the column decoder 27, the sense amplifier assembly 28, and the data register 29 are also referred to as the page buffer 4. Some of the constituent elements can be omitted from the peripheral circuit 6, and other constituent elements not shown can be incorporated. Some of the constituent elements can be omitted from the page buffer 4, and other constituent elements not shown can be incorporated.

[0033] Subsequently, Figure 2 the memory planes 30, 31, 32, and 33 will be described. The memory planes 30, 31, 32, and 33 each include a plurality of blocks ( Figure 2 not shown). Each of the plurality of blocks includes a plurality of memory cells ( Figure 2 not shown). Figure 2 In, those that are arranged side by side with the memory planes 33 to 32, 31, 30 and along Figure 2The direction of the paper surface is set as the x-axis. It is orthogonal to the x-axis, from the following row decoder 50A towards the row decoder 50B and along Figure 2 The direction of the paper surface is set as the y-axis. It is orthogonal to the x-axis and the y-axis, and towards the front side and penetrates Figure 2 The direction of the paper surface is set as the z-axis. Figure 3 In the following figures, the x-axis, y-axis, and z-axis with the same settings are also appropriately used for explanation.

[0034] The row decoder 5 and the page buffer 4 are provided on each memory plane. The row decoders 50A, 50B and the page buffer 40 are provided on the memory plane 30. The row decoders 51A, 51B and the page buffer 41 are provided on the memory plane 31. The row decoders 52A, 52B and the page buffer 42 are provided on the memory plane 32. The row decoders 53A, 53B and the page buffer 43 are provided on the memory plane 33.

[0035] Signals are output from the control unit 61 included in the peripheral circuit 6 to the row decoders 50A, 50B, 51A, 51B, 52A, 52B, 53A, 53B, and the page buffers 40, 41, 42, 43. The control unit 61 includes, for example, the sequencer 24.

[0036] The control unit 61 is connected to the row decoder 53A and the page buffer 43 through the signal line 71. The control unit 61 is connected to the row decoder 52A and the page buffer 42 through the signal line 72.

[0037] The control unit 61 is connected to the row decoder 51A and the page buffer 41 through the signal line 74. The control unit 61 is connected to the row decoder 50A and the page buffer 40 through the signal line 73. The signal lines 73 and 74 are wired overlapping the row decoder 50A.

[0038] The control unit 61 is connected to the row decoder 50B through the signal line 75. The control unit 61 is connected to the row decoder 51B through the signal line 76. The control unit 61 is connected to the row decoder 52B through the signal line 77. The control unit 61 is connected to the row decoder 53B through the signal line 78.

[0039] At least a part of the signal lines 75, 76, 77, 78 extending from the control unit 61 passes through the non-opposing region, which is a region where the memory plane 30, which is a part of the memory cell unit 3, does not oppose the peripheral circuit 6. In addition, the signal lines 71, 72, 73, 74, 75, 76, 77, 78 are not limited to a single signal line and may also be a bundle of multiple signal lines.

[0040] Refer to Figure 3 for further explanation of the wiring around the memory plane 30. Figure 3This is a diagram for explaining the vicinity of memory plane 30. The memory plane 30 includes a memory cell array 301, an intermediate region 302, and a guard ring 303. A plurality of memory cells (not explicitly shown in Figure 3 ) are provided in the memory cell array 301.

[0041] In the memory cell array 301, word lines WL and bit lines BL are arranged in a grid corresponding to the memory cells. The word lines WL are alternately connected to connection wirings 501A and 501B. The connection wiring 501A is connected to the row decoder 50A. The connection wiring 501B is connected to the row decoder 50B. The bit lines BL are connected to the page buffer 40.

[0042] A chip edge 9 is provided so as to surround the memory plane 30, the row decoders 50A and 50B. Wiring regions 81, 82, and 83 are provided between the memory cell array 301 and the chip edge 9. More specifically, the wiring regions 81, 82, and 83 are provided corresponding to the intermediate region 302 between the memory cell array 301 and the guard ring 303.

[0043] Figure 4 This is a diagram showing Figure 3 a cross section including the x-axis and the z-axis in the IV part and viewed from the negative y-axis direction toward the positive direction. Signal lines 75, 76, 77, and 78 are provided in the wiring region 81. When viewed from the substrate SB side, the wiring region 81 is provided on the bit line BL side. The bit lines BL are arranged such that their ends do not enter the intermediate region 302. The wiring region 81 is provided from the ends of the bit lines BL to the C_Nwell region. For example, the wiring region 81 and the bit lines BL are provided in the same layer. Therefore, since the wiring region 81 and the bit lines BL do not overlap, the signal lines 75, 76, 77, and 78 in the wiring region 81 are not easily affected by noise from the bit lines BL.

[0044] Figure 5 This is a diagram showing Figure 3 a cross section including the y-axis and the z-axis in the V part and viewed from the positive x-axis direction toward the negative direction. Signal lines 75, 76, 77, and 78 are provided in the wiring region 82. The wiring region 82 is provided overlapping a part of the row decoder 50B.

[0045] Refer to Figure 9 for an explanation of the region where the wiring region 82 overlaps the row decoder 50B. Figure 9 This is a diagram for explaining the wiring inside the row decoder 50B.

[0046] As Figure 9As shown, the row decoder 50B is connected to the memory plane 30 and the control unit 61. The row decoder 50B includes a plurality of block decoders, which are connected to the blocks included in the memory plane 30 one-to-one. Therefore, the wiring in the row decoder 50B decreases as it moves away from the memory plane 30.

[0047] The row decoder 50B includes a first region 50Ba with a higher wiring density and a second region 50Bb with a lower wiring density than the first region 50Ba. In the first region 50Ba, there are two types of wiring: wiring connected to the plurality of block decoders included in the first region 50Ba and wiring passing through the first region 50Ba and connected to the plurality of block decoders included in the second region 50Bb. On the other hand, in the second region 50Bb, there is only wiring connected to the plurality of block decoders included in the second region 50Bb. Therefore, the wiring density of the first region 50Ba with respect to the total volume, that is, the wiring density, is higher than the wiring density of the second region 50Bb with respect to the total volume. In the second region 50Bb, the row decoder 50B is connected to the word line WL only through the lowermost metal layer close to the substrate SB, and the metal layer farther from the substrate is removed to ensure the wiring region 82. The wiring region 82 through which the signal lines 75, 76, 77, 78 pass is provided overlapping with the second region 50Bb.

[0048] As Figure 6 shown, a buffer 791, which is a kind of arithmetic circuit, can be provided in the wiring region 83 at the corner connecting the wiring region 81 and the wiring region 82.

[0049] Figure 7 It is a diagram showing the Figure 3 IV part during multi-layerization, and is a diagram showing a cross-section including the x-axis and the z-axis and viewed from the negative y-axis direction to the positive direction. As Figure 7 shown, a multi-layered wiring region 81A can be provided. In the intermediate region 302 between the memory cell array 301 and the guard ring 303, the bit line BL can be not arranged, and by arranging other wirings as much as possible on the substrate SB side, the wiring region 81A can be ensured. In the wiring region 81A, for example, it can include upper-layer wirings such as signal lines 75a, 76a, 77a, 78a and lower-layer wirings such as signal lines 75b, 76b, 77b, 78b.

[0050] In the multi-layered wiring region 81A, as Figure 8 shown, a logic circuit 792, which is a kind of arithmetic circuit, can be provided. The logic circuit 792 is a more complex circuit than the buffer 791, but because the volume of the wiring region 81A is larger than the volume of the wiring region 81, it can be accommodated inside.

[0051] As described above, the NAND-type flash memory 2 as a semiconductor memory device includes: a memory cell section 3 (memory planes 30, 31, 32, 33) including a memory cell array 301 composed of a plurality of memory cells; a peripheral circuit 6 that performs voltage transfer control including write, read, and erase operations on the memory cell section 3; and signal lines 75, 76, 77, 78 that connect the peripheral circuit 6 to the memory cell section 3 and at least a part thereof passes through a wiring region 81, which is a non-facing region in the peripheral region of the memory cell section 3 excluding the memory cell array 301 where the memory cell section and the peripheral circuit 6 do not face each other. By passing the signal lines through the non-facing region, the chip size is not increased and signal constraints such as interference with the bit line BL can be avoided.

[0052] The signal lines 75, 76, 77, 78 pass through a region that overlaps with the row decoder 50B in a top view, and the row decoder 50B controls the word line WL connected to the memory cell array 301. The top view, more specifically, for example, in Figure 2 is the top view when observed from the direction of the xy plane passing through the memory planes 30, 31, 32, 33 arranged. In addition, from another perspective, for example, in Figure 3 is the top view when observed from the direction of the xy plane passing through the row decoders 50A, 50B, and the page buffer 40 arranged. In addition, from another perspective, for example, in Figure 3 is the top view when observed from the direction of the xy plane passing through the row decoders 50A, 50B, and the memory cell array 301 arranged.

[0053] The row decoder 50B includes a first region 50Ba with a higher wiring density and a second region 50Bb with a wiring density lower than that of the first region 50Ba, and the signal lines 75, 76, 77, 78 pass through the region that overlaps with the second region 50Bb.

[0054] The signal line has a corner portion that bends along the outer periphery of the memory cell array at the end of the non-facing region, and a buffer 791 as an arithmetic circuit or a logic circuit 792 is provided at the corner portion.

[0055] As described above, the present embodiment has been described with reference to specific examples. However, the present invention is not limited to these specific examples. Embodiments obtained by appropriately adding design changes to these specific examples are also included in the scope of the present invention as long as they have the features of the present invention. The elements, their configurations, conditions, shapes, etc. of each of these specific examples should not be limited to the illustrated content and can be appropriately changed. The elements of each of these specific examples can be appropriately changed in combination as long as there is no technical contradiction.

[0056] [Description of symbols]

[0057] 2 NAND-type flash memory

[0058] 3 Storage cell section

[0059] 5 Row decoder

[0060] 6 Peripheral circuit

[0061] 71, 72, 73, 74, 75, 76, 77, 78 Signal lines

[0062] 301 Storage cell array

[0063] 81, 82, 83 Wiring areas

Claims

1. A semiconductor memory device includes: A memory cell section including a plurality of memory cell arrays; A peripheral circuit that performs voltage transfer control including write operations, read operations, and erase operations on the memory cell section; and Signal lines connected to the peripheral circuit and the memory cell section, at least a part of which is formed in a non-facing region, which is a region in the peripheral region formed around the memory cell arrays of the memory cell section where the memory cell section and the peripheral circuit do not face each other; The signal lines pass through a region that overlaps with a row decoder in a top view, and the row decoder controls word lines connected to the memory cell arrays; The row decoder includes a first region with a higher wiring density and a second region with a wiring density lower than that of the first region, The signal lines pass through a region that overlaps with the second region.

2. The semiconductor memory device according to claim 1, wherein The signal lines have a corner portion that bends along the outer periphery of the memory cell arrays at an end of the non-facing region, and an arithmetic circuit is provided at the corner portion.

3. A semiconductor memory device includes: A memory cell section including a plurality of memory cell arrays; A peripheral circuit that performs voltage transfer control including write operations, read operations, and erase operations on the memory cell section; and Signal lines connected to the peripheral circuit and the memory cell section, at least a part of which is formed in a non-facing region, which is a region in the peripheral region formed around the memory cell arrays of the memory cell section where the memory cell section and the peripheral circuit do not face each other; The signal lines have a corner portion that bends along the outer periphery of the memory cell arrays at an end of the non-facing region, and an arithmetic circuit is provided at the corner portion.

4. The semiconductor memory device according to claim 3, wherein The signal lines pass through a region that overlaps with a row decoder in a top view, and the row decoder controls word lines connected to the memory cell arrays.

5. The semiconductor memory device according to claim 4, wherein The row decoder includes a first region with a higher wiring density and a second region with a wiring density lower than that of the first region, The signal lines pass through a region that overlaps with the second region.

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