Memory device

Abstract

A memory device is provided. The memory device includes an array of memory cells including a plurality of memory cells; and a page buffer circuit disposed in a page buffer region including a main region and a cache region disposed along a first horizontal direction, and including a first page buffer cell and a second page buffer cell adjacent to each other along a second horizontal direction in the main region. A first readout node of the first page buffer cell includes a first lower metal pattern and a first upper metal pattern electrically connected to the first lower metal pattern. A second readout node of the second page buffer cell includes a second lower metal pattern and a second upper metal pattern electrically connected to the second lower metal pattern and not adjacent to the first upper metal pattern in the second horizontal direction.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0100118, filed with the Korean Intellectual Property Office on August 10, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to memory devices, and more specifically, to page buffer circuitry and memory devices including the page buffer circuitry. Background Technology

[0004] Recently, communication devices with multiple functions and capable of processing large amounts of information have been developed, thus requiring memory devices to have large capacity and high integration. Memory devices may include page buffers for storing data in or outputting data from memory cells, and page buffers may have semiconductor devices, such as transistors. Due to the increasing integration of memory devices and advancements in process technology, the need to reduce the size of page buffers may lead to a reduction in the size of semiconductor devices; therefore, the layout of wiring connecting to these semiconductor devices may become more complex. Summary of the Invention

[0005] According to an example embodiment, a memory device is provided, comprising: a memory cell array including a plurality of memory cells; and a page buffer circuit connected to the memory cell array, the page buffer circuit being disposed in a page buffer region, the page buffer region including a main region and a cache region arranged along a first horizontal direction, the page buffer circuit including a first page buffer unit and a second page buffer unit arranged along a second horizontal direction in the main region, wherein the first page buffer unit includes a first read node, and the second page buffer unit includes a second read node, wherein the first read node includes: a first lower metal pattern disposed in a lower metal layer; and a first upper metal pattern disposed in an upper metal layer disposed vertically above the lower metal layer, and the first upper metal pattern is electrically connected to the first lower metal pattern, and wherein the second read node includes: a second lower metal pattern disposed in the lower metal layer; and a second upper metal pattern disposed in the upper metal layer, the second upper metal pattern being electrically connected to the second lower metal pattern, and the second upper metal pattern not being adjacent to the first upper metal pattern in the second horizontal direction.

[0006] According to another example embodiment, a memory device is provided, comprising: a first semiconductor layer including a plurality of memory cells respectively connected to a plurality of bit lines extending in a first horizontal direction; and a second semiconductor layer disposed in a vertical direction perpendicular to the first semiconductor layer, the second semiconductor layer including a plurality of page buffers, wherein the plurality of page buffers include a first page buffer unit including a first read node and a second page buffer unit including a second read node, wherein the first read node includes: a first lower metal pattern disposed in the lower metal layer; and a first upper metal pattern disposed in an upper metal layer disposed vertically above the lower metal layer and electrically connected to the lower metal pattern, wherein the second read node includes: a second lower metal pattern disposed in the lower metal layer; and a second upper metal pattern disposed in the upper metal layer, wherein the second page buffer unit is adjacent to the first page buffer unit in a second horizontal direction, and wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.

[0007] According to another example embodiment, a memory device is provided, comprising: a memory cell region including a plurality of memory cells and a first metal pad; and a peripheral circuit region including a second metal pad and connected vertically to the memory cell region via the first metal pad and the second metal pad, wherein the peripheral circuit region further includes a plurality of page buffers, wherein the plurality of page buffers include a first page buffer unit including a first read node and a second page buffer unit including a second read node, wherein the first read node includes: a first lower metal pattern disposed in a lower metal layer; and a first upper metal pattern disposed in an upper metal layer disposed vertically above the lower metal layer and electrically connected to the lower metal pattern, wherein the second read node includes: a second lower metal pattern disposed in the lower metal layer; and a second upper metal pattern disposed in the upper metal layer, wherein the second page buffer unit is adjacent to the first page buffer unit in a second horizontal direction, and wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.

[0008] According to another example embodiment, a page buffer circuit is provided in a page buffer region, the page buffer region including a main region and a cache region disposed adjacent to each other in a first horizontal direction. The page buffer circuit includes: a first read latch and a second read latch disposed in the main region, the first read latch and the second read latch being adjacent to each other in a second horizontal direction; a first cache latch and a second cache latch disposed in the cache region, the first cache latch and the second cache latch being adjacent to each other in a second horizontal direction and respectively connected to the first read latch and the second read latch; a lower metal layer, encapsulating... The upper metal layer includes a first lower metal pattern disposed vertically above the first and second read latches and corresponding to a first read node connected to the first read latch, and a second lower metal pattern disposed vertically above the first and second read latches and corresponding to a second read node connected to the second read latch; and an upper metal layer including a first upper metal pattern disposed vertically above the lower metal layer and connected to the first lower metal pattern, and a second upper metal pattern disposed vertically above the lower metal layer and connected to the second lower metal pattern, wherein the first upper metal pattern and the second upper metal pattern are not adjacent to each other in the second horizontal direction. Attached Figure Description

[0009] Embodiments of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram of a memory device according to an exemplary embodiment of the present invention;

[0011] Figure 2 These are exemplary embodiments of the concept of the present invention. Figure 1 A three-dimensional view of a memory device;

[0012] Figure 3 These are exemplary embodiments of the concept of the present invention. Figure 1 A three-dimensional diagram of the memory cell array;

[0013] Figure 4 These are exemplary embodiments of the concept of the present invention. Figure 3 A 3D diagram of a memory block;

[0014] Figure 5 This is a circuit diagram of a page buffer according to an exemplary embodiment of the present invention;

[0015] Figure 6 This is a circuit diagram of a page buffer circuit according to an exemplary embodiment of the present invention;

[0016] Figure 7 This is a circuit diagram of a cache unit according to an exemplary embodiment of the present invention;

[0017] Figure 8 This is a circuit diagram of a page buffer according to an exemplary embodiment of the present invention;

[0018] Figure 9 This is a block diagram of a page buffer circuit and a page buffer decoder according to an exemplary embodiment of the present invention.

[0019] Figure 10 These are exemplary embodiments of the concept of the present invention. Figure 9 A block diagram of the page buffer circuit;

[0020] Figure 11 This is a top view of a page buffer circuit according to an exemplary embodiment of the present invention;

[0021] Figure 12 These are exemplary embodiments of the concept of the present invention. Figure 11 A three-dimensional view of the first to third metal layers;

[0022] Figure 13 This is a cross-sectional view of a page buffer circuit according to an exemplary embodiment of the present invention;

[0023] Figures 14 to 17 This is the layout of the third metal layer according to some exemplary embodiments of the present invention;

[0024] Figure 18 This is a top view of a page buffer circuit according to an exemplary embodiment of the present invention;

[0025] Figures 19 to 22 This is the layout of the first to third metal layers according to some exemplary embodiments of the present invention;

[0026] Figure 23 and Figure 24 This is a circuit diagram of a page buffer according to some exemplary embodiments of the present invention;

[0027] Figures 25 to 28 This is the layout of the third metal layer according to some exemplary embodiments of the present invention;

[0028] Figure 29 This is a cross-sectional view of a memory device according to an exemplary embodiment of the present invention; and

[0029] Figure 30 This is a block diagram of an example solid-state drive (SSD) system that applies an exemplary embodiment of a memory device according to a concept of the present invention. Detailed Implementation

[0030] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a block diagram of a memory device 10 according to an exemplary embodiment of the present invention.

[0032] refer to Figure 1 The memory device 10 may include a memory cell array 100 and peripheral circuitry 200. According to an example embodiment, the peripheral circuitry 200 may include a page buffer circuit 210, a control circuit 220, a voltage generator 230, and a line decoder 240. According to an example embodiment, the peripheral circuitry 200 may also include data input / output circuitry, input / output interfaces, etc.

[0033] The memory cell array 100 can be connected to the page buffer circuit 210 via the bit line BL, and to the row decoder 240 via the word line WL, the serial select line SSL, and the ground select line GSL. The memory cell array 100 may include multiple memory cells, and the memory cells may be, for example, flash memory cells. Hereinafter, embodiments of the inventive concept will be described in detail with reference to the case where, by way of example, the multiple memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the multiple memory cells may be resistive memory cells, such as resistive random access memory (ReRAM), phase-change RAM (PRAM), or magnetic random access memory (MRAM).

[0034] In an example embodiment, the memory cell array 100 may include a three-dimensional memory cell array that may include a plurality of NAND strings, each NAND string including memory cells respectively connected to word lines vertically stacked on a substrate, which will refer to Figure 3 and Figure 4 A detailed description is provided. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648, describe in detail suitable features of a three-dimensional memory cell array configured on multiple levels, wherein word lines and / or bit lines are shared between levels, all of which are incorporated herein by reference. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the memory cell array 100 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include multiple NAND strings arranged in the row and column directions.

[0035] The control circuit 220 can output various control signals, such as the voltage control signal CTRL_vol, the row address X-ADDR, and the column address Y-ADDR, for programming, reading, or erasing data stored in the memory cell array 100 based on the command CMD, the address ADDR, and the control signal CTRL. In doing so, the control circuit 220 can typically control various operations within the memory device 10.

[0036] Voltage generator 230 can generate various types of voltages for performing programming, reading, and erasing operations on memory cell array 100 based on the voltage control signal CTRL_vol. Specifically, voltage generator 230 can generate word line voltages VWL, such as programming voltage, read voltage, pass voltage, erase voltage, or programming verification voltage. Furthermore, voltage generator 230 can also generate serial select line voltages and ground select line voltages based on the voltage control signal CTRL_vol.

[0037] In response to the row address X-ADDR, the row decoder 240 can select one of a plurality of memory blocks, one of the word lines WL of the selected memory block, and one of a plurality of string select lines SSL. The page buffer circuit 210 can select some of the bit lines BL in response to the column address Y-ADDR. For example, the page buffer circuit 210 operates as a write driver or a sense amplifier depending on the operating mode.

[0038] Page buffer circuit 210 may include a plurality of page buffers PB, each connected to a plurality of bit lines BL. In an example embodiment, each of the plurality of page buffers includes a page buffer unit (e.g., Figure 6 The cache units (e.g., CU0 to CU7 in the figure) included in each of the multiple page buffers can be separated and isolated from each other. Therefore, the degree of freedom in routing on the page buffer units can be improved, and the layout complexity can be reduced. Furthermore, the cache units can be positioned adjacent to the data input-output lines, reducing the distance between the cache units and the data input-output lines, thereby improving the data input-output rate.

[0039] In the example embodiment, the sensing node of each page buffer unit can be implemented using multiple metal layers arranged in the vertical direction, thus increasing the capacitance of the sensing node. According to the example embodiment, "metal layer" can refer to a "conductive layer" and is not limited to a metallic material. Furthermore, a shielding metal pattern applying a power supply voltage or a ground voltage can be provided on both sides of the metal pattern on which the sensing node is implemented, thus preventing coupling between adjacent sensing nodes. Therefore, during read operations on the memory device 10, voltage variations in the sensing nodes can be reduced, thereby improving the read reliability of the memory device 10.

[0040] Figure 2 These are exemplary embodiments of the concept of the present invention. Figure 1 A perspective view of the memory device 10.

[0041] refer to Figure 2 The memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in the vertical direction VD. Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction VD, so that the second semiconductor layer L2 can be closer to the substrate.

[0042] In the example embodiment, Figure 1 The memory cell array 100 can be formed in the first semiconductor layer L1, and Figure 1 The peripheral circuitry 200 can be formed in the second semiconductor layer L2. Therefore, the memory device 10 can have a structure in which the memory cell array 100 is on the peripheral circuitry 200, i.e., a cell over periphery (COP) structure. The COP structure can effectively reduce the area in the horizontal direction and improve the integration density of the memory device 10.

[0043] In an example embodiment, the second semiconductor layer L2 may include a substrate, and the peripheral circuitry 200 may be formed by creating transistors and metal patterns on the substrate (e.g., Figure 11 A first metal layer to a third metal layer (LM0, LM2, and LM3) are formed in a second semiconductor layer L2, wherein metal patterns are used to interconnect transistors on the substrate. After the peripheral circuitry 200 is formed in the second semiconductor layer L2, a first semiconductor layer L1 including a memory cell array 100 can be formed, and metal patterns for electrically connecting word lines WL and bit lines BL of the memory cell array 100 to the peripheral circuitry 200 formed in the second semiconductor layer L2 can be formed. For example, the bit line BL may extend in a first horizontal direction HD1, while the word line WL may extend in a second horizontal direction HD2.

[0044] With advancements in semiconductor technology, more layers of memory cells can be arranged in the memory cell array 100. In other words, the more word lines (WL) are stacked, the smaller the area of ​​the memory cell array 100, and therefore, the smaller the area of ​​the peripheral circuitry 200. According to an example embodiment, to reduce the area occupied by the page buffer circuitry 210, the page buffer circuitry 210 can have a structure where the page buffer cells are separated from the cache latches, and the read nodes, each included in the page buffer cells, can be jointly connected to a combined read node. This will be referred to... Figure 6 Provide a detailed description.

[0045] Figure 3 These are exemplary embodiments of the concept of the present invention. Figure 1 A three-dimensional view of the memory cell array 100.

[0046] refer to Figure 3 The memory cell array 100 may include multiple memory blocks BLK0, BLK1, ..., BLKi, where i represents a positive integer. Each of the multiple memory blocks BLK0 to BLKi may have a three-dimensional structure. For example, each of the multiple memory blocks BLK0 to BLKi may have a vertical structure. For example, each of the multiple memory blocks BLK0 to BLKi may include multiple NAND strings extending in the vertical direction VD. In this case, the multiple NAND strings may be separated by a specific distance in the first horizontal direction HD1 and the second horizontal direction HD2. The multiple memory blocks BLK0 to BLKi may be decoded by a line decoder (i.e., ... Figure 1 The row decoder 240 selects the memory block corresponding to the block address from a plurality of memory blocks BLK0 to BLKi.

[0047] Figure 4 These are exemplary embodiments of the concept of the present invention. Figure 3 A 3D view of memory block BLK0.

[0048] refer to Figure 4 The memory block BLK0 is formed on a substrate SUB in the vertical direction VD. The substrate SUB has a first conductivity type (e.g., p-type) and includes a common source line CSL extending along a second horizontal direction HD2 on the substrate SUB and doped with impurities of a second conductivity type (e.g., n-type). However, this disclosure is not limited to a substrate SUB having a p-type conductivity type; therefore, according to another example embodiment, the substrate SUB may be n-type conductive and may include a common source line CSL extending along a second horizontal direction HD2 on the substrate SUB and doped with p-type conductive impurities.

[0049] Multiple insulating films IL extending in the second horizontal direction HD2 are sequentially disposed in the region between two adjacent common source lines CSL of the substrate SUB in the vertical direction VD, and the multiple insulating films IL are separated by a specific distance in the vertical direction VD. For example, the multiple insulating films 11 may comprise an insulating material, such as silicon oxide.

[0050] In the region between two adjacent common source lines CSL of the substrate SUB, a plurality of pillars P are disposed sequentially along a first horizontal direction HD1 and pass through a plurality of insulating films IL along a vertical direction VD. For example, the plurality of pillars P can contact the substrate SUB by passing through the plurality of insulating films IL. Specifically, the surface layer S of each pillar P may include a silicon material of a first type and used as a channel region. The inner layer I of each pillar P may include an insulating material, such as silicon oxide or an air gap.

[0051] In the region between two adjacent common source lines CSL, a charge storage layer CS is disposed along the exposed surfaces of multiple insulating films IL, multiple pillars P, and a substrate SUB. The charge storage layer CS may include a gate insulating layer (or tunnel insulating layer), a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Furthermore, in the region between the two adjacent common source lines CSL, gate electrodes GE, including select lines GSL and SSL and word lines WL0 to WL7, are disposed on the exposed surface of the charge storage layer CS. According to an example embodiment, a string select transistor SST is disposed corresponding to the string select line SSL, and a ground select transistor GST is disposed corresponding to the ground select line GSL.

[0052] Each of the drains or drain contacts DRs is disposed on a plurality of pillars P. For example, the drain or drain contact DR may comprise silicon material doped with impurities having a second conductivity type. Bit lines BL0 to BL2, extending in a first horizontal direction HD1 and separated by a specific distance in a second horizontal direction HD2, are disposed on the drain DR.

[0053] Figure 5 This is a circuit diagram of a page buffer PB according to an exemplary embodiment of the present invention.

[0054] refer to Figure 5 The page buffer PB can correspond to Figure 1An example of a page buffer PB. The page buffer PB may include a page buffer unit (PBU) and a cache unit (CU). The cache unit CU may include a cache latch (C-LATCH) CL. According to the example embodiment, the C-LATCH CL is connected to the data input-output line; therefore, the cache unit CU may be adjacent to the data input-output line. Thus, the page buffer unit PBU may be separate from the cache unit CU, and the page buffer PB may have a separate structure corresponding to the page buffer unit PBU and the cache unit CU.

[0055] The page buffer unit (PBU) may include the master unit (MU). The master unit (MU) may include the master transistor in the page buffer (PB). The page buffer unit (PBU) may also include a bit line selection transistor (TR_hv) connected to the bit line (BL) and driven by the bit line selection signal (BLSLT). The bit line selection transistor may be implemented by a high-voltage transistor; therefore, the bit line selection transistor may be located in a well region different from the master unit (MU), i.e., in the high-voltage unit (HVU).

[0056] The master unit MU may include a sensing latch (S-LATCH) SL, a force latch (F-LATCH) FL, a most significant bit latch (M-LATCH) ML, and a least significant bit latch (L-LATCH) LL. According to an example embodiment, S-LATCH SL, F-LATCH FL, M-LATCH ML, or L-LATCH LL may be referred to as the "master latch". The master unit MU may also include a precharge circuit PC capable of controlling the precharge operation of bit line BL or sensing node SO based on the bit line clamping control signal BLCLAMP, and a transistor PM' driven by the bit line setup signal BLSETUP.

[0057] S-LATCH SL can store data stored in a memory cell or the read result of the threshold voltage of the memory cell during read or program verification operations. Furthermore, during programming operations, S-LATCH SL can be used to apply a programming bit line voltage or a programming disable voltage to the bit line BL. F-LATCH FL can be used to improve the threshold voltage distribution during programming operations. M-LATCH ML and L-LATCH LL of the page buffer unit PBU and C-LATCH CL of the cache unit CU can be used to store data input from an external source during programming operations and can be referred to as "data latches". When programming 3 bits of data on a memory cell, these 3 bits can be stored separately in M-LATCH ML, L-LATCH LL, and C-LATCH CL. For example, one bit from the 3 bits of data can be stored separately in each of M-LATCH ML, L-LATCH LL, and C-LATCH CL. In addition, during read operations, C-LATCH CL can receive data read from the memory cell from S-LATCH SL and output the data to the outside via the data input-output line.

[0058] In addition, the main unit MU may also include a first transistor NM1 to a fourth transistor NM4. The first transistor NM1 may be connected between the read node SO and the S-LATCH SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected between the read node SO and the F-LATCH FL, and may be driven by the forced monitoring signal MON_F. The third transistor NM3 may be connected between the read node SO and the M-LATCH ML, and may be driven by the most significant bit monitoring signal MON_M. The fourth transistor NM4 may be connected between the read node SO and the L-LATCH LL, and may be driven by the least significant bit monitoring signal MON_L.

[0059] In addition, the main unit MU may also include a fifth transistor NM5 and a sixth transistor NM6 connected in series between the bit line selection transistor TR_hv and the read node SO. The fifth transistor NM5 may be driven by the bit line off signal BLSHF, while the sixth transistor NM6 may be driven by the bit line connection control signal CLBLK. Furthermore, the main unit MU may also include a precharge transistor PM. The precharge transistor PM may be connected to the read node SO, may be driven by the load signal LOAD, and may precharge the read node SO to a precharge level during the precharge duration.

[0060] In an example embodiment, the main unit MU may further include a pair of pass transistors connected to the readout node SO, namely, a first pass transistor TR and a second pass transistor TR'. According to the example embodiment, the first pass transistor TR and the second pass transistor TR' may be referred to as "first readout node connection transistor and second readout node connection transistor". The first pass transistor TR and the second pass transistor TR' may be driven by a pass control signal SO_PASS. According to the example embodiment, the pass control signal SO_PASS may be referred to as "readout node connection control signal". The first pass transistor TR may be connected between the first terminal SOC_U and the readout node SO, while the second pass transistor TR' may be connected between the readout node SO and the second terminal SOC_D.

[0061] The page buffer PB verifies whether a selected memory cell from the NAND string connected to bit line BL has been fully programmed during a programming operation. Specifically, during a programming verification operation, the page buffer PB can store data read through bit line BL in S-LATCH SL. Based on the read data stored in S-LATCH SL, locks M-LATCH ML and L-LATCH LL, where the target data is stored, are set. For example, when the read data indicates programming is complete, in subsequent programming cycles, M-LATCH ML and L-LATCH LL are switched to the programming-disabled setting for the selected memory cell. C-LATCH CL can temporarily store input data provided from an external source. During a programming operation, the target data stored in C-LATCH CL can be stored in M-LATCH ML and L-LATCH LL.

[0062] According to an example embodiment, the first cache unit CU may include a monitoring transistor NM7. The source S of the monitoring transistor NM7 may be connected to the combined read node SOC, and a cache monitoring signal MON_C may be applied to the gate of the monitoring transistor NM7. Furthermore, the cache unit CU may include the monitoring transistor NM7 and a C-LATCH CL.

[0063] Figure 6 This is a circuit diagram of a page buffer circuit 210a according to an exemplary embodiment of the present invention.

[0064] refer to Figure 6The page buffer circuit 210a may include a first page buffer unit PBU0 to an eighth page buffer unit PBU7 disposed on the first horizontal direction HD1, and a first cache unit CU0 to an eighth cache unit CU7 disposed on the first horizontal direction HD1. For example, each of the first page buffer unit PBU0 to the eighth page buffer unit PBU7 may be implemented substantially similar to Figure 5 The page buffer unit (PBU), each of the first cache unit (CU0) through the eighth cache unit (CU7) can be implemented as substantially similar to Figure 5 The cache unit CU, and the above reference Figure 5 The description provided can be applied to this example embodiment.

[0065] The first page buffer unit PBU0 may include a first transfer transistor TR0 and a second transfer transistor TR0' connected in series, while the second page buffer unit PBU1 may include a first transfer transistor TR1 and a second transfer transistor TR1' connected in series. A transfer control signal SO_PASS[7:0] may be applied to the gates of the first transfer transistors TR0, TR1, and the second transfer transistors TR0', TR1'. According to an example embodiment, when the transfer control signal SO_PASS[7:0] is activated, the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' can be turned on. Therefore, the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' included in the first page buffer units PBU0 to the eighth page buffer units PBU7 respectively can be connected in series with each other, and all the first read nodes SO0 to the eighth read nodes SO7 can be connected to the combined read node SOC.

[0066] Page buffer units PBU0 through PBU7 may further include precharge transistors PM0 through PM7. In page buffer unit PBU0, precharge transistor PM0 may be connected between first read node SO0 and a voltage terminal to which a precharge level is applied, and may have a gate to which a load signal LOAD is applied. Precharge transistor PM0 may precharge first read node SO0 to a precharge level in response to the load signal LOAD.

[0067] The first cache unit CU0 may include a monitoring transistor NM7a, and for example, the monitoring transistor NM7a may correspond to Figure 5The monitoring transistor NM7a has its source S connected to the combined readout node SOC, and the cache monitoring signals MON_C[7:0] can be applied to the gates of the monitoring transistors NM7a to NM7h respectively. The monitoring transistors NM7a to NM7h, which are respectively included in the first cache unit CU0 to the eighth cache unit CU7, can be connected in parallel to the combined readout node SOC. Specifically, the sources of the monitoring transistors NM7a to NM7h can be connected in parallel to the combined readout node SOC.

[0068] The page buffer circuit 210a may further include a precharge circuit SOC_PRE located between the eighth page buffer unit PBU7 and the first cache unit CU0. The precharge circuit SOC_PRE may include a precharge transistor PMA and a shield transistor NMa for precharging the combined read node SOC. The precharge transistor PMA may be driven by the combined read node load signal SOC_LOAD, and when the precharge transistor PMA is turned on, the combined read node SOC can be precharged to the precharge level. The shield transistor NMa may be driven by the combined read node shield signal SOC_SHLD, and when the shield transistor NMa is turned on, the combined read node SOC can be discharged to ground.

[0069] In a structure where the first page buffer units PBU0 to PBU7 are separate from the first cache units CU0 to CU7, if eight signal lines are used to connect the first page buffer units PBU0 to PBU7 to the first cache units CU0 to CU7 respectively, the size of the page buffer circuit 210a in the second horizontal direction HD2 will increase. However, according to an example embodiment, the first read nodes SO0 to SO7 can be connected to each other using the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' respectively included in the first page buffer units PBU0 to PBU7, and the first read nodes SO0 to SO7 can be connected to the first cache units CU0 to CU7 through a combined read node SOC. By doing so, the increase in the size of the page buffer circuit 210a in the second horizontal direction HD2 can be prevented.

[0070] Figure 7 This is a circuit diagram of a cache unit CU according to an exemplary embodiment of the present invention.

[0071] refer to Figure 7The cache unit CU may include a monitoring transistor NM7 and a C-LATCH CL, and the C-LATCH CL may include a first inverter INV1 and a second inverter INV2, a dump transistor 132, and transistors 131, 133, 134, and 135. The monitoring transistor NM7 may be driven by the cache monitoring signal MON_C and may control the connection between the combined read node SOC and the C-LATCH CL.

[0072] A first inverter INV1 can be connected between the first node ND1 and the second node ND2, and a second inverter INV2 can be connected between the second node ND2 and the first node ND1. The first inverter INV1 and the second inverter INV2 can form a latch. Transistor 131 has a gate connected to the combined read node SOC. Dump transistor 132 can be driven by the dump signal Dump_C and can transfer data stored in C-LATCH CL to the main latch of the page buffer unit PBU (i.e., one of S-LATCH SL, F-LATCH FL, M-LATCH ML, or L-LATCH LL). Transistor 133 can be driven by the data signal DI, transistor 134 can be driven by the inverted data signal nDI, and transistor 135 can be driven by the write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first node ND1 and the second node ND2 can be determined based on the data signal DI and the inverted data signal nDI.

[0073] The cache unit CU can be connected to the input-output terminal RDi via transistors 136 and 137. Transistor 136 has a gate connected to the second node ND2 and can be turned on or off depending on the voltage level of the second node ND2. Transistor 137 can be driven by the read control signal DIO_R. When the read control signal DIO_R is activated, causing transistor 137 to turn on, the voltage level of the input-output terminal RDi can be determined as "1" or "0" according to the state of C-LATCH CL.

[0074] Figure 8 This is a circuit diagram of a page buffer PB' according to an exemplary embodiment of the present invention.

[0075] refer to Figure 8 Page buffer PB' may include page buffer unit PBU' and cache unit CU, and page buffer unit PBU' may include main unit MU' and high voltage unit HVU. Page buffer PB' may correspond to Figure 5 The example of modifying the page buffer PB, and the above reference Figures 5 to 7 The description provided can be applied to the example embodiments. Figure 5The page buffer unit (PBU) includes a first transistor TR and a second transistor TR', while the page buffer unit PBU' according to the example embodiment may include a transfer transistor TR'. The transfer transistor TR' may be driven by the transfer control signal SO_PASS and may be connected between the first terminal SOC_U and the second terminal SOC_D.

[0076] Figure 9 This is a block diagram of a page buffer circuit 210 and a page buffer decoder 250 according to an exemplary embodiment of the present invention.

[0077] refer to Figure 9 The page buffer circuit 210 may include a first page buffer circuit PGBUFa to a fourth page buffer circuit PGBUFd disposed on the second horizontal direction HD2, and for example, each of the first page buffer circuit PGBUFa to the fourth page buffer circuit PGBUFd may be implemented as... Figure 6 The page buffer circuit 210 is the same as that of the page buffer circuit. Therefore, the page buffer circuit 210 can be implemented in the form of a page buffer array. However, the inventive concept is not limited thereto, and each of the first page buffer circuits PGBUFa to the fourth page buffer circuits PGBUFd can include multiple page buffers, and each of the multiple page buffers can be implemented as the same as the page buffer array. Figure 8 The page buffer PB' is the same.

[0078] Page buffer decoder 250 may be adjacent to page buffer circuit 210 in the first horizontal direction HD1, and may include first to fourth page buffer decoders PBDECa to PBDECd disposed in the second horizontal direction HD2. The first page buffer decoder PBDECa to the fourth page buffer decoder PBDECd may be connected to the first page buffer circuit PGBUFa to the fourth page buffer circuit PGBUFd, respectively. For example, the first page buffer decoder PBDECa may generate a decoder output signal corresponding to the number of failure bits based on the page buffer signal received from the first page buffer circuit PGBUFa. For example, when the page buffer signal is logic low, the programming of the corresponding memory cell may be determined as a failure, and the data programmed into the corresponding memory cell may be determined as a failure bit.

[0079] Figure 10 These are exemplary embodiments of the concept of the present invention. Figure 9 Block diagram of page buffer circuit 210.

[0080] refer to Figure 10The first page buffer circuit PGBUFa may include page buffer units PBU0a to PBU7a and cache units CU0a to CU7a. Each read node of page buffer units PBU0a to PBU7a can be connected to the read node SOC1 of the first combination, and the cache units CU0a to CU7a can also be connected to the read node SOC1 of the first combination. The second page buffer circuit PGBUFb may include page buffer units PBU0b to PBU7b and cache units CU0b to CU7b. ​​The corresponding read nodes of page buffer units PBU0b to PBU7b can be connected to the read node SOC2 of the second combination, and the cache units CU0b to CU7b can also be connected to the read node SOC2 of the second combination. The third page buffer circuit PGBUFc may include page buffer units PBU0c to PBU7c and cache units CU0c to CU7c. The corresponding read nodes of page buffer units PBU0c to PBU7c can be connected to the read node SOC3 of the third combination, and the cache units CU0c to CU7c can also be connected to the read node SOC3 of the third combination. The fourth page buffer circuit PGBUFd may include page buffer units PBU0d to PBU7d and cache units CU0d to CU7d. The corresponding read nodes of page buffer units PBU0d to PBU7d can be connected to the read node SO4 of the fourth combination, and the cache units CU0d to CU7d can also be connected to the read node SO4 of the fourth combination.

[0081] Figure 11 This is a top view of a page buffer circuit 20 according to an exemplary embodiment of the present invention. Figure 12 These are exemplary embodiments of the concept of the present invention. Figure 11 A three-dimensional view of the first metal layer LM0 to the third metal layer LM2.

[0082] Reference Figure 11 and Figure 12 The page buffer circuit 20 may include a first page buffer unit PBU0a and a second page buffer unit PBU0b adjacent to each other in the second horizontal direction HD2. The first page buffer unit PBU0a may include a transistor TRa, and the transistor TRa may include a source S0a, a gate G0a, and a drain D0a. The second page buffer unit PBU0b may include a transistor TRb, and the transistor TRb may include a source S0b, a gate G0b, and a drain D0b. For example, transistors TRa and TRb may correspond to... Figure 5 The transmission transistor TR shown is Figure 8 The transmission transistor TR is shown. However, the present invention is not limited to this.

[0083] A first metal layer LM0, a second metal layer LM1, and a third metal layer LM2 can be disposed above the page buffer circuit 20 in the vertical direction VD. For example, the first metal layer LM0 and the third metal layer LM2 can extend in the first horizontal direction HD1, while the second metal layer LM1 can extend in the second horizontal direction HD2. The first metal layer LM0 may include first metal patterns LM0a and LM0b, the second metal layer LM1 may include second metal patterns LM1a and LM1b, and the third metal layer LM2 may include third metal patterns LM2a and LM2b. For example, the pitch of the first metal patterns LM0a and LM0b may be smaller than the pitch of the third metal patterns LM2a and LM2b. For example, the thickness of the first metal patterns LM0a and LM0b in the vertical direction VD may be smaller than the thickness of the third metal patterns LM2a and LM2b in the vertical direction VD. According to the example embodiment, the "first metal layer" may be referred to as the "lower metal layer," the "third metal layer" may be referred to as the "upper metal layer," the "first metal pattern" may be referred to as the "lower metal pattern," and the "third metal pattern" may be referred to as the "upper metal pattern."

[0084] The first to third metal patterns LM0a, LM1a, and LM2a above the first page buffer unit PBU0a can be connected to each other, thus enabling the implementation of the first read node SO0. For example, the first metal pattern LM0a can be connected to the drain D0a of transistor TRa via contact CT0a, the second metal pattern LM1a can be connected to the first metal pattern LM0a via contact CT1a, and the third metal pattern LM2a can be connected to the second metal pattern LM1a via contact CT2a. In this case, the third metal pattern LM2a can be referred to as the first read node SO0 or the first read plus node SO0+. As described above, by using multiple metal layers to implement the first read node SO0, the total capacitance of the first read node SO0 can be increased to a sufficiently large value related to the read current, thereby providing robustness to changes in read conditions. Therefore, during read operations, the voltage variation of the first read node SO0 can be reduced, and the read reliability of the first read node SO0 can be improved.

[0085] The first to third metal patterns LM0b, LM1b, and LM2b above the second page buffer unit PBU0b can be connected to each other, thus enabling the implementation of a second read node SO1. For example, the first metal pattern LM0b can be connected to the drain D0b of transistor TRb via contact CT0b, the second metal pattern LM1b can be connected to the first metal pattern LM0b via contact CT1b, and the third metal pattern LM2b can be connected to the second metal pattern LM1b via contact CT2b. In this case, the third metal pattern LM2b can be referred to as the second read node SO1 or the second read plus node SO1+. As described above, by using multiple metal layers to implement the second read node SO1, the total capacitance of the second read node SO1 can be increased to a sufficiently large value related to the read current to provide robustness against changes in read conditions. Therefore, during read operations, the voltage variation of the second read node SO1 can be reduced, and the read reliability of the second read node SO1 can be improved.

[0086] In the example embodiment, the third metal patterns LM2a and LM2b may not be adjacent in the second horizontal direction HD2. For example, the third metal patterns LM2a and LM2b may be separated by a first distance, i.e., a first spacing SP in the first horizontal direction HD1. Therefore, because the coupling between the third metal patterns LM2a and LM2b can be reduced, the voltage change of the second read node SO1 will not affect the voltage of the first read node SO0, thus improving the read reliability of the memory device.

[0087] In an exemplary embodiment, the first metal layer LM0 may further include first metal patterns LM0c, LM0d, and LM0e between first metal patterns LM0a and LM0b. Each of the first metal patterns LM0c, LM0d, and LM0e may include multiple patterns separated from each other, and, for example, these multiple patterns may be connected to multiple transistors. For example, an internal power supply voltage or ground voltage may be applied to the first metal pattern LM0c, thus the first metal pattern LM0a corresponding to the first readout node SO0 may be shielded. In an exemplary embodiment, the metal pattern to which the internal power supply voltage or ground voltage is applied may be referred to as a "power supply pattern". Furthermore, for example, an internal power supply voltage or ground voltage may be applied to the first metal pattern LM0e, thus the first metal pattern LM0b corresponding to the second readout node SO1 may be shielded. As described above, according to an exemplary embodiment, by providing first metal patterns LM0c and LM0e with fixed bias voltages on one side of the first metal patterns LM0a and LM0b corresponding to the first readout node SO0 and the second readout node SO1, respectively, voltage variations in each of the first readout node SO0 and the second readout node SO1 can be minimized.

[0088] According to the microprocessor, the area occupied by the page buffer circuit 20 is based on the transistor width WD. For example, the smaller the transistor width WD, the smaller the area occupied by the page buffer circuit 20. For example, the transistor width WD can correspond to the size of the gate G0a of the transistor TRa in the second horizontal direction HD2. Specifically, the smaller the transistor width WD, the smaller the size of the first page buffer unit PBU0a in the second horizontal direction HD2. However, regardless of the reduction in transistor width WD, the spacing of the first metal layer LM0 does not decrease. Therefore, the number of wirings (i.e., the number of metal patterns) above the first page buffer unit PBU0a with a reduced size in the second horizontal direction HD2 can also be reduced. For example, the number of metal patterns corresponding to the first metal layer LM0 of the first page buffer unit PBU0a can be reduced from 6 to 4.

[0089] When the number of metal patterns in the first metal layer LM0 corresponding to the first page buffer unit PBU0a decreases, the read reliability of the first page buffer unit PBU0a may decrease. For example, during read operations, to prevent coupling between the first read node SO0 and adjacent nodes, the metal pattern adjacent to the first read node SO0 can be used as a shield to apply a fixed bias voltage to it. However, when the metal pattern corresponding to the shield is removed due to the reduction in the number of metal patterns, the voltage variation of the first read node SO0 may increase due to the coupling between the first read node SO0 and adjacent nodes, thus potentially reducing the read reliability of the first page buffer unit PBU0a.

[0090] However, according to the example embodiment, by using a separate page buffer unit-cache unit structure, the degrees of freedom of the metal pattern in the third metal layer LM2 above the first page buffer unit PBU0a can be increased, allowing one of the metal patterns in the third metal layer LM2 to be used as the first read add node SO0+. By connecting the first read node SO0 to the first read add node SO0+, an increase in the voltage variation of the first read node SO0 can be prevented, thus preventing a decrease in the read reliability of the first page buffer unit PBU0a.

[0091] Figure 13 This is a cross-sectional view of a page buffer circuit 20a according to an exemplary embodiment of the present invention.

[0092] refer to Figure 13 The page buffer circuit 20a corresponds to Figure 11 The page buffer circuit 20 shown is a modified example, and the above references... Figure 11 and Figure 12The description provided can also be applied to this example embodiment. Page buffer circuit 20a may include a transistor TR on the substrate SUB. For example, transistor TR may correspond to... Figure 5 The transmission transistor TR shown is Figure 8 The transmission transistor TR is shown. However, the inventive concept is not limited thereto. The first metal layer LM0 may extend in the first horizontal direction HD1 and may be connected to the source / drain region S / D of the transistor TR via contact CT0. The second metal layer LM1 may extend in the second horizontal direction HD2 and may be connected to the first metal layer LM0 via contact CT1. The third metal layer LM2 may extend in the first horizontal direction HD1 and may be connected to the second metal layer LM1 via contact CT2. As described above, according to the exemplary embodiment, the third metal layer LM2 and the first metal layer LM0 may partially overlap in the vertical direction VD.

[0093] Figure 14 This is the layout 30 of the third metal layer LM2 above the page buffer circuit 210 and page buffer decoder 250 in an exemplary embodiment of the present invention.

[0094] refer to Figure 14 Page buffer circuit 210 and page buffer decoder 250 can be disposed on the first horizontal direction HD1. Page buffer circuit 210 can be disposed in the page buffer region including main region MR and cache region CR. Page buffer unit array including page buffer units PBU0a to PBU0d can be disposed on main region MR, and cache unit array including cache units CU0a to CU0d can be disposed on cache region CR.

[0095] The third metal layer LM2 may include metal patterns 311 to 318 and 321 to 328 extending in the first horizontal direction HD1, and may be disposed above the page buffer circuit 210 and the page buffer decoder 250 in the vertical direction VD. For example, the third metal layer LM2 may correspond to Figures 11 to 13 The third metal layer LM2. Metal patterns 311, 314, and 316 can be positioned above the main region MR, cache region CR, and page buffer decoder 250 by crossing them, while metal pattern 315 can be positioned above the main region MR and cache region CR by crossing them. For example, the internal power supply voltage IVC can be applied to metal patterns 311 and 316, the ground voltage GND can be applied to metal pattern 314, and the first page buffer driver signal PBDRV can be applied to metal pattern 315.

[0096] Metal patterns 312, 313, 317, and 318 can be disposed above the cache region CR and page buffer decoder 250 by intersecting the cache region CR and page buffer decoder 250. Metal patterns 312, 313, 317, and 318 can be electrically connected to the cache units CU0a to CU0d and the page buffer decoder 250 by contacts CT. Metal patterns 321 to 328 can be disposed above the main region MR by intersecting the main region MR.

[0097] As per the above reference Figure 10 The page buffer circuit 210 may have a separate page buffer unit-cache unit structure. For example, in the page buffer circuit 210, metal patterns 312, 313, 317, and 318 that apply signals associated with cache units CU0a to CU0d can be disposed above the cache region CR and the page buffer decoder 250, and may not extend into the main region MR. For example, metal patterns 312 and 318 may correspond to the input-output terminal RDi and the inverting input-output terminal nRDi, respectively, while the inverting data signal nDI and the data signal DI may be applied to metal patterns 313 and 317, respectively.

[0098] According to the page buffer unit-cache unit separation structure, the wiring freedom of the third metal layer LM2 above the main region MR where page buffer units PBU0a to PBU0d are disposed can be increased. Therefore, some metal patterns 321 to 324 of the third metal layer LM2 above the main region MR can be used as the first read nodes SO0 to the fourth read nodes SO3 of the page buffer units PBU0a to PBU0d, respectively. Specifically, the first read nodes SO0 to the fourth read nodes SO3 can be implemented by metal patterns included in the first metal layer LM0, and the metal patterns included in the first metal layer LM0 can be electrically connected to the metal patterns 321 to 324 included in the third metal layer LM2, thus increasing the capacitance of each of the first read nodes SO0 to the fourth read nodes SO3.

[0099] Figure 15 This is the layout 30a of the third metal layer LM2 in an exemplary embodiment of the present invention.

[0100] refer to Figure 15 Layout 30a corresponds to Figure 14 The layout of 30 is modified from Example 4, and repeated descriptions are omitted. In the cache region CR, for example, it provides... Figure 6The first cache unit CU0 to the eighth cache unit CU7. The main region MR may include a low-voltage region LV and a high-voltage region HV. For example, in the low-voltage region LV, it can provide Figure 5 main unit MU or Figure 8 The primary unit MU' in the high voltage region HV can provide Figure 5 or Figure 8 The high-voltage unit HVU. Although for convenience, Figure 15 A low-voltage region LV and a high-voltage region HV are shown, but the invention is not limited thereto. For example, multiple low-voltage regions and multiple high-voltage regions corresponding to the first cache units PBU0 to the eighth cache units PBU7 can be provided on the first horizontal direction HD1. The page buffer units in the main region MR can be connected to the column driver, and the column driver can provide gate drive voltages respectively applied to the gates of the transistors included in the page buffer units.

[0101] The third metal layer LM2 may include metal patterns 311 to 318, 321 to 328, and 331 to 334 extending in the first horizontal direction HD1. Metal patterns 311, 314, and 316 may be disposed above the main region MR, cache region CR, and page buffer decoder 250 by crossing the main region MR, cache region CR, and page buffer decoder 250, while metal pattern 315 may be disposed above the main region MR and cache region CR by crossing the main region MR and cache region CR. For example, a first page buffer driver signal PBDRV may be applied to metal pattern 315, and metal pattern 315 may be connected to a column driver. Metal patterns 331 to 334 may be disposed above the high-voltage region HV of the page buffer circuit 210 in the vertical direction VD. For example, metal patterns 331 to 334 may correspond to the first node SOC_U0 to the fourth node SOC_U3, respectively. For example, one of the first node SOC_U0 to the fourth node SOC_U3 may correspond to... Figure 5 or Figure 8 The first terminal is SOC_U.

[0102] Figure 16 This is the layout 30b of the third metal layer LM2 in an exemplary embodiment of the present invention.

[0103] refer to Figure 16 Layout 30b corresponds to Figure 15A modified example of layout 30a is provided, and repeated descriptions are omitted. The third metal layer LM2 may include metal patterns 311, 312a to 316a, 321a to 324a, 326a, 331a, 333a, and 335 extending in the first horizontal direction HD1. Metal patterns 311 and 315a may be disposed over the main region MR, cache region CR, and page buffer decoder 250 by intersecting the main region MR, cache region CR, and page buffer decoder 250. For example, the internal power supply voltage IVC and the ground voltage GND may be applied to metal patterns 311 and 315a, respectively.

[0104] Metal patterns 321a to 324a can be positioned on the vertical direction VD above the low-voltage region LV, and can respectively correspond to, for example, the first readout node SO0 to the fourth readout node SO3. Metal patterns 321a and 322a can be positioned on a line on the first horizontal direction HD1, while metal patterns 323a and 324a can be positioned on a line on the first horizontal direction HD1. Metal pattern 326a can be positioned on the vertical direction VD above the main region MR, and for example, ground voltage GND can be applied to metal pattern 326a. Metal pattern 335 can be positioned on the vertical direction VD above the main region MR, for example, the first page buffer driver signal PBDRV can be applied to metal pattern 335, and metal pattern 335 can be connected to the first column driver. Metal pattern 316a can be positioned on the vertical direction VD above the cache region CR and the page buffer decoder 250, for example, the second page buffer driver signal PBDRVa can be applied to metal pattern 316a, and metal pattern 316a can be connected to the second column driver. Metal patterns 331a and 333a can be positioned above the high-voltage region HV in the vertical direction VD. For example, metal pattern 331a can correspond to the first node SOC_U0 and the second node SOC_U1, while metal pattern 333a can correspond to the third node SOC_U2 and the fourth node SOC_U3.

[0105] Figure 17 This is the layout 30c of the third metal layer LM2 in an exemplary embodiment of the present invention.

[0106] refer to Figure 17 Layout 30c corresponds to Figure 16A modified example of layout 30b is provided, and repeated descriptions are omitted. The third metal layer LM2 may include metal patterns 311, 312a to 314a, 315b, 316a, 321a to 324a, 326b, 327a, and 331b to 334b ​​extending in the first horizontal direction HD1. Metal pattern 315b may be disposed above the cache region CR and page buffer decoder 250 in the vertical direction VD, and for example, ground voltage GND may be applied to metal pattern 315b. Metal patterns 326b and 327a may be disposed above the low voltage region LV in the vertical direction VD, and for example, ground voltage GND and internal power supply voltage IVC may be applied to metal patterns 326b and 327a, respectively. Metal patterns 331b to 334b ​​may be disposed above the high voltage region HV in the vertical direction VD, and may correspond to, for example, the first node SOC_U0 to the fourth node SOC_U3, respectively.

[0107] Figure 18 This is a top view of a page buffer circuit 40 according to an exemplary embodiment of the present invention.

[0108] refer to Figure 18 The page buffer circuit 40 may include a lower metal layer 410 comprising lower metal patterns 411a, 411b, 412, 413a, 413b, 414, 415a, 415b, 416, 417a, 417b, and 418, an upper metal layer 420 comprising upper metal patterns 421 to 429, and a plurality of active regions 430. For example, the plurality of active regions 430 may include source / drain regions of transistors included in the page buffer cell. Figure 18 As shown, the spacing between the lower metal patterns is smaller than the spacing between the upper metal patterns. For example, according to an exemplary embodiment, the distance between adjacent patterns of the lower metal patterns is smaller than the distance between adjacent patterns of the upper metal patterns.

[0109] Lower metal patterns 411a to 418 can be disposed above multiple active regions 430 in the vertical direction VD and can extend in the first horizontal direction HD1. For example, lower metal patterns 412, 414, 416, and 418 can correspond to first readout nodes SO0 to fourth readout nodes SO3, respectively. Upper metal patterns 421 to 429 can be disposed above the lower metal layer 410 in the vertical direction VD and can extend in the first horizontal direction HD1. For example, upper metal patterns 422, 424, 426, and 428 can be connected to lower metal patterns 412, 414, 416, and 418 via contacts CT, respectively. Therefore, upper metal patterns 422, 424, 426, and 428 can correspond to first readout nodes SO0 to fourth readout nodes SO3, respectively.

[0110] For example, an internal power supply voltage or ground voltage can be applied to the lower metal patterns 411a and 411b on both sides of the lower metal pattern 412 corresponding to the first readout node SO0. Therefore, the lower metal patterns 411a and 411b can be used as shielding lines for the lower metal pattern 412. Similarly, the lower metal patterns 413a and 413b can be used as shielding lines for the lower metal pattern 414, the lower metal patterns 415a and 415b can be used as shielding lines for the lower metal pattern 416, and the lower metal patterns 417a and 417b can be used as shielding lines for the lower metal pattern 418. Furthermore, for example, an internal power supply voltage or ground voltage can be applied to the upper metal patterns 421, 423, 425, and 427. Therefore, the upper metal patterns 421, 423, 425, and 427 can be used as shielding lines for the upper metal patterns 422, 424, 426, and 428, respectively.

[0111] Figure 19 This is a layout 50a of the first metal layer LM0 and the third metal layer LM2 according to an exemplary embodiment of the present invention.

[0112] refer to Figure 19 The first metal layer LM0 and the third metal layer LM2 can extend in the first horizontal direction HD1, and the third metal layer LM2 can be disposed above the first metal layer LM0 in the vertical direction VD, and can be connected to the first metal layer LM0 via a contact CT. The third metal layer LM2 may include first readout node patterns SOa to fourth readout node patterns SOd and first internal signal patterns ISa to fourth internal signal patterns ISd. For example, signals applied to the readout latch can be applied to the first internal signal patterns ISa to fourth internal signal patterns ISd respectively. The first readout node patterns SOa to fourth readout node patterns SOd can be non-adjacent to each other in the second horizontal direction HD2. For example, the first readout node patterns SOa to fourth readout node patterns SOd and the first internal signal patterns ISa to fourth internal signal patterns ISd can be alternately arranged in the second horizontal direction HD2.

[0113] The patterns on multiple tracks (e.g., tracks one through six) of the third metal layer LM2 will be described below. For example, a first internal signal pattern ISa may be disposed on the first track, a first readout node pattern SOa and a second readout node pattern SOb may be disposed on the second track, a second internal signal pattern ISb may be disposed on the third track, a third internal signal pattern ISc may be disposed on the fourth track, a third readout node pattern SOc and a fourth readout node pattern SOd may be disposed on the fifth track, and a fourth internal signal pattern ISd may be disposed on the sixth track.

[0114] Figure 20This is a layout 50b of the first metal layer LM0 and the third metal layer LM2 according to an exemplary embodiment of the present invention.

[0115] refer to Figure 20 Layout 50b corresponds to Figure 19 A modified example of layout 50a is provided, and repeated descriptions are omitted. The third metal layer LM2 may also include metal patterns 511 and 512 to which a ground voltage GND or an internal power supply voltage IVC is applied, respectively. Metal patterns 511 and 512 may be used as shielding lines for the first readout node patterns SOa to the fourth readout node patterns SOd. For example, metal pattern 511 may include vertical patterns on the first, third, fourth, and sixth tracks and horizontal patterns connecting the vertical patterns, and may be used as shielding lines for the first readout node patterns SOa and the third readout node pattern SOc. For example, metal pattern 512 may include vertical patterns on the first, third, fourth, and sixth tracks and horizontal patterns connecting the vertical patterns, and may be used as shielding lines for the second readout node patterns SOb and the fourth readout node pattern SOd.

[0116] Figure 21 This is a layout 50c of the first metal layer LM0 and the third metal layer LM2 according to an exemplary embodiment of the present invention. (See reference...) Figure 21 Layout 50c corresponds to Figure 20 A modified example of layout 50b is provided, and repeated descriptions are omitted. The third metal layer LM2 may also include metal patterns 513 and 514 to which a ground voltage GND or an internal power supply voltage IVC is applied, respectively. Metal patterns 513 and 514 may be used as shielding lines for the first readout node patterns SOa to the fourth readout node patterns SOd. Furthermore, metal pattern 513 may also be used as shielding lines for the first internal signal patterns ISa to the fourth internal signal patterns ISd.

[0117] Figure 22 This is a layout 50d of the first metal layer LM0 and the third metal layer LM2 according to an exemplary embodiment of the present invention.

[0118] refer to Figure 22 Layout 50d corresponds to Figure 19A modified example of layout 50a is provided, and repeated descriptions are omitted. The third metal layer LM2 may include a first readout node pattern SOa and a second readout node pattern SOb, as well as first internal signal patterns ISa to fourth internal signal patterns ISd. The first readout node pattern SOa and the second readout node pattern SOb, as well as the first internal signal patterns ISa to fourth internal signal patterns ISd, may be alternately arranged. In the following, the patterns on multiple tracks of the third metal layer LM2 will be described. For example, the first internal signal pattern ISa may be arranged on the first track, the first readout node pattern SOa may be arranged on the second track, the second internal signal pattern ISb may be arranged on the second and third tracks, the third internal signal pattern ISc may be arranged on the fourth track, the second readout node pattern SOb may be arranged on the fifth track, and the fourth internal signal pattern ISd may be arranged on the sixth track.

[0119] Figure 23 This is a circuit diagram of a page buffer "PB" according to an exemplary embodiment of the present invention.

[0120] refer to Figure 23 "Page buffer PB" corresponds to Figure 5 The example shown illustrates a modified page buffer PB, and the above description of the page buffer PB can also be applied to the example embodiments. When compared with the page buffer PB, the page buffer PB may also include a dynamic latch DL. Furthermore, in some embodiments, such as... Figure 8 As shown, the page buffer "PB" may include a transfer transistor "TR", instead of the first transfer transistor TR and the second transfer transistor TR'.

[0121] Dynamic latch D1 may include transistors NM11, NM12, and NM13. Transistor NM11 may be positioned between the read node SO and the dynamic node D, transistor NM12 may be positioned between the dynamic node D and the ground terminal, and transistor NM13 may be positioned between the S-LATCH SL and the gate of transistor NM12. Transistor NM11 may be driven by the monitoring signal MON_D, while transistor NM13 may be driven by the set signal SET_D.

[0122] Figure 24 This is a circuit diagram of a page buffer PB”_1 according to an exemplary embodiment of the present invention.

[0123] refer to Figure 24 Page buffer PB_1 corresponds to Figure 23The example shown is a modified version of the page buffer "PB", and the above description of the page buffer "PB" can also be applied to the example embodiment. The page buffer "PB"_1 may include a dynamic latch D1', and the dynamic latch D1' may include transistors NM11, NM12, and NM13'. In this case, transistor NM13' may be disposed between the read node SO and the gate of transistor NM12.

[0124] Figure 25 This is the layout 60 of the third metal layer LM2 in an exemplary embodiment of the present invention.

[0125] refer to Figure 25 The first page buffer unit 610 to the fourth page buffer unit 640 can be disposed on the second horizontal direction HD2, and for example, each of the first page buffer unit 610 to the fourth page buffer unit 640 can correspond to Figure 23 Page Buffer Unit (PBU) or Figure 24 The page buffer unit PBU. The third metal layer LM2 may include metal patterns 611, 612, 613, 614, 621, 622, 623, 624, 631, 632, 633, 634 and 635, and may be disposed above the first page buffer unit 610 to the fourth page buffer unit 640 in the vertical direction VD.

[0126] Metal patterns 611 to 614 can correspond to the first read nodes SO0 to the fourth read nodes SO3, respectively, and metal patterns 621 to 624 can correspond to the first dynamic nodes D_0 to the fourth dynamic nodes D_3, respectively. In this case, the first read node SO0 and the first dynamic node D_0 can be connected to the transistors included in the first page buffer unit 610, for example, connected to... Figure 23 or Figure 24 The transistor NM11. Similarly, the second read node SO1 and the second dynamic node D_1 can be connected to the transistor included in the second page buffer unit 620, the third read node SO2 and the third dynamic node D_2 can be connected to the transistor included in the third page buffer unit 630, and the fourth read node SO3 and the fourth dynamic node D_3 can be connected to the transistor included in the fourth page buffer unit 640.

[0127] For example, metal patterns 611 and 621 can be arranged in a single line along the first horizontal direction HD1, metal patterns 612 and 622 can be arranged in a single line along the first horizontal direction HD1, metal patterns 613 and 623 can be arranged in a single line along the first horizontal direction HD1, and metal patterns 614 and 624 can be arranged in a single line along the first horizontal direction HD1. An internal power supply voltage IVC can be applied to metal patterns 631 and 634, while a ground voltage GND can be applied to metal patterns 632 and 635. A first page buffer drive signal PBDRV can be applied to metal pattern 633, and metal pattern 633 can be connected to, for example, a column driver.

[0128] Figure 26 This is a layout 60a of the third metal layer LM2 in an exemplary embodiment of the present invention.

[0129] refer to Figure 26 The first page buffer unit 610a to the fourth page buffer unit 640a can be disposed on the second horizontal direction HD2, and for example, each of the first page buffer unit 610a to the fourth page buffer unit 640a can correspond to Figure 23 Page Buffer Unit (PBU) or Figure 24 The page buffer unit PBU_1. The third metal layer LM2 may include metal patterns 611a, 612a, 613a, 614a, 621a, 622a, 623a, 624a, 631a, 632a, 633a and 634a, and may be disposed above the first page buffer unit 610a to the fourth page buffer unit 640a in the vertical direction VD.

[0130] Metal patterns 611a to 614a can correspond to the first readout nodes SO0 to the fourth readout nodes SO3, respectively, and metal patterns 621a to 624a can correspond to the first dynamic nodes D_0 to the fourth dynamic nodes D_3, respectively. For example, metal patterns 611a, 612a, 621a, and 622a can be arranged in a line along the first horizontal direction HD1, while metal patterns 613a, 614a, 623a, and 624a can be arranged in a line along the first horizontal direction HD1. An internal power supply voltage IVC can be applied to metal patterns 631a and 634a, while a ground voltage GND can be applied to metal pattern 632a. A first page buffer drive signal PBDRV can be applied to metal pattern 633a, and metal pattern 633a can be connected to, for example, a column driver.

[0131] Figure 27 This is the layout 60b of the third metal layer LM2 in an exemplary embodiment of the present invention.

[0132] refer to Figure 27 The first page buffer unit 610b to the fourth page buffer unit 640b can be disposed on the second horizontal direction HD2, and for example, each of the first page buffer unit 610b to the fourth page buffer unit 640b can correspond to Figure 23 Page Buffer Unit (PBU) or Figure 24 The page buffer unit PBU_1. The third metal layer LM2 may include metal patterns 611b, 612b, 613b, 614b, 621b, 622b, 623b, 624b, 631b, 632b, 633b, 634b and 635b, and may be disposed above the first page buffer unit 610b to the fourth page buffer unit 640b in the vertical direction VD.

[0133] Metal patterns 611b to 614b can correspond to the first readout nodes SO0 to the fourth readout nodes SO3, respectively, and metal patterns 621b to 624b can correspond to the first dynamic nodes D_0 to the fourth dynamic nodes D_3, respectively. For example, metal patterns 611b and 621b can be arranged in a line along the first horizontal direction HD1, metal patterns 612b and 622b can be arranged in a line along the first horizontal direction HD1, metal patterns 613b and 623b can be arranged in a line along the first horizontal direction HD1, and metal patterns 614b and 624b can be arranged in a line along the first horizontal direction HD1. The internal power supply voltage IVC can be applied to metal patterns 631b and 634b, and the ground voltage GND can be applied to metal patterns 632b and 635b. The first page buffer drive signal PBDRV can be applied to metal pattern 633b, and metal pattern 633b can be connected to, for example, a column driver.

[0134] Figure 28 This is a layout 60c of the third metal layer LM2 in an exemplary embodiment of the present invention.

[0135] refer to Figure 28 The first page buffer unit 610c to the fourth page buffer unit 640c can be disposed on the second horizontal direction HD2, and for example, each of the first page buffer unit 610c to the fourth page buffer unit 640c can correspond to Figure 23 Page Buffer Unit (PBU) or Figure 24 The page buffer unit PBU”_1. The third metal layer LM2 may include metal patterns 611a to 614a, 621c to 624c and 631a to 634a, and may be disposed above the first page buffer unit 610c to the fourth page buffer unit 640c in the vertical direction VD.

[0136] Metal patterns 611a to 614a can correspond to the first readout nodes SO0 to the fourth readout nodes SO3, respectively, and metal patterns 621c to 624c can correspond to the first dynamic nodes D_0 to the fourth dynamic nodes D_3, respectively. For example, metal patterns 611a, 612a, 621c, and 622c can be arranged in a line along the first horizontal direction HD1, while metal patterns 613a, 614a, 623c, and 624c can be arranged in a line along the first horizontal direction HD1. An internal power supply voltage IVC can be applied to metal patterns 631a and 634a, while a ground voltage GND can be applied to metal pattern 632a. A first page buffer drive signal PBDRV can be applied to metal pattern 633a, and metal pattern 633a can be connected to, for example, a column driver.

[0137] Figure 29 This is a cross-sectional view of a memory device 900 according to an exemplary embodiment of the present invention.

[0138] refer to Figure 29 The memory device 900 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then connecting the upper and lower chips by bonding. For example, the bonding method may include a method of electrically connecting bonding metals formed on the topmost metal layer of the upper chip and bonding metals formed on the topmost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten. (Reference) Figures 1 to 27 The embodiments shown can be implemented in memory device 900, for example, as referenced above. Figures 1 to 27 The page buffer circuit described can be set in the peripheral circuit area PERI.

[0139] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device 900 may include an external pad bonding region (PA), a word line bonding region (WLBA), and a bit line bonding region (BLBA). The peripheral circuit region (PERI) may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c respectively connected to the plurality of circuit elements 720a, 720b, and 720c, and second metal layers 740a, 740b, and 740c respectively formed on the first metal layers 730a, 730b, and 730c. In an example embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten, which has relatively high resistance, while the second metal layers 740a, 740b, and 740c may be formed of copper, which has relatively low resistance.

[0140] According to the example embodiment, although only the first metal layers 730a, 730b, and 730c and the second metal layers 740a, 740b, and 740c are shown and described, the example embodiment is not limited thereto, and one or more metal layers may also be formed on the second metal layers 740a, 740b, and 740c. At least a portion of the one or more metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of aluminum or the like, which has a lower resistivity than Cu, which forms the second metal layers 740a, 740b, and 740c.

[0141] An interlayer insulating layer 715 may be disposed on a first substrate 710 and cover a plurality of circuit elements 720a, 720b and 720c, a first metal layer 730a, 730b and 730c and a second metal layer 740a, 740b and 740c, and may include an insulating material such as silicon oxide or silicon nitride.

[0142] Lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding region (WLBA). In the WLBA, the lower bonding metals 771b and 772b in the peripheral circuit region (PERI) can be electrically connected to the upper bonding metals 871b and 872b by bonding, and both the lower and upper bonding metals 771b and 772b can be formed of aluminum, copper, tungsten, etc. The upper bonding metals 871b and 872b in the cell region (CELL) can be referred to as first metal pads, while the lower bonding metals 771b and 772b in the peripheral circuit region (PERI) can be referred to as second metal pads.

[0143] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 810 and a common source line 820. On the second substrate 810, multiple word lines 831 to 838 (i.e., 830) may be stacked in a direction perpendicular to the upper surface of the second substrate 810 (vertical direction VD). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 830, respectively, and the multiple word lines 830 may be disposed between the at least one string select line and the at least one ground select line.

[0144] In the bit line bonding area (BLBA), the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 810 and pass through multiple word lines 830, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In an example embodiment, the bit line 860c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810.

[0145] exist Figure 29 In the example embodiment shown, the region where the channel structure CH, bit line 860c, etc., are provided can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 860c can be electrically connected to circuit element 720c, which provides page buffer 893 in peripheral circuit region PERI. For example, bit line 860c can be connected to upper bonding metals 871c and 872c in cell region CELL, and upper bonding metals 871c and 872c can be connected to lower bonding metals 771c and 772c of the circuit element 720c connected to page buffer 893.

[0146] In the word line bonding area (WLBA), multiple word lines 830 can extend in a second horizontal direction HD2 parallel to the upper surface of the second substrate 810 and can be connected to multiple cell contact plugs 841 to 847 (i.e., 840). The multiple word lines 830 and the multiple cell contact plugs 840 can be connected to each other in pads formed by at least a portion of the multiple word lines 830 extending at different lengths in the second horizontal direction HD2. A first metal layer 850b and a second metal layer 860b can be sequentially connected to the upper portion of the multiple cell contact plugs 840 connected to the multiple word lines 830. The multiple cell contact plugs 840 can be connected to the peripheral circuit region PERI via upper bonding metals 871b and 872b of the cell region CELL in the word line bonding area (WLBA) and lower bonding metals 771b and 772b of the peripheral circuit region PERI.

[0147] Multiple unit contact plugs 840 may be electrically connected to circuit element 720b providing line decoder 894 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 720b providing line decoder 894 may differ from the operating voltage of circuit element 720c providing page buffer 893. For example, the operating voltage of circuit element 720c providing page buffer 893 may be greater than the operating voltage of circuit element 720b providing line decoder 894.

[0148] A common source line contact plug 880 can be disposed in the external pad bonding region PA. The common source line contact plug 880 can be formed of a conductive material (such as a metal, metal compound, or polysilicon) and can be electrically connected to the common source line 820. A first metal layer 850a and a second metal layer 860a can be sequentially stacked on top of the common source line contact plug 880. For example, the region where the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed can be defined as the external pad bonding region PA.

[0149] Input-output pads 705 and 805 can be set in the external pad bonding area PA. (See reference) Figure 29 A lower insulating film 701 covering the lower surface of the first substrate 710 may be formed below the first substrate 710, and a first input-output pad 705 may be formed on the lower insulating film 701. The first input-output pad 705 can be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI via a first input-output contact plug 703, and can be separated from the first substrate 710 via the lower insulating film 701. Furthermore, a side insulating film may be disposed between the first input-output contact plug 703 and the first substrate 710 to electrically separate the first input-output contact plug 703 from the first substrate 710.

[0150] refer to Figure 29 An upper insulating film 801 covering the upper surface of the second substrate 810 can be formed on the second substrate 810, and a second input-output pad 805 can be disposed on the upper insulating film 801. The second input-output pad 805 can be connected to at least one of a plurality of circuit elements 720a, 720b and 720c disposed in the peripheral circuit region PERI via a second input-output contact plug 803.

[0151] According to an embodiment, the second substrate 810 and the common source line 820 may not be located in the region where the second input-output contact plug 803 is disposed. Furthermore, the second input-output pad 805 may not overlap with the word line 830 in the vertical direction VD. (See reference...) Figure 29The second input-output contact plug 803 can be separated from the second substrate 810 in a direction parallel to the upper surface of the second substrate 810, and can pass through the interlayer insulating layer 815 of the cell region to connect to the second input-output pad 805.

[0152] According to embodiments, the first input-output pad 705 and the second input-output pad 805 can be selectively formed. For example, the memory device 900 may include only the first input-output pad 705 disposed on the first substrate 710 or the second input-output pad 805 disposed on the second substrate 810. Alternatively, the memory device 900 may include the first input-output pad 705 and the second input-output pad 805.

[0153] In each of the external pad bonding region PA and bit line bonding region BLBA, which are respectively included in the cell region CELL and the peripheral circuit region PERI, the metal pattern in the uppermost metal layer can be set as a virtual pattern, or the uppermost metal layer can be absent.

[0154] In the external pad bonding region PA, the memory device 900 may include a lower metal pattern 773a corresponding to an upper metal pattern 872a formed in the uppermost metal layer of the cell region CELL, and having the same shape as the upper metal pattern 872a in the uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern may be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same shape as the lower metal pattern in the peripheral circuit region PERI.

[0155] The lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 871b and 872b of the cell region CELL via Cu-Cu bonding.

[0156] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 892, corresponding to the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 752 of the peripheral circuit region PERI, can be formed in the uppermost metal layer of the cell region CELL. The contacts may not be formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell region CELL.

[0157] Figure 30 This is a block diagram of an example of a solid-state drive (SSD) system 1000 that applies some example embodiments of a memory device according to the concept of the present invention.

[0158] refer to Figure 30 SSD 1000 may include host 1100 and SSD 1200. SSD 1200 sends signals to and receives signals from host 1100 via a signal connector and receives power via a power connector. SSD 1200 may include SSD controller 1210, auxiliary power supply 1220, and memory devices MEM 1230, 1240, and 1250. Memory devices 1230, 1240, and 1250 may be vertically stacked NAND flash memory devices and communicate with the SSD controller via channels Ch1, Ch2...Chn. Here, SSD 1200 can use the above reference... Figures 1 to 29 The example embodiments described are used for implementation.

[0159] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A memory device comprising: an array of memory cells including a plurality of memory cells connected to a plurality of bit lines extending in a first horizontal direction, respectively; and a page buffer circuit connected to the array of memory cells through the plurality of bit lines, the page buffer circuit being disposed in a page buffer region including a main region and a cache region arranged along the first horizontal direction, wherein the page buffer circuit includes: a first page buffer cell and a second page buffer cell arranged in the main region along a second horizontal direction, wherein the first page buffer cell includes: a first bit line selection transistor connected to a first bit line; a first sense node connected to the first bit line selection transistor; and a first pass transistor connected to the first sense node, wherein the second page buffer cell includes: a second bit line selection transistor connected to a second bit line; a second sense node connected to the second bit line selection transistor; and a second pass transistor connected to the second sense node, wherein the first sense node includes: a first lower metal pattern disposed in a lower metal layer and electrically connected to the first pass transistor; and a first upper metal pattern disposed in an upper metal layer disposed above the lower metal layer along a vertical direction and electrically connected to the first lower metal pattern, and wherein the second sense node includes: a second lower metal pattern disposed in the lower metal layer and electrically connected to the second pass transistor; and a second upper metal pattern disposed in the upper metal layer electrically connected to the second lower metal pattern and not adjacent to the first upper metal pattern in the second horizontal direction. 2.The memory device of claim 1, wherein the page buffer circuit further includes a first cache latch and a second cache latch disposed in the cache region, and wherein the first cache latch and the second cache latch are adjacent to each other in the second horizontal direction and connected to the first page buffer cell and the second page buffer cell, respectively, and adjacent to each other in the second horizontal direction. 3.The memory device of claim 1, wherein the first lower metal pattern and the second lower metal pattern extend in the same direction as the first upper metal pattern and the second upper metal pattern. 4.The memory device of claim 3, wherein the first bit line and the second bit line extend in the same direction as the first lower metal pattern and the second lower metal pattern and the first upper metal pattern and the second upper metal pattern. 5.The memory device of claim 1, wherein the upper metal layer includes: a first power pattern disposed above the first page buffer cell; and a second power pattern disposed above the second page buffer cell. the first upper metal pattern disposed above the first page buffer unit and adjacent to the first power pattern in the second horizontal direction; the second upper metal pattern disposed above the second page buffer unit; and a second power pattern disposed above the second page buffer unit and adjacent to the second upper metal pattern in the second horizontal direction.

6. The memory device of claim 1, wherein the upper metal layer comprises: an internal signal pattern disposed above the first page buffer unit; a first power pattern disposed above the first page buffer unit and adjacent to the internal signal pattern in the second horizontal direction; and the first upper metal pattern and the second upper metal pattern disposed above the second page buffer unit.

7. The memory device of claim 1, wherein the upper metal layer comprises: a first power pattern disposed above the first page buffer unit; a second power pattern disposed above the second page buffer unit; and the first upper metal pattern and the second upper metal pattern disposed between the first power pattern and the second power pattern in the first horizontal direction.

8. The memory device of claim 1, wherein the upper metal layer comprises: an internal signal pattern disposed above the first page buffer unit; the first upper metal pattern and the second upper metal pattern disposed above the second page buffer unit and arranged in the first horizontal direction; and a power pattern disposed between the internal signal pattern and the first upper metal pattern and the second upper metal pattern.

9. The memory device of claim 1, wherein the upper metal layer comprises: a first power pattern; a first upper metal pattern disposed adjacent to the first power pattern in the second horizontal direction; a second power pattern disposed adjacent to the first upper metal pattern in the second horizontal direction; the second upper metal pattern disposed adjacent to the second power pattern in the second horizontal direction; and a third power pattern disposed adjacent to the second upper metal pattern in the second horizontal direction, and wherein the first power pattern to the third power pattern and the first upper metal pattern and the second upper metal pattern extend in the first horizontal direction.

10. The memory device of claim 1, wherein the upper metal layer comprises: a first internal signal pattern on a first track; the first upper metal pattern on a second track; a second internal signal pattern on a third track; a third internal signal pattern on a fourth track; and the second upper metal pattern on a fifth track, and wherein the first internal signal pattern, the second internal signal pattern, and the third internal signal pattern and the first upper metal pattern and the second upper metal pattern extend in the first horizontal direction.

11. The memory device of claim 10, wherein the upper metal layer further comprises: a first power pattern on the first track; and a second power pattern on the second track. ​ ​ ​ a second power pattern on the third track, and wherein the first power pattern, the first upper metal pattern, and the second power pattern are adjacent to each other in the second horizontal direction.

12. The memory device of claim 1, wherein the first lower metal pattern and the second lower metal pattern are not adjacent to each other in the second horizontal direction.

13. The memory device of claim 1, wherein the lower metal layer includes: a first power pattern; the first lower metal pattern disposed adjacent to the first power pattern in the second horizontal direction; a second power pattern disposed adjacent to the first lower metal pattern in the second horizontal direction; and the second lower metal pattern disposed adjacent to the second power pattern in the second horizontal direction, and wherein the first power pattern and the second power pattern and the first lower metal pattern and the second lower metal pattern extend in the first horizontal direction.

14. The memory device of claim 1, wherein the first page buffer unit includes a first dynamic latch connected to the first sense node, the first dynamic latch including a first dynamic node, wherein the second page buffer unit includes a second dynamic latch connected to the second sense node, the second dynamic latch including a second dynamic node, wherein the first dynamic node includes: a third lower metal pattern disposed in the lower metal layer; and a third upper metal pattern disposed in the upper metal layer and electrically connected to the third lower metal pattern, and wherein the second dynamic node includes: a fourth lower metal pattern disposed in the lower metal layer; and a fourth upper metal pattern disposed in the upper metal layer and electrically connected to the fourth lower metal pattern.

15. The memory device of claim 14, wherein the first upper metal pattern and the third upper metal pattern are arranged along the first horizontal direction, the second upper metal pattern and the fourth upper metal pattern are arranged along the first horizontal direction, and the third upper metal pattern and the fourth upper metal pattern are not adjacent to each other in the second horizontal direction.

16. The memory device of claim 14, wherein the first upper metal pattern to the fourth upper metal pattern are arranged along the first horizontal direction.

17. The memory device of claim 14, wherein the first upper metal pattern and the third upper metal pattern are arranged along the first horizontal direction, the second upper metal pattern and the fourth upper metal pattern are arranged along the first horizontal direction, and the third upper metal pattern and the fourth upper metal pattern are adjacent to each other in the second horizontal direction.

18. A memory device, comprising: a first semiconductor layer including a plurality of memory cells connected to a plurality of bit lines extending in a first horizontal direction, respectively; and a second semiconductor layer disposed in a vertical direction perpendicular to the first semiconductor layer, the second semiconductor layer including a plurality of page buffers, wherein the plurality of page buffers includes a first page buffer unit and a second page buffer unit, wherein the first page buffer unit includes: a first bit line selection transistor connected to a first bit line; a first readout node connected to the first bit line selection transistor; and a first pass transistor connected to the first readout node, wherein the second page buffer unit includes: a second bit line selection transistor connected to a second bit line; a second readout node connected to the second bit line selection transistor; and a second pass transistor connected to the second readout node, wherein the first readout node includes: a first lower metal pattern disposed in a lower metal layer and electrically connected to the first pass transistor; and a first upper metal pattern disposed in an upper metal layer disposed above the lower metal layer in the vertical direction and electrically connected to the first lower metal pattern, wherein the second readout node includes: a second lower metal pattern disposed in the lower metal layer and electrically connected to the second pass transistor; and a second upper metal pattern disposed in the upper metal layer, wherein the second page buffer unit is disposed adjacent to the first page buffer unit in a second horizontal direction, and wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.

19. The memory device of claim 18, wherein the plurality of page buffers includes: a plurality of first page buffer units disposed in a main region of the second semiconductor layer in the first horizontal direction; a plurality of second page buffer units disposed in the main region of the second semiconductor layer in the first horizontal direction and adjacent to the first page buffer units in the second horizontal direction; a plurality of first cache latches disposed in a cache region of the second semiconductor layer in the first horizontal direction and respectively corresponding to the first page buffer units; and a plurality of second cache latches disposed in the cache region of the second semiconductor layer in the first horizontal direction, adjacent to the first cache latches in the second horizontal direction, and respectively corresponding to the second page buffer units, and wherein the main region and the cache region are adjacent to each other in the first horizontal direction.

20. A memory device, comprising: a memory cell region including a plurality of memory cells and a first metal pad; and a peripheral circuit region including a second metal pad and connected to the memory cell region in a vertical direction through the first metal pad and the second metal pad, wherein the peripheral circuit region further includes a plurality of page buffers, wherein the plurality of page buffers includes a first page buffer unit and a second page buffer unit, wherein the first page buffer unit includes: a first bit line selection transistor connected to a first bit line; a first readout node connected to the first bit line selection transistor; and a first pass transistor connected to the first readout node, wherein the second page buffer unit includes: a second bit line selection transistor connected to a second bit line; a second readout node connected to the second bit line selection transistor; and a second pass transistor connected to the second readout node, wherein the first readout node includes: a first lower metal pattern disposed in a lower metal layer and electrically connected to the first pass transistor; and a first upper metal pattern disposed in an upper metal layer disposed above the lower metal layer in the vertical direction and electrically connected to the first lower metal pattern, wherein the second readout node includes: a second lower metal pattern disposed in the lower metal layer and electrically connected to the second pass transistor; and a second upper metal pattern disposed in the upper metal layer, wherein the second page buffer unit is disposed adjacent to the first page buffer unit in a second horizontal direction, and wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction. a second readout node connected to the second bit line selection transistor; and a second pass transistor connected to the second readout node, wherein the first readout node includes: a first lower metal pattern disposed in a lower metal layer and electrically connected to the first pass transistor; and a first upper metal pattern disposed in an upper metal layer disposed above the lower metal layer in a vertical direction and electrically connected to the first lower metal pattern, wherein the second readout node includes: a second lower metal pattern disposed in the lower metal layer and electrically connected to the second pass transistor; and a second upper metal pattern disposed in the upper metal layer, wherein the second page buffer unit is disposed adjacent to the first page buffer unit in a second horizontal direction, and wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.

Images