Reduced resistivity of access lines in memory arrays

Abstract

This application is directed to reduced resistivity of access lines in a memory array. A first metal layer can be formed over a via configured to couple an access line of a memory array with a corresponding driver. The first metal layer can be oxidized, and subsequently a second metal layer can be formed over the oxidized first metal layer. One or more access lines of the memory device can be formed from the second metal layer, the oxidized first metal layer, or both.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 993,695, filed August 14, 2020, entitled “Reduced Resistivity for Access Lines in a Memory Array”, by Wei et al., which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field focuses on reducing the resistivity of access lines in memory arrays. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of them. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM, on the other hand, may lose its stored state when disconnected from external power. Summary of the Invention

[0006] Describe a method. The method may include forming a via extending through one or more materials of a memory device. The method may include forming a first metal layer over the via. The method may include oxidizing the first metal layer. The method may include forming a second metal layer over the first metal layer after oxidizing the first metal layer, wherein the second metal layer serves one or more access lines of the memory device.

[0007] Describe a device. The device may include: a collection of memory cells coupled to access lines extending within the device in a first direction, the access lines comprising metal; vias extending through one or more materials within the device in a second direction, the second direction being different from the first direction; and metal oxide lines extending between the metal and the vias in the first direction.

[0008] Describe a device. The device may include: access lines for a collection of memory cells, wherein the access lines include metal wires extending within the device in a first direction; vias extending in a second direction other than the first direction; and drivers for the access lines, wherein: the drivers are coupled to the access lines via the vias; and a metal oxide is inserted between the metal wires and the vias. Attached Figure Description

[0009] Figure 1 Examples of memory devices that support reduced resistivity of access lines in a memory array, according to examples disclosed herein, are shown.

[0010] Figure 2 An example of a memory array that supports reduced resistivity of access lines in a memory array, according to examples disclosed herein.

[0011] Figure 3 Examples of memory structures that reduce the resistivity of access lines in a memory array, based on examples disclosed herein, are shown.

[0012] Figure 4 Examples of memory structures that reduce the resistivity of access lines in a memory array, based on examples disclosed herein, are shown.

[0013] Figure 5 Examples of memory structures that reduce the resistivity of access lines in a memory array, based on examples disclosed herein, are shown.

[0014] Figure 6 and 7 Flowcharts illustrating one or more methods for reducing the resistivity of access lines in a supported memory array, based on examples disclosed herein. Detailed Implementation

[0015] Memory cells in an access (e.g., read or write) memory array may include one or more access lines coupled to the memory cell that apply a non-zero voltage. During operation of the memory array, charge can accumulate within the parasitic capacitance of the memory array (e.g., the parasitic capacitance associated with the access lines of the memory array). In some instances, the accumulated charge can discharge through the accessed memory and cause a current “spiking” (e.g., a relatively high current discharge through the memory cell over a relatively short period). For example, a memory cell may become conductive during access (e.g., when the voltage on the memory cell exceeds a threshold voltage of the memory cell), which can cause the accumulated charge in the memory array to discharge through the selected memory cell. Current spikes can damage the memory cell. For example, a memory cell may degrade or deplete in proportion to the number and magnitude of current spikes experienced by the memory cell over time.

[0016] In some memory arrays, each access line may be coupled to a corresponding driver, which may be configured to bias the access line at a desired voltage. The access line may be coupled to the corresponding driver via one or more vias (or other interconnects), wherein the driver is located outside the memory array (e.g., below). At least in the context of access lines or drivers, the distance of the current path between a memory cell and the driver of an access line coupled to the same memory cell may be referred to as the electrical distance (ED) of the memory cell.

[0017] Memory cells near the access line-via connection point may have a relatively small ED (exposure current) and are referred to as near-memory cells, while memory cells far from the access line-via connection point may have a relatively large ED and are referred to as far-memory cells. In some instances, accessing far-memory cells may require a relatively large drive current due to the relatively high resistance between the driver and the memory cell. In other instances, near-memory cells may experience more severe (e.g., more destructive) current spikes due to the relatively low resistance path between the memory cell and the charge accumulated in parasitic capacitance along the entire length of the access line. Therefore, optimizing the driver current of the access line driver, the resistivity of the access line, or other aspects of the physical or operating parameters of the memory array may involve trade-offs related to the difference in ED between far-memory cells and near-memory cells.

[0018] The techniques and structures described herein can mitigate current spikes and reduce access line resistivity (and thus the difference in ED between distant and near memory cells), as well as other benefits that may be understood by those skilled in the art. A first metal layer may be formed over a stack of one or more materials, wherein vias extend through the stack, and wherein each via is coupled to a corresponding driver. Thus, the first metal layer may be formed above and in contact with the exposed upper surface of each of the vias. The first metal layer may be formed as a relatively thin layer (e.g., as a sheet). The first metal layer may then be oxidized. In some cases, the first metal layer may be oxidized to its entire depth. And in some cases, the vias may be formed of metal, and the upper portion of the vias may also be oxidized. A second metal layer may then be formed over the oxidized first metal layer. The second metal layer may be thicker than the oxidized first metal layer. The oxidized first and second metal layers may be patterned to form an array of access lines, each access line coupled to a corresponding via and thus to a corresponding driver.

[0019] When a metal oxide layer is oxidized (and potentially the upper portion of a via), resistance can be introduced into the signal path between the driver for the access line and the memory cell coupled to the access line, reducing current spikes near the memory cell. Furthermore, forming a second metal layer over the metal oxide layer (e.g., oxidizing the first metal layer) causes a reduction in the resistivity of the second metal layer, and thus a reduction in the resistivity of the resulting access line. This reduces power consumption and also reduces the relative difference in ED between near and far memory cells, which can support optimizations or simplifications to the driver current of the memory array or other operational or physical characteristics of the memory array or a device or system containing the memory array.

[0020] First, as referenced Figure 1 and 2 Features of this disclosure are described in the context of the described apparatus and array. (See references...) Figures 3 to 5 The features of this disclosure are described in the context of the memory structure described herein. These and other features of this disclosure are further illustrated by references to [reference needed]. Figure 6 and 7 A flowchart relating to the reduction of resistivity of access lines in the described memory array is shown and described with reference to the flowchart.

[0021] Figure 1 An example memory device 100 is shown according to the examples disclosed herein. The memory device 100 may also be referred to as an electronic memory device. Figure 1This is an illustrative representation of the various components and features of the memory device 100. Therefore, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships and are not necessarily their actual physical locations within the memory device 100. Furthermore, although... Figure 1 Some of the elements included are labeled with numerical indicators, while other corresponding elements are not labeled, but they are the same or will be understood as similar, in order to increase the visibility and clarity of the depicted features.

[0022] exist Figure 1 In an illustrative example, memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 programmable to store different states. In some instances, each memory cell 105 is programmable to store one of two states identified as logic 0 and logic 1, and thus stores one bit of information. In some instances, memory cells 105 may be configured to store one of more than two logic states, and thus store more than one bit of information.

[0023] 3D memory array 102 may comprise two or more two-dimensional (2D) memory arrays formed on top of each other. Compared to 2D arrays, this increases the number of memory cells that can be placed or generated on a single die or substrate, which in turn can reduce manufacturing costs or improve the performance of the memory device, or both. Memory array 102 may comprise two stacks (hierarchies) of memory cells 105 and can therefore be considered a 3D memory array; however, the number of stacks is not limited to two and may in some cases be one or more more than two. Each stack may be aligned or positioned such that the memory cells 105 in one stack can be aligned (precisely overlapped, or substantially overlapped) with the memory cells in the other stack, thereby forming a memory cell stack 145.

[0024] In some instances, memory cell 105 may be a self-select memory cell, a phase-change memory (PCM) cell, and / or another type of resistance- or threshold-based memory cell. Self-select memory cell 105 may include one or more components of a material (e.g., a chalcogenide material), each acting as both a storage element and a cell selector (selection) element, thereby eliminating the need for a separate cell selector circuit (which does not contribute to storage). Such components may be referred to as storage and selector components (or elements), or self-select memory components (or elements). In contrast, other types of memory cells, such as dynamic random access memory (DRAM) or PCM cells, may each include a separate (dedicated) cell selector element, such as a three-terminal selector element (e.g., a transistor) or a two-terminal selector element (e.g., a diode), to facilitate the selection or non-selection of the memory cell without contributing to the storage of any logical state.

[0025] Memory array 102 may include multiple word lines 110 (e.g., row lines) labeled WL_1 to WL_M for each stack, and multiple bit lines 115 (e.g., column lines) labeled BL_1 to BL_N, where M and N depend on the array size. In some instances, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. In some cases, word lines 110 and bit lines 115 may be generally referred to as access lines because they allow access to memory cells 105. In some instances, word lines 110 may also be referred to as row lines 110, and bit lines 115 may also be referred to as number lines 115 or column lines 115. References to access lines, word lines, and bit lines, etc., may be interchanged without affecting understanding or operation. Activating or selecting a word line 110 or bit line 115 may involve applying a voltage to the corresponding line. Word lines 110 and bit lines 115 may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors or other conductive materials, alloys, compounds or the like.

[0026] Word lines 110 and bit lines 115 may be substantially perpendicular (i.e., orthogonal) to each other or otherwise intersect each other to form a memory cell array. For example... Figure 1 As shown, two memory cells 105 in memory cell stack 145 can share a common conductive line, such as bit line 115. That is, bit line 115 can electronically communicate with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105 in memory cell stack 145. Other configurations are possible; for example, a third stack (not shown) can share access line 110 with either the lower or upper stack shown. Generally, a memory cell 105 can be located at the intersection of two conductive lines, such as word line 110 and bit line 115. This intersection point can be referred to as the address of memory cell 105. A target memory cell 105 can be a memory cell 105 located at the intersection of the energized word line 110 and bit line 115; that is, word line 110 and bit line 115 can be energized to read, write, or otherwise access memory cell 105 at their intersection point. Other memory cells 105 that are electronically communicated with the same word line 110 or bit line 115 (e.g., connected to the word line or bit line) may be referred to as non-target memory cells 105.

[0027] Electrodes may be coupled to memory cell 105 and word line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact to memory cell 105. Electrodes may comprise traces, wires, conductive lines, conductive layers, or the like that provide a conductive path between elements or components of memory device 100. In some instances, memory cell 105 may comprise a plurality of selectable or other memory components (e.g., selectable components and storage components) connected to each other via electrodes and separated from access lines 110, 115. As described above, for selectable memory cell 105, a single component (e.g., a segment or layer of chalcogenide material within memory cell 105) may serve as a storage element (e.g., for storing or facilitating the storage of the state of memory cell 105) and as a selector element (e.g., for selecting or facilitating the selection of memory cell 105).

[0028] The electrodes within the memory cell stack 145 may each have the same material (e.g., carbon) or may have various (different) materials. In some cases, the electrodes may be made of a material different from that of the access lines. In some instances, the electrodes may shield the word line 110, the bit line 115, or another memory component with materials contained in the select or other memory components (e.g., chalcogenide materials) to prevent chemical interactions between the material and the word line 110, the bit line 115, or another memory component.

[0029] Operations such as reading and writing can be performed on memory cell 105 by activating or selecting the corresponding word line 110 or bit line 115 (e.g., by changing their voltage). Access to memory cell 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. This process can be referred to as decoding a row or word line address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate bit line 115. This process can be referred to as decoding a column or bit line address. For example, row decoder 120 and / or column decoder 130 may be instances of decoders implemented using decoder circuitry.

[0030] When accessing memory cell 105 (e.g., in cooperation with memory controller 140, row decoder 120, and / or column decoder 130) to determine the logical state stored in memory cell 105, memory cell 105 may be read (e.g., sensed) by sensing component 125. Sensing component 125 may provide an output signal indicating (e.g., at least in part based on) the logical state stored in memory cell 105 to one or more components (e.g., column decoder 130, input / output component 135, memory controller 140). In some instances, the detected logical state may be provided to a host device (e.g., a device using memory device 100 for data storage, a processor coupled to memory device 100 in an embedded application), where such signaling may be provided directly from input / output component 135 or via memory controller 140.

[0031] Sensing component 125 may include various transistors or amplifiers to detect and amplify differences in signals obtained based on reads from memory cell 105, a process known as latching. The detected logic state of memory cell 105 can then be output as output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120. Those skilled in the art will appreciate that sensing components can be associated with column decoders or row decoders without losing their functional purpose.

[0032] Although the side of memory array 102 is shown for clarity, row decoder 120 and column decoder 130 may, in some cases, be located below memory array 102. Each decoder 120, 130 may include or be coupled to one or more drivers configured to drive access lines 110, 115 to a desired voltage (e.g., to access one or more associated memory cells 105). In some cases, the drivers may be distributed over the entire area under memory array 102. Vias may extend through one or more layers or stacks of memory device 100 to couple a driver to its corresponding access line 110, 115. For example, if access lines 110, 115 are considered to extend in a horizontal direction (e.g., the x-direction or y-direction), then the via may extend in a vertical (z-direction). In some cases, one or more layers between the drivers and access lines may contain metallic wiring, which may be referred to as interconnect layers or collectively as interconnect layers. The driver can be coupled to a corresponding line in the interconnect layer, and the via can extend between the interconnect layer and the layer containing the access line 115.

[0033] As described herein, a portion (e.g., the lower portion) of word line 110 or bit line 115 may include a metal oxide line in contact with a via for word line 110 or bit line 115. The metal oxide line may be conceptualized as a portion of word line 110 or bit line 115 or as separate from word line 110 or bit line 115, and the scope of the claims does not depend on such conceptualization. The upper portion of the via may also be oxidized. As discussed elsewhere, the metal oxide can reduce the severity of current spikes experienced by memory cells coupled to word line 110 or bit line 115. Additionally or alternatively, word line 110 or bit line 115 may have reduced resistivity due to the presence of the metal oxide (e.g., a metal layer formed over the metal oxide and formed therefrom on word line 110 or bit line 115 may have a lower resistivity than such a metal layer formed in the absence of the metal oxide).

[0034] Figure 2 An example of a 3D memory array 200 according to the examples disclosed herein is shown. The memory array 200 may be a reference. Figure 1 An example of a portion of the described memory array 102. The memory array 200 may include a first array or stack 205-a of memory cells positioned above a substrate 204 and a second array or stack 205-b of memory cells positioned above the first array or stack 205-a. While the example of memory array 200 includes two 205-a, 205-b, it should be understood that one stack 205 (e.g., a 2D memory array) or more than two stacks 205 are also possible. Furthermore, although... Figure 2 Some of the components are labeled with numerical indicators, while other corresponding components are not labeled, but they are the same or will be understood to be similar, in order to improve the visibility and clarity of the depicted features.

[0035] The memory array 200 may also include word lines 210 and bit lines 215, which may be references. Figure 1 Examples of word line 110 and bit line 115 described herein. Word line 210 and bit line 215 may have been initially formed (manufactured) from one or more corresponding layers or metals or metal oxides, and may therefore include metallic materials such as tungsten (W), copper (Cu), aluminum (Al), gold (Au), titanium (Ti) or metal alloys.

[0036] In some cases, the resistivity of an access line can be expressed as the resistance per unit length of the access line (e.g., if the cross-sectional area of ​​the access line is constant, then the resistivity can in some cases be expressed in ohm-meters (ohms per meter of length multiplied by the cross-sectional area of ​​the access line, such as in square meters), thus obtaining a fixed resistance per unit length of the access line). Alternatively or concurrently, the resistivity of the access line can be expressed as sheet resistance, which can be a measurement of the resistivity of a sheet comprising a material of uniform thickness or formed of a sheet of material of uniform thickness. In some cases, sheet resistance can be expressed in ohm squares, which may be dimensionally equal to an ohm (e.g., by dividing the resistivity unit ohm-meter by the uniform sheet thickness, such as in meters) but may specifically imply sheet resistance (e.g., rather than the bulk resistance of a conventional resistor).

[0037] The memory cells of the first stack 205-a may include a first electrode 225-a, a memory element 220-a, and a second electrode 225-b. Furthermore, the memory cells of the second stack 205-b may include a first electrode 225-c, a memory element 220-b, and a second electrode 225-d. In some embodiments, the memory cells of the first stack 205-a and the second stack 205-b may have a common conductive line, such that corresponding memory cells of each stack 205-a and 205-b may share a bit line 215 or a word line 210, as referenced. Figure 1 As described. For example, the first electrode 225-c of the second stack 205-b and the second electrode 225-b of the first stack 205-a can be coupled to bit line 215-a, such that bit line 215-a is shared by vertically adjacent memory cells.

[0038] In some cases, the architecture of memory array 200 may be referred to as a cross-point architecture, where memory cells are formed at the topological cross-points between word line 210 and bit line 215, such as... Figure 2 As shown in the diagram, such crossover architectures can provide relatively high-density data storage with lower manufacturing costs compared to at least some other memory architectures. For example, a crossover architecture may have memory cells with a reduced area and thus an increased memory cell density compared to at least some other architectures.

[0039] Although one memory element 220 is shown per memory cell for clarity, the memory cells of the first stack 205-a and the second stack 205-b may each contain one or more memory elements 220 (e.g., elements of memory material configurable to store information), which may or may not be optional memory elements. In some instances, the memory element 220 may, for example, comprise a chalcogenide material or other alloy, which includes selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some embodiments, a chalcogenide material primarily having selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some instances, the SAG alloy may also contain silicon (Si), and such a chalcogenide material may be referred to as a SiSAG alloy. In some other instances, the SAG alloy may also contain indium (In), and such a chalcogenide material may be referred to as an InSAG alloy in some cases. In some instances, chalcogenides may contain additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), which are in atomic or molecular form.

[0040] In some cases, memory element 220 may be contained within a PCM cell. Within the PCM cell, memory element 220 can switch from amorphous to crystalline and vice versa, and thus this state can be written to the memory cell containing memory element 220 by applying a voltage to memory element 220 and thus allowing current to flow through it to heat it above its melting temperature, and then removing the voltage and current according to various timing parameters configured to cause memory element 220 to be in the desired state (e.g., amorphous or crystalline). The heating and quenching of memory element 220 can be achieved by controlling the current flowing through it (which in turn can be achieved by controlling the voltage difference between the corresponding word line 210 and the corresponding bit line 215).

[0041] The memory element 220 in its crystalline state may have atoms arranged in a periodic structure, which can produce relatively low resistance (e.g., in the set state). Conversely, the memory element 220 in its amorphous state may have little or no periodic atomic structure, which can result in relatively high resistance (e.g., in the reset state). The difference in resistance between the amorphous and crystalline states of the memory element 220 can be significant; for example, the material in its amorphous state may have a resistance one or more orders of magnitude greater than that in its crystalline state. In some cases, the amorphous state may have an associated threshold voltage, and current may not flow until it exceeds Vth. Some PCM cells may include one memory element 220 configured to undergo a phase transition and thus act as a storage element, and another memory element 220 configured to act as a diode (e.g., a jump-back diode) and thus as a selection element. The selection element may be configured to remain in an amorphous state even when the storage elements in the same PCM cell are in a crystalline state.

[0042] In some cases, memory element 220 can be partially amorphous and partially crystalline, and its resistance can have some value between the resistance of memory element 220 in a fully crystalline or fully amorphous state. Memory element 220 can therefore be used for applications other than binary logic; that is, the number of possible states stored in the material can exceed two.

[0043] In some cases, the memory element 220 included in the self-selected memory cell is operable so that it does not undergo phase changes during normal operation of the memory cell (e.g., due to the composition of the memory (e.g., chalcogenide) material and / or due to the operating voltage and current configured to maintain the memory element 220 in a single phase (e.g., amorphous or glassy phase). For example, the memory element 220 may contain a chemical element, such as arsenic, that inhibits the crystallization of the chalcogenide material and thus allows it to be maintained in an amorphous state. Here, some or all of the set of logic states supported by the memory cell (e.g., including the memory element 220 and electrode 225) may be associated with the amorphous state of the memory element 220 (e.g., stored by the memory element 220 when it is in an amorphous state). For example, both logic state '0' and logic state '1' may be associated with the amorphous state of the memory element 220 (e.g., stored by the memory element 220 when it is in an amorphous state). In some cases, memory element 220 may be configured to store the logical state corresponding to the information bit.

[0044] During a programming (write) operation of a memory cell (e.g., including electrode 225-a, memory element 220-a, and electrode 225-b), the polarity used for programming (writing) or whether memory element 220 is programmed to be in an amorphous or crystalline state can affect (determine, set, program) specific behaviors or characteristics of memory element 220, such as the threshold voltage or resistance of memory element 220. Differences in the threshold voltage or resistance of memory element 220 depending on the logic state stored by memory element 220 (e.g., the difference between the threshold voltage or resistance when memory element 220 stores logic state '0' and logic state '1') can correspond to a read window of memory element 220.

[0045] Word line 210-a may be at a first level of memory array 200, bit line 215-a may be at a second level of memory array 200, and word line 210-b may be at a third level of memory array 200. Each word line 210 and bit line 215 may include a corresponding metal portion 230 and a metal oxide line 235. In some instances, the metal oxide line 235 may alternatively be considered as separate from the corresponding access line (e.g., separate from the corresponding word line 110 or bit line 115), but the claims are not limited based on such conceptualization. As discussed above and elsewhere herein, a layer of metal oxide may have been formed based on the oxidation of a corresponding metal layer, and in some cases, the metal oxide line 235 may include the same metal material as the metal portion 230 (e.g., if the metal portion 230 includes tungsten (W), then the metal oxide line 235 may include tungsten oxide (W)). x O y If the metal portion 230 includes aluminum (Al), then the metal oxide line 235 may include aluminum oxide (Al). x O y (e.g.); etc.). As described below and elsewhere herein, a second metal layer may have been formed over (e.g., on) the metal oxide layer corresponding to the metal oxide line 235, and the metal portion 230 may have been formed from such a second metal layer. As discussed elsewhere herein, such structures and techniques can provide current spike mitigation and access line resistivity benefits, as well as other possible benefits.

[0046] Figure 3 An example of a memory structure 300 that supports reduced resistivity of access lines in a memory array is shown. For example, memory structure 300 may correspond to, as shown in the reference... Figure 1 The described memory device 100 or as referenced Figure 2 The intermediate structures related to the fabrication of the described memory array 200. The memory structure 300 may include vias 305, drivers 310, and a first metal layer 315.

[0047] Via 305 can be configured to carry signals between driver 310 and access lines, and the via can be formed as described herein. Via 305 may extend through a stack of one or more materials (e.g., dielectric material, memory cell material, or any other material contained in a memory device), which are not shown for clarity of the features presented. Figure 3 In some cases, the via 305 extending through a stack of one or more materials may correspond to one or more stacks of memory devices. The via 305 may be made of one or more materials. For example, the via 305 may contain a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), gold (Au), titanium (Ti), or a metal alloy).

[0048] Driver 310 can be configured to drive a subsequently formed access line coupled to via 305. For example, driver 310 can be used for access operations (e.g., as referenced). Figure 1 The driver 310 (which performs the described read, write, and refresh operations) drives the access lines to the desired voltage. The driver 310 may contain any number of transistors or other circuit components for generating the desired voltage. The driver 310 may be an example of a word line driver or a bit line driver as described elsewhere herein.

[0049] Although a single through-hole 305 and a single driver 310 are shown, any number of through-holes 305 can be manufactured and said any number of through-holes can be coupled to any number of drivers 310. Additionally, although Figure 3 The via 305 is shown as being directly coupled to the driver 310, but the via 305 may alternatively be coupled to the driver 310 via some intermediate interconnect structure (e.g., other vias, metal wiring). The driver 310 may also be distributed throughout the memory array of the memory device.

[0050] In some cases, prior to the formation of the first metal layer 315, a thin layer of oxide (not shown) may form on the via 305 due to natural or unintentional oxidation. For example, the via 305 may be exposed to oxygen during formation, which can cause the thin layer of oxide to form on top of the via 305. In some instances, a dry etching process (e.g., dry argon etching) can be used to remove the thin layer of oxide formed on the via 305 prior to the formation of the first metal layer 315. That is, using a dry etching process allows the first metal layer 315 to be in direct contact with the via 305.

[0051] The first metal layer 315 can be formed over the via 305 (e.g., in contact with the upper surface of the via) using any suitable technique. For example, the first metal layer 315 can be formed using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or any combination thereof. The first metal layer 315 can be formed as a thin layer or a coating. In some cases, the first metal layer 315 can be formed as a sheet. In some cases, the first metal layer 315 can be formed as a blanket over the via 305 and any number of other materials through which the via 305 extends (e.g., the first metal layer 315 can be formed as a sheet over an entire area of ​​a die or wafer). In some cases, the first metal layer 315 can be formed of the same material as the via 305, such as tungsten (W), copper (Cu), aluminum (Al), gold (Au), titanium (Ti), or a metal alloy. In other cases, the first metal layer 315 can be formed of a different material than the material used to form the via 305.

[0052] Figure 4 An example of a memory structure 400 that supports reduced resistivity of access lines in a memory array is shown. For example, memory structure 400 may correspond to, as in reference... Figure 1 The described memory device 100 or as referenced Figure 2 The described memory array 200 is a fabrication-related intermediate structure. In some instances, the memory structure 400 may be the result of additional forming techniques applied to the memory structure 300 as described herein. The memory structure 300 may include vias 305, drivers 310, and a metal oxide layer 415.

[0053] In forming as reference Figure 3 Following the first metal layer 315, the first metal layer 315 may be oxidized to form a metal oxide layer 415. For example, if the first metal layer 315 contains tungsten (W), then the metal oxide layer 415 may contain tungsten oxide (W). x O y If the first metal layer 315 contains aluminum (Al), then the metal oxide layer 415 may contain aluminum oxide (Al). x O y );etc.

[0054] In some instances, the first metal layer 315 can be oxidized by exposing it to oxygen at a relatively high temperature for a duration. Changing the duration of the first metal layer 315's exposure to oxygen or the temperature at which the first metal layer 315 is exposed to oxygen below it can alter the degree of oxidation of the first metal layer 315. For example, the greater the duration or temperature, the greater the degree of oxidation. When the first metal layer 315 is exposed to oxygen, oxygen can flow above the first metal layer 315.

[0055] In other instances, the first metal layer 315 can be oxidized by exposure to oxygen-containing plasma. In such cases, the metal oxide layer 415 can be formed by allowing plasma to flow over the first metal layer 315. In some instances, the degree of oxidation of the metal oxide layer 415 can vary depending on the pressure used in the oxidation chamber, the excitation power of the oxygen-containing plasma, the concentration of the oxygen-containing plasma, and the temperature at which the first metal layer 315 is exposed to the oxygen-containing plasma.

[0056] In some instances, the first metal layer 315 may be formed in a deposition chamber, and the first metal layer 315 may be oxidized in an oxidation chamber. In some cases, the first metal layer 315 may be formed in a vacuum, and the vacuum may be maintained such that the oxidation of the first metal layer can occur under the same vacuum (e.g., the first metal layer 315 may be formed and oxidized in situ).

[0057] In other instances, the first metal layer 315 can be oxidized by oxygen removed from the deposition chamber and exposed to the outside of the vacuum (e.g., in situ). In such cases, the degree of oxidation of the metal oxide layer 415 may depend on the duration of removal of the first metal layer 315 from the vacuum.

[0058] In some cases, a portion 420 of the via 305 (e.g., the upper portion) may also be oxidized during the oxidation process. For example, regardless of the technique used to oxidize the first metal layer 315, if sufficient degree of oxidation is allowed (e.g., such that the first metal layer 315 is oxidized at least above the via 305, across its entire depth), then a portion 420 of the via 305 may also become oxidized (e.g., due to the same process used to oxidize the first metal layer). Thus, as an example, if the portion 420 is formed of tungsten (W), then the oxidation process may cause the portion 420 to contain tungsten oxide (W). x O y ).

[0059] Figure 5 An example of a memory structure 500 that supports reduced resistivity of access lines in a memory array is shown. For example, memory structure 500 may correspond to, as in reference... Figure 1 The described memory device 100 or as referenced Figure 2 The described memory array 200 is a fabrication-related intermediate structure. In some instances, memory structure 500 may be the result of additional forming techniques applied to memory structure 400 as described herein. Memory structure 300 may include vias 305, drivers 310, a metal oxide layer 415, and a second metal layer 525.

[0060] Reference Figure 4Following the described oxidation process (e.g., the formation of metal oxide layer 415), a second metal layer 525 may be formed on metal oxide layer 415. The second metal layer 525 may be relatively thick relative to the first metal layer 315. In some examples, the second metal layer 525 may be formed of the same material as the first metal layer 315, such as tungsten (W), copper (Cu), aluminum (Al), gold (Au), titanium (Ti), or a metal alloy. In other examples, the second metal layer 525 may be formed of a material different from that of the first metal layer 315.

[0061] The second metal layer 525 can be formed using any suitable technique. For example, the second metal layer 525 can be formed using a PVD process, a CVD process, or any combination thereof. In some cases, the second metal layer 525 can be formed using the same deposition process used to form the first metal layer 315. In other instances, the second metal layer 525 can be formed using a different deposition process than that used to form the first metal layer 315. In some cases, the second metal layer 525 can be formed as a blanket over the first metal layer 315 (e.g., the second metal layer 525 can be formed as a wafer over an entire area of ​​a bare die or wafer).

[0062] In some instances, the second metal layer 525 may be formed in the same vacuum in which the first metal layer 315 is formed and oxidized (e.g., the formation of the first metal layer 315, the oxidation of the first metal layer 315, and the formation of the second metal layer 525, or any subset thereof, may occur in situ). This prevents the metal oxide layer 415 from being exposed to any air prior to the formation of the second metal layer 525.

[0063] The second metal layer 525 and the metal oxide layer 415 can be patterned (e.g., processed) to form any number of access lines 530. At least one of the access lines 530 can be coupled to a via 305, such as Figure 5 As shown in the diagram. This allows the separately formed metal lines and metal oxide lines to form a second metal layer 525 and a metal oxide layer 415. For a given access line 530, the corresponding metal oxide line can be considered as a portion of access line 530 (e.g., a sublayer of the access line) or alternatively as a layer separate from (e.g., in contact with) access line 530. Neither conceptualization is intended to limit the scope of the claims.

[0064] The driver 310 can be configured to drive the access line 530 via a signal path including the via 305 during access operations (e.g., read and write operations) to select the memory cell coupled to the access line 530.

[0065] In some cases, forming a second metal layer 525 on top of the metal oxide layer 415 can result in the second metal layer 525 (and therefore any access lines 530 formed therefrom) having a lower resistivity than if the metal oxide layer 415 were not present (e.g., if the second metal layer 525 is formed directly on the via 305 and one or more materials surrounding the via 305). For example, when the second metal layer 525 is formed on the metal oxide layer 415, the second metal layer 525 can be formed at nucleation sites of the metal oxide layer 415. Forming at the nucleation sites of the metal oxide layer 415 can result in the formation of larger crystals (e.g., grains) of the second metal layer 525 material during the formation process of the second metal layer 525. In some instances, larger crystals can result in the second metal layer 525 having a reduced density, reduced resistivity, or both.

[0066] When the second metal layer 525 has a reduced resistivity (e.g., compared to when it is formed in the absence of the metal oxide layer 415), the amount of drive current required to access the distant memory cell via the access line 530 can be reduced. That is, the relatively large ED of the distant memory cell can be reduced by reducing the resistivity in the current path between the distant memory cell and the driver 310. Furthermore, the difference in ED between the near and distant memory cells can be reduced, thereby supporting further design optimizations (e.g., the configuration of the driver current output by the driver 310).

[0067] Alternatively, the presence of a metal oxide line formed by the metal oxide layer 415, the oxide portion 420 of the via 305, or both, can mitigate current spikes via the memory cell coupled to the access line 530. This prevents memory cell degradation and extends memory cell lifespan.

[0068] In some instances, as in the reference Figure 4 During the described formation process, the first metal layer 315 may be partially oxidized. That is, the first metal layer 315 may be oxidized in a manner more suitable for applications such as those described in the reference. Figure 4 The oxidation described is performed within a shorter duration than the complete oxidation of the first metal layer 315. In such instances, a portion 420 of the via 305 (e.g., the upper portion) can avoid the oxidation process and remain unoxidized. For example, if the via 305 is formed of tungsten (W), then after the partial oxidation of the first metal layer 315, portion 420 may also remain tungsten rather than being oxidized to include tungsten oxide (W). x O yTherefore, the first metal layer 315 can be formed as a layer comprising both a metal layer and a metal oxide layer (e.g., a layer having an upper portion comprising a metal oxide layer 415 and a lower portion comprising a metal layer 315). In such examples, the second metal layer 525 can still be formed over the metal oxide layer 415. That is, the formation process can produce a via 305, a first metal layer 315 formed on top of the via 305, a positive oxidation of the first metal layer 315 to the upper portion of the metal oxide layer 415, and a second metal layer 525 formed on top of the metal oxide layer 415. In some examples, the presence of the metal oxide layer 415 between the metal layer 315 and the second metal layer 525 can mitigate current spikes coupled to the access line 530.

[0069] Figure 6 A flowchart illustrating one or more methods 600 for reducing the resistivity of access lines in a supporting memory array according to aspects of this disclosure is provided. The operation of method 600 may be carried out as described herein by means of forming tools, oxidation tools, dry etching tools, or any combination thereof.

[0070] At 605, a through-hole extending through one or more materials of the memory device may be formed. Operation at 605 may be performed according to the methods described herein. In some instances, aspects of operation at 605 may be performed by a forming tool as described herein.

[0071] At 610, a first metal layer may be formed over the via. Operation at 610 may be performed according to the methods described herein. In some instances, aspects of operation at 610 may be performed by a forming tool as described herein.

[0072] At 615, the first metal layer can be oxidized. The operation at 615 can be performed according to the methods described herein. In some instances, aspects of the operation at 615 can be performed by an oxidation tool as described herein.

[0073] At 620, after oxidizing the first metal layer, a second metal layer may be formed over the first metal layer, wherein the second metal layer serves as one or more access lines of the memory device. Operation of 620 may be performed according to the methods described herein. In some instances, aspects of operation of 620 may be performed by a forming tool as described herein.

[0074] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features or components for: forming a through-hole extending through one or more materials of the memory device, forming a first metal layer over the through-hole, oxidizing the first metal layer, and forming a second metal layer over the first metal layer after oxidizing the first metal layer, wherein the second metal layer serves one or more access lines of the memory device.

[0075] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for oxidizing the upper portion of the via after forming a first metal layer over the via.

[0076] In some cases of the method 600 and apparatus described herein, the upper portion of the via may be oxidized by exposing the first metal layer to oxygen when the upper portion of the via can contact the first metal layer.

[0077] In some cases of the method 600 and apparatus described herein, the first metal layer may have a first thickness, and the second metal layer may have a second thickness that is greater than the first thickness.

[0078] In some instances of the method 600 and apparatus described herein, the first metal layer and the second metal layer may both be formed using the same material.

[0079] In some cases of the method 600 and apparatus described herein, the via may contact a first metal layer, and the first metal layer may contact a second metal layer.

[0080] In some cases of the method 600 and apparatus described herein, the first metal layer may be used for one or more access lines of the memory device.

[0081] In some instances of the method 600 and apparatus described herein, oxidizing the first metal layer may include operations, features, components, or instructions for exposing the first metal layer to oxygen for a duration.

[0082] In some cases of the method 600 and apparatus described herein, the oxidation of the first metal layer may include operations, features, components, or instructions for exposing the first metal layer to plasma.

[0083] In some cases of the method 600 and apparatus described herein, forming a first metal layer may include operations, features, components, or instructions for depositing the first metal layer via a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or any combination thereof.

[0084] In some instances of the method 600 and apparatus described herein, forming a second metal layer may include operations, features, components, or instructions for depositing the second metal layer via a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or any combination thereof.

[0085] Examples of the methods 600 and apparatus described herein may further include operations, features, components, or instructions for removing oxide portions of vias prior to the formation of a first metal layer.

[0086] Some aspects of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: forming a first metal layer in a vacuum, oxidizing the first metal layer in a vacuum, and forming a second metal layer in a vacuum.

[0087] Figure 7 A flowchart illustrating one or more methods 700 for reducing the resistivity of access lines in a supporting memory array according to aspects of this disclosure is provided. The operation of method 700 may be carried out as described herein by means of forming tools, oxidation tools, dry etching tools, or any combination thereof.

[0088] At 705, a through-hole extending through one or more materials of the memory device may be formed. Operation of 705 may be performed according to the methods described herein. In some instances, aspects of operation of 705 may be performed by a forming tool as described herein.

[0089] At 710, a first metal layer may be formed over the via. Operation at 710 may be performed according to the methods described herein. In some instances, aspects of operation at 710 may be performed by a forming tool as described herein.

[0090] At 715, the first metal layer can be oxidized. The operation at 715 can be performed according to the methods described herein. In some instances, aspects of the operation at 715 can be performed by an oxidation tool as described herein.

[0091] At point 720, after the first metal layer is formed above the via, the upper portion of the via can be oxidized. The operation at point 720 can be performed according to the methods described herein. In some instances, aspects of the operation at point 720 can be performed by an oxidation tool as described herein.

[0092] At 725, after oxidizing the first metal layer, a second metal layer may be formed over the first metal layer, wherein the second metal layer serves as one or more access lines of the memory device. Operation of 725 may be performed according to the methods described herein. In some instances, aspects of operation of 725 may be performed by a forming tool as described herein.

[0093] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0094] Describe a device. The device may include: a collection of memory cells coupled to access lines extending within the device in a first direction, the access lines comprising metal; vias extending through one or more materials within the device in a second direction, the second direction being different from the first direction; and metal oxide lines extending between the metal and the vias in the first direction.

[0095] In some instances, a portion of the via may be oxidized and in contact with a metal oxide line.

[0096] In some cases, the metal oxide line may have a first thickness, and the metal of the access line may have a second thickness that is greater than the first thickness.

[0097] In some cases, metal oxide lines may come into contact with the metal of the access lines.

[0098] In some instances, the access lines consist of metal oxide lines.

[0099] In some cases, the first portion of the via contains metal, and the second portion of the via contains metal oxide.

[0100] In some cases, the first portion of the access line and via contains tungsten, and the second portion of the metal oxide line and via contains tungsten oxide.

[0101] In some instances, the metal oxide line contains an oxide of a second metal that may be different from the metal of the access line.

[0102] In some cases, metal oxide lines may have a higher resistivity than vias, access lines, or both.

[0103] Describe a device. The device may include access lines for a collection of memory cells, wherein the access lines include metal wires extending within the device in a first direction, vias extending in a second direction other than the first direction, and drivers for the access lines, wherein the drivers are coupled to the access lines via the vias and metal oxides are inserted between the metal wires and the vias.

[0104] Some instances may further include at least a portion of the metal oxide contained within a metal oxide line extending in the first direction.

[0105] In some cases, a portion of the via contains metal oxide and can contact the metal oxide line.

[0106] The information and signals described herein can be represented using any of a variety of techniques and methods. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0107] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0108] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via conductive paths, while in a closed-circuit relationship, signals can be transmitted between components via conductive paths. When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0109] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then those components are isolated from each other. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components from each other, it prevents signals from flowing between the components using previously permitted conductive paths.

[0110] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0111] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0112] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., most charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0113] The exemplary configurations described herein, in conjunction with the accompanying drawings, are not intended to represent all implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other examples. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatus are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0114] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any similar component that has the same first reference numeral but is independent of the second reference numeral.

[0115] The information and signals described herein can be represented using any of a variety of techniques and methods. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description.

[0116] The various illustrative blocks and modules described herein in conjunction with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0117] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributions such that portions of the functionality are implemented in different physical locations. Furthermore, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0118] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: Forming a through-hole extending through one or more materials of a memory device, wherein a first portion of the through-hole comprises tungsten and a second portion of the through-hole comprises tungsten oxide; A first metal layer is formed above the through hole; Oxidize the first metal layer, wherein the first metal layer comprises at least partially tungsten oxide based on the oxidation of the first metal layer; and After oxidizing the first metal layer, a second metal layer is formed over the first metal layer, wherein the second metal layer is used for one or more access lines of the memory device, and wherein the second metal layer extends in a first direction different from the second direction in which the via extends.

2. The method according to claim 1, further comprising: After forming the first metal layer over the via, the upper portion of the via is oxidized, wherein the second portion of the via comprises at least partially tungsten oxide based on the oxidation of the upper portion of the via.

3. The method of claim 2, wherein the upper portion of the via is oxidized at least in part based on the first metal layer being exposed to oxygen when the upper portion of the via comes into contact with the first metal layer.

4. The method according to claim 1, wherein: The first metal layer has a first thickness; and The second metal layer has a second thickness greater than the first thickness.

5. The method of claim 4, wherein the first metal layer and the second metal layer are both formed using the same material.

6. The method according to claim 1, wherein: The through-hole is in contact with the first metal layer; and The first metal layer is in contact with the second metal layer.

7. The method of claim 1, wherein the first metal layer is used for the one or more access lines of the memory device.

8. The method of claim 1, wherein oxidizing the first metal layer comprises exposing the first metal layer to oxygen for a duration.

9. The method of claim 1, wherein oxidizing the first metal layer comprises exposing the first metal layer to a plasma comprising oxygen for a duration.

10. The method of claim 1, wherein forming the first metal layer comprises: The first metal layer is deposited via physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof.

11. The method of claim 1, wherein forming the second metal layer comprises: The second metal layer is deposited via physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof.

12. The method of claim 1, further comprising: Before forming the first metal layer, the oxidized portion of the via is removed.

13. The method according to claim 1, wherein: The formation of the first metal layer occurs in a vacuum; The oxidation of the first metal layer occurs in the vacuum; and The formation of the second metal layer occurs in the vacuum.

14. An apparatus comprising: An assembly of memory cells coupled to access lines extending in the device in a first direction, the access lines comprising metal; A through-hole extending through one or more materials within the device in a second direction different from a first direction, wherein a first portion of the through-hole comprises tungsten and a second portion of the through-hole comprises tungsten oxide; and A metal oxide line, comprising tungsten oxide and extending in the first direction between the metal and the through-hole.

15. The device of claim 14, wherein the second portion of the through-hole is in contact with the metal oxide line.

16. The device according to claim 14, wherein: The metal oxide line has a first thickness; and The metal in the access line has a second thickness greater than the first thickness.

17. The device of claim 14, wherein the metal oxide line is in contact with the metal of the access line.

18. The device of claim 14, wherein the access line comprises the metal oxide line.

19. The device according to claim 14, wherein: The access line comprises tungsten.

20. The device of claim 14, wherein the metal of the access line is different from the tungsten oxide of the metal oxide line.

21. The device of claim 14, wherein the metal oxide line has a greater resistivity than the via, the metal of the access line, or both.

22. An apparatus comprising: Access lines for a collection of memory cells, wherein the access lines include metal wires extending in a first direction within the device; A through-hole extending in a second direction different from the first direction, wherein a first portion of the through-hole comprises tungsten and a second portion of the through-hole comprises tungsten oxide; and A driver for the access line, wherein: The driver is coupled to the access line via the through-hole; and A metal oxide layer, including tungsten oxide, is inserted between the metal wire and the through hole.

23. The device of claim 22, wherein at least a portion of the metal oxide layer is contained within a metal oxide line extending in the first direction.

24. The device of claim 23, wherein a portion of the through-hole includes the metal oxide layer and is in contact with the metal oxide line.

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