Decoder architecture for memory devices

Abstract

This application is directed to decoder architectures for memory devices. An apparatus includes a memory array having memory cells and access lines coupled with the cells, and a decoder having a first stage and a second stage. The decoder supplies a first voltage to the access lines during a first access operation and a second voltage to the access lines during a second access operation. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

Description

[0001] CROSS REFERENCE

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 108,763, filed December 1, 2020, entitled “DECODER ARCHITECTURE FOR MEMORY DEVICE”, by Bedeschi et al., which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to decoder architectures for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically represented as logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any one of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write to or program the states in the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory array including memory cells and access lines coupled to the memory cells; a decoder including a first stage and a second stage, the decoder being configured to supply a first voltage to the access lines during a first access operation and to supply a second voltage to the access lines during a second access operation, the second stage of the decoder possibly including: a first transistor configured to supply the first voltage to the access lines during the first access operation based at least in part on a third voltage at the source of the first transistor exceeding a fourth voltage at the gate of the first transistor and a first threshold voltage of the first transistor; and a second transistor configured to supply the second voltage to the access lines during the second access operation based at least in part on a fifth voltage at the gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage of the second transistor.

[0007] Describe a method. The method may include: receiving a command associated with a memory cell coupled to an access line; at least in part based on receiving the command, biasing the source of a first transistor to a first voltage exceeding a second voltage of the gate of the first transistor and a first threshold voltage of the first transistor through a first stage of a decoder to activate the first transistor, wherein a second stage of the decoder includes the first transistor; at least in part based on receiving the command, biasing the source of a second transistor to a third voltage through the first stage of the decoder to deactivate the second transistor, wherein a fourth voltage of the gate of the second transistor is less than the second voltage and the second threshold voltage of the second transistor, and wherein the second stage of the decoder includes the second transistor; and supplying a positive voltage to the access line at least in part based on biasing the source of the first transistor and biasing the source of the second transistor.

[0008] Describe an apparatus. The apparatus may include: a memory array including memory cells and access lines coupled to the memory cells; a decoder including a first stage and a second stage, the second stage including a first transistor and a second transistor; and a controller coupled to the memory array and the decoder and configured to: receive a command associated with the memory cells coupled to the access lines; at least in part based on receiving the command, bias the source of the first transistor through the first stage of the decoder to a first voltage exceeding a second voltage of the gate of the first transistor and a first threshold voltage of the first transistor to activate the first transistor, wherein the second stage of the decoder includes the first transistor; at least in part based on receiving the command, bias the source of the second transistor through the first stage of the decoder to a third voltage to deactivate the second transistor, wherein a fourth voltage of the gate of the second transistor is less than the second voltage and the second threshold voltage of the second transistor, and wherein the second stage of the decoder includes the second transistor; and supply a positive voltage to the access lines at least in part based on biasing the source of the first transistor and biasing the source of the second transistor. Attached Figure Description

[0009] Figure 1 An example of a memory die supporting a decoder architecture for a memory device, according to the examples disclosed herein, is shown.

[0010] Figure 2 An example of a memory cell for a decoder architecture supporting a memory device, as disclosed herein, is shown.

[0011] Figure 3 Examples of decoders that support memory device decoder architectures according to the examples disclosed herein are shown.

[0012] Figure 4A , 4B Figures 4C illustrate examples of circuitry supporting a decoder architecture for a memory device, according to the examples disclosed herein.

[0013] Figure 5 A block diagram of a memory device with a decoder architecture supporting the memory device according to the examples disclosed herein is shown.

[0014] Figure 6 A flowchart illustrating an example disclosed herein demonstrates one or more methods for supporting a decoder architecture for a memory device. Detailed Implementation

[0015] A memory device may include an array of memory cells (e.g., a memory array) for storing data from a host device. In some instances, the memory device may read data from or write data to memory cells based on commands from the host device. In such instances, the memory device may drive voltages on access lines (e.g., word lines or bit lines) coupled to memory cells to activate the memory cells and perform read or write operations. The memory device may implement a decoder (e.g., a column decoder or row decoder) to decode a memory address associated with a host device command and activate the access lines coupled to the memory cells associated with the command. In some instances, the decoder may be located below the memory array. In such instances, scaling down the size of the decoder in a similar manner as the size of the memory array decreases can be challenging. For example, the size of the memory array may decrease, but the voltage activating the memory cells may not decrease, thus scaling down the components in the decoder used to apply the voltage can be challenging. That is, memory devices using high voltages may include transistors with oxides capable of isolating high voltages from access lines. In some instances, it may be difficult to scale down the size and dimensions of the oxides while still isolating the high voltage. Additionally, in some cases, it can be difficult to design a decoder that is scaled down to the memory array while preventing interference with adjacent access lines. That is, scaling down the decoder increases the likelihood that voltage may also be applied to adjacent access lines of non-target memory cells.

[0016] This document describes systems, techniques, and apparatuses for a memory device including a decoder with a first stage configured to supply a positive voltage, a negative voltage, or a ground voltage to access lines coupled to memory cells based on commands received from a host device. For example, the first stage of the decoder may include a first transistor supplying a positive voltage during a first access operation, a second transistor supplying a negative voltage during a second access operation, and a third transistor supplying a ground voltage for a duration between the first and second access operations. That is, the decoder may be configured to provide a bipolar programming voltage (e.g., positive or negative voltage) to the memory cells. In some instances, the voltage driving the access lines can be reduced by half compared to other solutions. In such instances, the thickness of the oxide layer used for isolation from high voltages can be reduced, allowing for a smaller decoder. In some instances, the third transistor may also act as a voltage clamp, reducing the likelihood of interference with adjacent lines. The decoder may also include second and third stages for supplying voltage and providing a level shifter. This configuration allows the decoder to be scaled down proportionally to the size of the memory device. In such instances, the decoder can remain positioned below the memory array, even if the memory array is scaled down to a smaller size, thus eliminating the need for additional wiring between the memory array and its supporting circuitry.

[0017] The features of this disclosure are initially referenced in the reference. Figure 1 and 2 The memory systems, dies, and arrays described herein are described in the context of the memory systems, dies, and arrays described herein. Features of this disclosure are described in the references to... Figure 3 The decoder and circuitry described in section 4 are described in the context of this disclosure. These and other features of this disclosure are further elaborated by reference to [reference 4]. Figure 5 and 6 Device diagrams and flowcharts related to the decoder architecture of the described memory device are shown and referenced in the description.

[0018] Figure 1 An example of a memory die 100 supporting a decoder architecture for a memory device according to the examples disclosed herein is shown. In some instances, the memory die 100 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 100 may include one or more memory cells 105, each programmable to store different logical states (e.g., a programmed state from a set of two or more possible states). For example, memory cell 105 may be used to store one information bit at a time (e.g., logic 0 or logic 1). In some instances, memory cell 105 (e.g., multi-level memory cell 105) may be used to store more than one information bit at a time (e.g., logic 00, logic 01, logic 10, logic 11).

[0019] Memory cell 105 can use configurable materials to store logical states. These configurable materials can be referred to as memory elements, memory storage elements, material elements, material memory elements, material portions, or polarity write material portions, etc. The configurable material of memory cell 105 can refer to chalcogenide-based storage components, such as those mentioned above. Figure 3 For more detailed description, chalcogenide memory elements can be used in phase-change memory (PCM) cells, threshold memory cells, or self-selection memory cells.

[0020] The memory die 100 may include access lines (e.g., row lines 110 and column lines 115) arranged in a pattern (e.g., a grid pattern). The access lines may be formed of one or more conductive materials. In some instances, row lines 110 may be referred to as word lines. In some instances, column lines 115 may be referred to as digital lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, are interchangeable without affecting understanding or operation. Memory cells 105 may be located at the intersection of row lines 110 and column lines 115.

[0021] For example, read and write operations can be performed on memory cell 105 by activating or selecting access lines (e.g., one or more of row lines 110 or column lines 115). A single memory cell 105 can be accessed at its intersection by biasing row lines 110 and column lines 115 (e.g., applying a voltage to row lines 110 or column lines 115). The intersection of row lines 110 and column lines 115 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 105. Access lines can be conductive lines coupled to memory cell 105 and can be used to perform access operations on memory cell 105.

[0022] Memory cell 105 can be controlled by row decoder 120 or column decoder 125. For example, row decoder 120 may receive row addresses from local memory controller 145 and activate row line 110 based on the received row addresses. Column decoder 125 may receive column addresses from local memory controller 145 and activate column line 115 based on the received column addresses. In some instances, row decoder 120 and / or column decoder 125 may be located below the memory array (e.g., below memory cell 105). Row decoder 120 and column decoder 125 may comprise three levels (e.g., a first level, a second level, and a third level). In some instances, the first level of row decoder 120 and column decoder 125 may be coupled to either row line 110 or column line 115, respectively. The second level of row decoder 120 and column decoder 125 may be coupled to the first level and configured to activate the first level associated with the row address or the column address. In other words, row decoder 120 and column decoder 125 may include multiple first stages, each first stage being coupled to a different row line 110 or column line 115. A second stage may be used to activate the first stage associated with the row address or column address. Row decoder 120 and column decoder 125 may also include a third stage configured to supply voltage to the first stages and the row lines 110 and column lines 115.

[0023] In some instances, row decoder 120 and column decoder 125 may provide voltages based on commands received from the host device or a stage of memory die 110. For example, in response to a first access command from the host device, row decoder 120 and column decoder 125 may provide positive voltages to row line 110 and column line 115, respectively. In other instances, in response to a second access command from the host device, row decoder 120 and column decoder 125 may provide negative voltages to row line 110 and column line 115, respectively. That is, memory cell 105 can be programmed with negative or positive voltage pulses (e.g., bipolar programming), and row decoder 120 and column decoder 125 may activate the memory cell using positive or negative voltages according to commands received from the host device. In other instances, row decoder 120 and column decoder 125 may provide ground voltages to row line 110 and column line 115, respectively. For example, row decoder 120 and column decoder 125 may provide ground voltages during a reset operation or during a period between a first access operation and a second access operation.

[0024] In some instances, the first stage of the row decoder 120 and column decoder 125 may contain three (3) transistors. The simplicity of the first stage of the row decoder 120 and column decoder 125 allows them to be scaled down proportionally to the shrinkage of the memory die 100—for example, the row decoder 120 and column decoder 125 may be made smaller proportionally to the shrinkage of the memory die 100 to save additional space. In such instances, the first transistor of the first stage may be configured to supply a positive voltage, the second transistor of the first stage may be configured to supply a negative voltage, and the third transistor of the first stage may be configured to supply ground. For further details regarding the first stage, refer to [reference needed]. Figure 4A-4C describe.

[0025] Sensing component 130 can be used to detect the state of memory cell 105 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 105 based on the stored state. Sensing component 130 may include one or more sensing amplifiers for amplifying or otherwise converting signals generated by accessing memory cell 105. Sensing component 130 can compare the signal detected from memory cell 105 with reference 135 (e.g., reference voltage). The detected logic state of memory cell 105 can be provided as an output of sensing component 130 (e.g., provided to input / output 140) and can indicate the detected logic state to another component of the memory device including memory die 100.

[0026] The local memory controller 145 can control access to memory cells 105 via various components (e.g., row decoder 120, column decoder 125, sensing component 130). In some instances, one or more of the row decoder 120, column decoder 125, and sensing component 130 may be located in the same location as the local memory controller 145. The local memory controller 145 can be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller associated with a host device, another controller associated with memory die 100), translate the commands or data (or both) into information usable by memory die 100, perform one or more operations on memory die 100, and transfer data from memory die 100 to the host device based on the performance of said one or more operations. The local memory controller 145 can generate row signals and column address signals to activate target row lines 110 and target column lines 115. The local memory controller 145 can also generate and control various voltages or currents used during operation of memory die 100. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed in the operational memory die 100.

[0027] The local memory controller 145 can be used to perform one or more access operations on one or more memory cells 105 of the memory die 100. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed by the local memory controller 145 in response to individual access commands (e.g., from a host device) or otherwise coordinated. The local memory controller 145 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 100 but not directly related to accessing the memory cells 105.

[0028] The local memory controller 145 can be used to perform write operations (e.g., programming operations) on one or more memory cells 105 of the memory die 100. During a write operation, the memory cells 105 of the memory die 100 can be programmed to store a desired logical state. The local memory controller 145 can identify the target memory cell 105 on which a write operation is to be performed. The local memory controller 145 can identify target row lines 110 and target column lines 115 coupled to the target memory cell 105 (e.g., the address of the target memory cell 105). The local memory controller 145 can activate the target row lines 110 and target column lines 115 (e.g., apply a voltage to the row lines 110 or column lines 115) to access the target memory cell 105. The local memory controller 145 can apply a specific signal (e.g., a write pulse) to the column line 115 during a write operation to store a specific state in the memory element of the memory cell 105. The pulse used as part of the write operation can contain one or more voltage levels over a duration.

[0029] The local memory controller 145 can be used to perform read operations (e.g., sensing operations) on one or more memory cells 105 of the memory die 100. During the read operation, the logical state stored in the memory cells 105 of the memory die 100 can be determined. The local memory controller 145 can identify the target memory cell 105 on which the read operation is to be performed. The local memory controller 145 can identify target row lines 110 and target column lines 115 coupled to the target memory cell 105 (e.g., the address of the target memory cell 105). The local memory controller 145 can activate the target row lines 110 and target column lines 115 (e.g., apply a voltage to the row lines 110 or column lines 115) to access the target memory cell 105. The sensing component 130 can detect signals received from the memory cell 105 based on pulses applied to the row lines 110, pulses applied to the column lines, and / or the resistance or threshold characteristics of the memory cell 105. The sensing component 130 can amplify the signals. The local memory controller 145 can activate the sensing component 130 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 105 with the reference signal 135. Based on the comparison, the sensing component 130 can determine the logic state stored in the memory cell 105. The pulse used for the read operation can contain one or more voltage levels over a duration.

[0030] Figure 2 An example of a memory array 200 according to the embodiments disclosed herein is shown. The memory array 200 may be a reference. Figure 1An example of a portion of the described memory array or memory die. Memory array 200 may include a first memory cell stack 205 positioned above a substrate (not shown) and a second memory cell stack 210 on top of the first array or stack 205. Although an example of memory array 200 includes two stacks 205, 210, memory array 200 may include any number of stacks (e.g., one or more).

[0031] The memory array 200 may also include row lines 110-a, 110-b, 110-c, 110-d, column lines 115-a and 115-b, which may be references. Figure 1 Examples of row lines 110 and column lines 115 are described. One or more memory cells in the first stack group 205 and the second stack group 210 may be contained in one or more chalcogenide materials in the posts between the access lines. For example, a single stack between access lines may contain one or more of a first electrode, a first chalcogenide material (e.g., a selector assembly), a second electrode, a second chalcogenide material (e.g., a memory element), or a third electrode. Although contained in Figure 3 Some elements are labeled with numerical indicators, while other corresponding elements are not labeled, but they are the same or should be understood as similar, in order to increase the visibility and clarity of the depicted features.

[0032] One or more memory cells in the first stack 205 may include one or more of electrodes 225-a, memory elements 220-a, or electrodes 225-b. One or more memory cells in the second stack 210 may include electrodes 225-c, memory elements 220-b, and electrodes 225-d. The memory element 220 may be an example of a chalcogenide material, such as a phase-change memory element, a threshold memory element, or a self-selecting memory element. In some instances, the memory cells of the first stack 205 and the second stack 210 may have a common conductive line, such that corresponding memory cells in one or more stacks 205 and one or more stacks 210 may share column line 115 or row line 110. For example, the first electrode 225-c of the second stack 210 and the second electrode 225-b of the first stack 205 may be coupled to column line 115-a, such that column line 115-a can be shared by vertically adjacent memory cells.

[0033] In some instances, the material of the storage element 220 may comprise a chalcogenide material or other alloys comprising selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may also comprise silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some instances, SAG alloys may comprise silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof. In some instances, the chalcogenide glass may contain additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0034] In some instances, storage element 220 may be an example of a phase-change memory cell. In such instances, the material used for storage element 220 may be based on an alloy (e.g., the alloys listed above) and may be used to undergo a phase transition or change to a different physical state during normal operation of the memory cell. For example, a phase-change memory cell may have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration).

[0035] Phase change memory cells can exhibit an observable difference in resistance between the crystalline and amorphous states of phase change materials, which can be chalcogenide materials. Crystalline materials allow atoms to be arranged in a periodic structure, resulting in relatively low resistance. In contrast, amorphous materials may have little or no periodic atomic structure, leading to relatively high resistance.

[0036] The difference in resistance between the amorphous and crystalline states of a material can be significant. For example, the resistance of an amorphous material can be one or more orders of magnitude greater than that of a crystalline material. In some instances, the material can be partially amorphous and partially crystalline, and the resistance can have a value somewhere between that of a fully crystalline or fully amorphous material. In such instances, the material can be used to store more than two logic states (e.g., three or more logic states).

[0037] During programming (writing) operations of phase-change memory cells (e.g., electrode 225-a, memory element 220-a, electrode 225-b), various parameters of the programming pulse can influence (e.g., determine, set, program) specific properties or characteristics of the material of memory element 220, such as the threshold voltage or resistance of the material. To program a low-resistance state (e.g., a relatively crystalline state) in the phase-change memory cell, a programming pulse that heats or melts the material of memory element 220 can be applied, which may be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the programming pulse can decrease (e.g., relatively slowly) over a duration, allowing the material to form a crystalline structure upon cooling, thereby forming a stable crystalline material state. To program a high-resistance state (e.g., a relatively amorphous state) in the phase-change memory cell, a programming pulse that heats and / or melts the material of memory element 220 can be applied. The decrease in the amplitude of the programming pulse can be faster than that of the programming pulse for the low-resistance state. In such scenarios, materials can be cooled using atoms arranged in a more disordered atomic pattern, as the atoms cannot form a crystalline structure before the material reaches a stable state, thus creating a stable amorphous material state. The difference in threshold voltage resistance of the material of storage element 220, depending on the logic state stored by the material of storage element 220, can correspond to the read window of storage element 220. In some cases, a portion of the storage element can undergo material changes associated with the logic state.

[0038] In some instances, such as for threshold memory cells or selectable memory cells, some or all of the set of logic states supported by the memory cell may be associated with an amorphous state of a chalcogenide material (e.g., a single-state material may be used to store different logic states). In some instances, memory element 220 may be an example of a selectable memory cell. In such instances, the material used for memory element 220 may be based on an alloy (e.g., alloys listed above) and may be used to change to different physical states during normal operation of the memory cell. For example, a selectable memory cell may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a RESET state), and the low threshold voltage state may correspond to a second logic state (e.g., a SET state).

[0039] During a programming (write) operation of a self-selected memory cell (e.g., including electrode 225-a, memory element 220-a, and electrode 225-b), the polarity of the write operation can affect (determine, set, program) specific properties or characteristics of the material of memory element 220, such as the threshold voltage of the material. The threshold voltage difference of the material of memory element 220, depending on the logic state stored by the material of memory element 220 (e.g., the difference between the threshold voltage when the material stores logic state '0' and when it stores logic state '1'), can correspond to the read window of memory element 220.

[0040] In some instances, the architecture of memory array 200 may be referred to as a crosspoint architecture, where memory cells are formed at topological intersections between row lines 110 and column lines 115. Compared to other memory architectures, such crosspoint architectures offer relatively high-density data storage and lower manufacturing costs. For example, compared to other architectures, crosspoint architectures can have memory cells with a smaller area and therefore a higher memory cell density. For instance, compared to other architectures with a 6F² memory cell area (e.g., those with three-terminal selector elements), the architecture can have a 4F² memory cell area, where F is the minimum feature size. For example, DRAM can use transistors as three-terminal devices as selector elements for each memory cell and can have a larger memory cell area compared to crosspoint architectures.

[0041] although Figure 3 The examples illustrate two memory stacks, but other configurations are possible. In some instances, a single memory stack of memory cells can be constructed above the substrate, which can be referred to as a two-dimensional memory. In some instances, two or more memory cell stacks can be configured in a similar manner as a three-dimensional cross-point architecture. Furthermore, in some cases, Figure 3 As shown or referenced Figure 3 The described elements may be electrically coupled to each other as shown or described, but may be physically rearranged (e.g., storage element 220 and possible selection elements or electrodes 225 may be electrically connected in series between row line 110 and column line 115, but do not need to be in a post or stack configuration).

[0042] In some instances, line 110 may be connected to the first decoder (e.g., reference). Figure 1 The described row decoder 120 is coupled. Column line 115 may be coupled to a second decoder (e.g., reference...). Figure 1The described column decoder 125 is coupled. A decoder (e.g., a first decoder and a second decoder) can supply positive or negative voltages to row lines 110 and column lines 115. The decoder can have multiple stages, e.g., three (3) stages. Row lines 110 and column lines 115 can be coupled to the first stage. The decoder can decode a row address or column address received from a host device and activate row line 110 or column line 115 based on the decoding. In some instances, the first stage may include a first transistor for supplying a positive voltage, a second transistor for supplying a negative voltage, and a third transistor for supplying a ground voltage. Further details regarding the first, second, and third stages can be found in [reference needed]. Figure 3 And 4 are described.

[0043] Figure 3 An example of a decoder 300 supporting a memory device decoder architecture according to the examples disclosed herein is shown. Decoder 300 may be a line decoder (e.g., see reference 1). Figure 1 The described row decoder 120) or column decoder (e.g., reference) Figure 1 An example of the described column decoder 125. Decoder 300 may include a first stage 305, a second stage 310, and a third stage 315. Decoder 300 may also include voltage sources 320-a and 320-b.

[0044] Decoder 300 and one or more other components of the memory device may be configured to decode a memory address in a command received from the host device and activate the memory cell associated with the memory address (e.g., memory cell 105). For example, the memory device may be configured to receive a memory address, determine the memory cell associated with the address, and use decoder 300 to activate circuitry 325 in first stage 305, transistors in second stage 310, and transistors in third stage 315 to access a line coupled to the memory cell (e.g., reference 105). Figure 1 The described row lines 110 or column lines 115 provide voltage. Although the first stage 305, the second stage 310, and the third stage 315 are shown as adjacent to each other, in some instances, the first stage 305, the second stage 310, and the third stage 315 may be configured to be located in different positions below the memory array containing the memory cells. In some instances, multiple drivers for the second stage 310 and the third stage 315 can share a decoder (e.g., at a location below the memory array).

[0045] The first stage 305 may be configured to supply voltage to an access line coupled to a memory cell to activate the memory cell. That is, each circuit 325 in the first stage 305-a may be coupled to a different access line (or multiple access lines) and supply a negative or positive voltage to the corresponding coupled access line. The decoder 300 may include multiple first stages 305 (e.g., 305-a to 305-h), and each first stage 305 may have eight (8) circuits 325. The first stages 305 may be coupled to a second stage 310 of the decoder. In some instances, the first stages 305 may be configured to prevent interference with adjacent word lines. That is, the circuits 325 may include clamps (e.g., transistors) configured to prevent voltage supplied to an access line coupled to the circuit 325 from affecting nearby adjacent access lines. Further details of the circuits 325 can be found in [reference]. Figure 4A-4C To provide.

[0046] The second stage 310 may be configured to supply voltage to the first stage 305 to activate the first stage 305 associated with a command. For example, the decoder 300 may activate the first transistor 330 of the second stage to supply voltage to the first stage 305. When the access line and the memory cell associated with the first stage 305-a are not targeted (e.g., not associated with a memory address received from the host device), the decoder 300 may deactivate the first transistor 330 of the second stage to isolate the first stage 305-a from the voltage. In some instances, the second stage 310 may include a first portion of the second stage 310-a and a second portion of the second stage 310-b. When a first access operation is performed, the decoder 300 may activate the first portion of the second stage 310-a. For example, when a negative voltage is supplied to the first stage 305-a, the first portion of the second stage 310-a may activate a given transistor (e.g., the first transistor 330). In other instances, when a second access operation is performed, the decoder 300 may activate the second portion of the second stage 310-b. For example, when a positive voltage is supplied to the first stage 305-a, the second part of the second stage 310-b can activate the transistor.

[0047] The third stage 315 may be configured to isolate a voltage from voltage source 320 from or supply a voltage from voltage source 320 to the second stage 310. For example, a first portion of the third stage 315-a may be configured to activate a transistor during a first access operation to supply a negative voltage from voltage source 320-a to a first portion of the second stage 310-a (e.g., first transistor 330). In such an example, a second portion of the third stage 315-b may isolate a second portion of the second stage 310-b from voltage source 320-b. In other examples, a second portion of the third stage 315-b may be configured to activate a transistor during a second access operation to supply a positive voltage from voltage source 320-b to a second portion of the second stage 310-b. In such an example, a first portion of the third stage 315-a may isolate a first portion of the second stage 310-a from voltage source 320-a.

[0048] Voltage source 320-a can be configured to supply a negative voltage to decoder 300. In some instances, the voltage supplied by voltage source 320-a can be a VNN voltage with a value of -2.6 volts. Voltage source 320-b can be configured to supply a positive voltage to decoder 300. In some instances, the voltage supplied by voltage source 320-b can be a VPP voltage with a value of 2.6 volts.

[0049] In some instances, memory devices (e.g., reference) Figure 1 The described memory device can be used in memory cells (e.g., reference). Figure 1 The memory cell 105 described herein stores data from the host device. The host device may transmit access commands (e.g., read, write, or refresh commands) to the memory device. In response, the memory device may activate the memory cell associated with the memory address in the command received from the host device. The memory cell may be activated by applying a voltage to an access line coupled to the memory cell. In some instances, the memory cell may support bipolar programming (e.g., the memory cell may be written to or read using either a positive or negative voltage). The decoder 300 may supply voltage to the access line according to the command—for example, the decoder 300 may provide a positive or negative voltage based on the command. The decoder 300 may also be configured to supply a ground voltage to the access line between access operations.

[0050] For example, the memory device may receive a first command associated with a first access operation on a first memory cell. In response to receiving the first command, decoder 300 may activate transistors in the first portion of the third stage 315-a and the first transistor 330 of the first portion of the second stage 310-a, and supply a negative voltage to circuit 325. Decoder 300 may also deactivate some or all of the transistors in the second portion of the second stage 310-b and the second portion of the third stage 315-b to isolate circuit 325 from the positive voltage. In such an example, the memory device may apply a negative voltage to the access line coupled to the first memory cell associated with the first command.

[0051] In other instances, the memory device may receive a second command associated with a second access operation on a first memory cell. In response to receiving the second command, decoder 300 may activate transistors in the second portion of the third stage 315-b and the second portion of the second stage 310-b, and supply a positive voltage to circuit 325. Decoder 300 may also deactivate some or all of the transistors in the first portion of the second stage 310-a and the first portion of the third stage 315-a to isolate circuit 325 from the negative voltage. In such instances, the memory device may apply a positive voltage to the access line coupled to the first memory cell associated with the second command.

[0052] By using the architecture described herein, decoder 300 can be manufactured to scale down in proportion to the shrinkage of the memory array. That is, in some instances, scaling down the decoder to scale down the memory array can be challenging. For example, the memory array can use the same voltage during scaling, but this could allow the decoder to remain the same size—for example, the decoder's drivers might not scale down because they still provide the same voltage. In other instances, decoder 300 using high voltages may include transistors with oxides capable of isolating high voltages from access lines. In some instances, it may be difficult to scale down the size and dimensions of the oxides while still isolating the high voltages.

[0053] As described in this article, decoder 300 can use smaller voltages compared to other solutions (e.g., the magnitudes of positive and negative voltages can be reduced by half). This allows the decoder to isolate high voltages using smaller transistors, resulting in a smaller footprint. Decoder 300 also features simpler voltage-to-access line routing. For additional details on the simpler routing, please refer to [link to relevant documentation]. Figure 4A-4C Described in the context of circuit 325.

[0054] Figure 4A , 4BExamples of circuits 400, 401, and 402, respectively, for a decoder architecture supporting a memory device according to the embodiments disclosed herein are shown in Figures 400, 401, and 402. In some instances, circuit 400 may be a reference circuit. Figure 3 An instance of the described circuit 325. That is, circuits 400, 401 and 402 may be instances of components of the first stage (e.g., first stage 305) of a decoder (e.g., decoder 300). Figure 4A , 4B 4C can represent the various voltages received and output by circuit 325 during different time periods (e.g., during the first access operation, the second access operation, or the time period between the first access operation and the second access operation).

[0055] Figure 4A A circuit 400 is shown, comprising a first transistor 405, a second transistor 410, and a third transistor 415. The circuit 400 may also include an access line 455 (e.g., reference 415). Figure 1 The described row line 110 or column line 115). In some instances, access line 455 may be connected to a memory cell (e.g., reference...). Figure 1 The memory cell 105 described is coupled. Circuit 400 may be an example of a circuit configuration that applies a positive voltage (VPP) to access line 455.

[0056] In an example of circuit 400, the first transistor 405 may be configured to supply access line 455 with a voltage 425-a received at the source of the first transistor 405. In other examples, the first transistor 405 may be configured to isolate access line 455 from voltage 425-a. That is, the first transistor 405 is configured to supply voltage 425-a to access line 455 when activated and to isolate voltage 425-a from access line 455 when deactivated. The first transistor 405 may be an example of a PMOS transistor. In such examples, the first transistor 405 may be activated when voltage 425-a exceeds the sum of voltage 430-a received at the gate of the first transistor 405 and a threshold voltage of the first transistor 405. In some examples, the first transistor 405 may be associated with a second stage of the decoder (e.g., reference...). Figure 3 The second part of the second stage 310-b is coupled. That is, the voltage 425-a at the source of the first transistor 405 can be received from the second part of the second stage. In circuit 400, a ground voltage can be applied to the gate of the first transistor 405, and a positive voltage (VPP) can be applied to the source of the first transistor 405. The difference between the positive voltage and the ground voltage can exceed the threshold voltage of the first transistor 405, thereby activating the first transistor 405.

[0057] In an example of circuit 400, the second transistor 410 may be configured to isolate access line 455 from voltage 435-a. In other examples, the second transistor 410 may be configured to supply access line 455 with voltage 435-a received at the source of the second transistor 410. That is, the second transistor 410 is configured to supply voltage 435-a to access line 455 when activated and to isolate voltage 435-a from access line 455 when deactivated. The second transistor 410 may be an example of an NMOS transistor. In such examples, the second transistor 410 may be activated when voltage 440-a at the gate of the second transistor 410 exceeds the sum of voltage 435-a and threshold voltage of the second transistor 410. In some examples, the second transistor 410 may be associated with a second stage of the decoder (e.g., reference...). Figure 3 The first part of the second stage 310-a is coupled. That is, the voltage 435-a at the source of the first transistor 405 can be received from the first part of the second stage. In circuit 400, a ground voltage can be applied to the gate of the second transistor 410, and the source of the second transistor 410 can float (e.g., it can be isolated from one or more voltage sources through the second stage of the decoder). The difference between the positive voltage and the ground voltage can be less than the threshold voltage of the second transistor 410, thereby deactivating the second transistor 410.

[0058] The third transistor may be configured to supply access line 455 with a voltage 450-a (e.g., a ground voltage) received at the source of the third transistor 415. In other instances, the third transistor 415 may be configured to isolate the voltage 450-a from access line 455. In some instances, the third transistor 415 may be configured to prevent interference to adjacent access lines (not shown). That is, the third transistor 415 may be configured to clamp when the access line is not accessed. The third transistor 415 may be an example of an NMOS transistor. During operation, as shown in circuit 400, the third transistor 415 may be deactivated based on the application of a ground voltage to the gate of the third transistor 415.

[0059] Access line 455 can be configured to drive voltage 420-a to a memory cell coupled to access line 455. In some instances, access line 455 can be configured to activate a memory cell. In an example of circuit 400, voltage 420-a can be an example of a positive voltage (VPP).

[0060] In some instances, scaling down the decoder and circuitry 400 in proportion to the shrinking of the memory array can be challenging. For example, it may be difficult to scale down the decoder and circuitry 400 while still providing the appropriate voltage to the memory array. That is, memory devices using high voltages may include transistors with oxides capable of isolating the high voltage from the access lines. In some instances, it may be difficult to scale down the size and dimensions of the oxides while still isolating the high voltage. Additionally, in some instances, it may be difficult to design a decoder that scales down to the memory array and prevents interference with adjacent access lines. In other instances, the complexity of the decoder may make it even more difficult to scale down.

[0061] Circuit 400 allows the decoder to be scaled down proportionally to the memory array. For example, the decoder and circuit 400 can use a smaller voltage than other solutions (e.g., half the voltage). Additionally, circuit 400 simplifies voltage routing to the access lines because it is configured to provide positive, negative, or ground voltage to the access lines—for example, a single circuit 400 can be used to provide voltage to the access lines. In some instances, circuit 400 can also reduce excessive power consumption. For example, the first transistor 405, the second transistor 410, or the third transistor 415 can sometimes be activated or deactivated by the existing voltage supplied to the source of each transistor, rather than activating each transistor each time by supplying a voltage to its gate. The third transistor 415 can also clamp access line 455 and prevent interference with adjacent access lines.

[0062] In some instances, the memory device may receive a first command associated with a first access operation. The decoder may decode the first command and activate the second part of the third level (e.g., refer to...). Figure 3 The transistor in the second part of the third stage 315-b (described) is activated, and the second transistor in the second part of the second stage is activated. Therefore, the circuit 400 can be powered by a first voltage source (e.g., reference). Figure 3 The described voltage source 320-b) supplies a positive voltage 425-a to the source of the first transistor 405. Circuit 400 may also supply a voltage 430-a with a value of zero (0) volts at the gate of the first transistor 405. That is, the gate of the first transistor 405 may not be supplied with voltage. In such an example, voltage 425-a may exceed the sum of voltage 430-a and the threshold voltage of the first transistor 405, thereby activating the first transistor 405. Additionally, the decoder may deactivate the first part of the third stage (e.g., see reference...). Figure 3The second part of the third stage 315-a described herein) and some or all of the transistors in the first part of the second stage. Therefore, circuit 400 can float the source of the second transistor 410 via the second stage (e.g., it can be isolated from one or more voltage sources). That is, the second transistor 410 can be isolated from the second voltage source (e.g., 320-a) and receive a voltage 435-a floating on the supply line coupling the second transistor 410 to the second stage. The second transistor 410 can also be supplied with a voltage 440-a having a value of zero (0) volts at its gate. In such an example, voltage 440-a can be less than the sum of voltage 435-a and the threshold voltage of the second transistor 410, thereby deactivating the second transistor 410 and isolating access line 455 from the voltage from the second voltage source.

[0063] Alternatively, circuit 400 may supply a ground voltage 450-a at the source of third transistor 415. Third transistor 415 may be supplied with a voltage 445-a having a value of zero (0) volts at its gate. In such instances, voltage 445-a may be less than the sum of voltage 450-a and the threshold voltage of the third transistor, thereby deactivating third transistor 415. Therefore, during the first access operation, circuit 400 may drive access line 455 to the same positive voltage 420-a as the voltage 425-a received at the source of first transistor 405. In some instances, the first command may be referred to as a select-high operation. In such instances, voltage 420-a may have a value of 2.6 volts to activate the memory cell coupled to access line 455.

[0064] Figure 4B An example of circuitry 401 is shown when the memory device receives a second command. For example, the memory device may receive a second command associated with a second access operation. Circuitry 401 may be an example of a circuit configuration that applies a negative voltage (VNN) to access line 455.

[0065] The decoder can decode the second command and activate the first part of the third level (e.g., refer to...). Figure 3The transistors in the first part of the third stage (315-a) are described, and the second transistor in the first part of the second stage is activated. Therefore, circuit 401 can supply a negative voltage 435-b at the source of the second transistor 410 from a second voltage source. Circuit 401 can also supply a voltage 440-b with a value of zero (0) volts at the gate of the second transistor 410. That is, the gate of the second transistor 410 may not be supplied with voltage. In such an example, voltage 440-b may exceed the sum of voltage 435-b and the threshold voltage of the second transistor 410, thereby activating the second transistor 410. Additionally, the decoder can deactivate some or all of the transistors in the second part of the third stage and the second part of the second stage. Therefore, circuit 401 can float the source of the first transistor 405 through the second stage (e.g., it may be isolated from one or more voltage sources). That is, the first transistor 405 may be isolated from the first voltage source and receive a voltage 425-b floating on the routing line that couples the first transistor 405 to the second stage. Circuit 401 may also supply a voltage 430-b with a value of zero (0) volts at the gate of the first transistor 405. In such an example, voltage 425-b may be less than the sum of voltage 430-a and the threshold voltage of the first transistor 405, thereby deactivating the first transistor 405 and isolating access line 455 from the voltage from the first voltage source.

[0066] Additionally, circuit 401 may supply a ground voltage 450-b at the source of the third transistor 415. Circuit 401 may supply a voltage 445-b with a value of zero (0) volts at the gate of the third transistor. In such instances, voltage 445-b may be less than the sum of voltage 450-b and the threshold voltage of the third transistor, thereby deactivating the third transistor 415. Therefore, during the second access operation, circuit 401 may drive access line 455 to the same negative voltage 420-b as the voltage 435-b received at the source of the second transistor 410. In some instances, the second command may be referred to as a select-low operation. In such instances, voltage 420-b may have a value of -2.6 volts to activate the memory cell coupled to access line 455.

[0067] Figure 4CAn example of circuitry 402 is shown when the memory device is idle—for example, during a period between a first access operation and a second access operation. Circuitry 402 may be an example of a circuit configuration that applies ground to access line 455 (e.g., when the access line is not the target access line during operation). That is, access line 455 may be idle during a period in which no access operation is performed. The decoder may deactivate some or all of the transistors in the second and third stages. Thus, circuitry 402 may float the source of the first transistor 405 and the source of the second transistor 410 via the second stage (e.g., it may be isolated from one or more voltage sources). When the memory device is idle, circuitry 402 may supply voltages to the gates of the first transistor 405 and the second transistor 410. For example, circuitry 402 may supply a positive voltage 430-c to the gate of the first transistor 405 and a negative voltage 440-c to the gate of the second transistor 410. In such an example, voltage 425-c may be less than the sum of voltage 430-a and the threshold voltage of the first transistor 405, thereby deactivating the first transistor 405. Additionally, voltage 440-c may be less than the sum of voltage 435-c and the threshold voltage of the second transistor 410, thereby deactivating the second transistor 410.

[0068] Circuit 402 may also supply a positive voltage 445-c to the gate of the third transistor 415. The third transistor 415 may also receive a ground voltage 450-c at its source. In such an example, voltage 445-c may exceed the sum of voltage 450-c and the threshold voltage of the third transistor 415, thereby activating the third transistor 415. Therefore, when the memory device is idle, the third transistor 415 may couple a ground voltage source to access line 455, thereby grounding access line 455 and driving the ground voltage 420-c to the memory cell coupled to access line 455.

[0069] In other words, the memory device can receive a first command associated with a select-high operation. In response to the command, the decoder can activate transistors in the second part of the third stage and transistors in the second stage to bias the source of the first transistor 405 using a positive voltage 425-a from the first voltage source. During the execution of the first command, the decoder can also deactivate some or all of the transistors in the first part of the third stage and the first part of the second stage, causing the source of the second transistor to float, and thereby deactivating the second transistor 410. Therefore, circuit 402 can activate the first transistor 405 to supply a positive voltage 420-a to the access line 455 during the first access operation.

[0070] When the memory device receives a second command associated with a select-low operation, the decoder can activate transistors in the first part of the third stage and transistors in the first part of the second stage to bias the source of the second transistor 410 with a negative voltage from a second voltage source. During the execution of the second command, the decoder can also deactivate some or all of the transistors in the second part of the second stage and the second part of the third stage, causing the source of the first transistor 405 to float, thereby deactivating the first transistor 405. Therefore, circuit 402 can activate the second transistor 410 to supply a negative voltage 420-b to the access line 455 during the second access operation.

[0071] When the memory device has executed the first command or the second command, the decoder can deactivate some or all of the transistors in the first and second stages, causing the source of the first transistor 405 to float and the source of the second transistor 410 to float. Circuit 402 can also supply voltage 430-c to the gate of the first transistor 405 and voltage 440-c to the gate of the second transistor 410. Therefore, circuit 402 can deactivate the first transistor 405 and the second transistor 410. Additionally, circuit 402 can supply voltage 445-c to the gate of the third transistor 415 to activate the third transistor 415. In such an example, the third transistor 415 can couple a ground voltage 450-c from a ground voltage source to the access line 455.

[0072] Figure 5 A block diagram 500 illustrates a memory device 520 with a decoder architecture supporting the memory device according to an example disclosed herein. The memory device 520 may be a reference. Figure 1 -4. Examples of aspects of the memory device described herein. Memory device 520 or its various components may be examples of building blocks for implementing various aspects of the decoder architecture of the memory device as described herein. For example, memory device 520 may include receiving component 525, biasing component 530, activation component 535, deactivation component 540, decoding component 545, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0073] The receiving component 525 may be configured or otherwise supported as a means for receiving commands associated with memory cells coupled to the access line. In some instances, the receiving component 525 may be configured or otherwise supported as a means for receiving a second command associated with a memory cell coupled to the access line.

[0074] The biasing component 530 may be configured or otherwise support a component for: at least partially based on a received command, biasing the source of a first transistor to a first voltage exceeding a second voltage at the gate of the first transistor and a first threshold voltage of the first transistor to activate the first transistor, wherein a second stage of the decoder includes the first transistor. In some instances, the biasing component 530 may be configured or otherwise support a component for: at least partially based on a received command, biasing the source of a second transistor to a third voltage at the first stage of the decoder to deactivate the second transistor, wherein a fourth voltage at the gate of the second transistor is less than the second voltage and the second threshold voltage of the second transistor, and wherein a second stage of the decoder includes the second transistor. In some cases, the biasing component 530 may be configured or otherwise support a component for: supplying a positive voltage to an access line at least partially based on biasing the source of the first transistor and biasing the source of the second transistor.

[0075] In some examples, bias component 530 may be configured or otherwise support a component for: at least partially based on a command, biasing the source of a first transistor to a fifth voltage less than a second voltage at the gate of the first transistor and a first threshold voltage of the first transistor via a first stage of the decoder to deactivate the first transistor. In some examples, bias component 530 may be configured or otherwise support a component for: at least partially based on a received command, biasing the source of a second transistor to a sixth voltage via a first stage of the decoder to activate the second transistor, wherein a fourth voltage at the gate of the second transistor exceeds the sixth voltage and the second threshold voltage of the second transistor. In some cases, bias component 530 may be configured or otherwise support a component for: at least partially based on biasing the source of the first transistor and biasing the source of the second transistor to supply a negative voltage to the access line.

[0076] In some instances, biasing component 530 may be configured or otherwise support a component that, after executing a command, biases the gate of a first transistor to a fifth voltage to deactivate the first transistor, wherein the fifth voltage and a first threshold voltage of the first transistor are less than a sixth voltage at the source of the first transistor. In some cases, biasing component 530 may be configured or otherwise support a component that, after executing a command, biases the gate of a second transistor to a seventh voltage to deactivate the second transistor, wherein the seventh voltage is less than a third voltage at the source of the second transistor and a second threshold voltage of the second transistor. In some examples, biasing component 530 may be configured or otherwise support a component that isolates access lines from positive or negative voltages, at least partially based on biasing the gate of the first transistor and biasing the gate of the second transistor.

[0077] In some examples, bias component 530 may be configured or otherwise support a fifth voltage, after command execution, biasing the gate of the third transistor to an eighth voltage exceeding the source voltage of the third transistor and a third threshold voltage of the third transistor, wherein the second stage of the decoder includes the third transistor. In some instances, bias component 530 may be configured or otherwise support a fifth voltage, at least partially based on biasing the gate of the third transistor, to supply an eighth voltage to the access line. In some cases, bias component 530 may be configured or otherwise support a sixth voltage as a ground voltage associated with a reset operation.

[0078] In some cases, bias component 530 may be configured or otherwise support a component for supplying a second voltage to the gate of the first transistor such that the second voltage at the gate of the first transistor exceeds the sum of the first voltage and the first threshold voltage of the first transistor. In some instances, bias component 530 may be configured or otherwise support a component for supplying a fourth voltage to the gate of the second transistor such that the fourth voltage at the gate of the second transistor is less than the sum of the second voltage and the second threshold voltage of the second transistor.

[0079] In some instances, activation component 535 may be configured or otherwise support a component for: activating a third transistor of a first stage of the decoder, at least in part based on a received command, the third transistor being coupled to the first transistor and a fourth transistor of the third stage of the decoder. In some cases, activation component 535 may be configured or otherwise support a component for: activating the fourth transistor of the third stage to couple the third transistor of the first stage to a voltage source supplying a positive voltage, wherein the source of the first transistor is biased at least in part based on the activation of the third transistor and the activation of the fourth transistor.

[0080] In some examples, the deactivation component 540 may be configured or otherwise support components for: deactivating, at least in part, a third transistor of a first stage of the decoder, coupled to a second transistor and a fourth transistor of a third stage of the decoder, based on a received command. In some cases, the deactivation component 540 may be configured or otherwise support components for: deactivating, to decouple, the fourth transistor of the third stage from a voltage source supplying a negative voltage, wherein the source of the second transistor is biased at least in part based on the deactivation of the third transistor and the deactivation of the fourth transistor.

[0081] In some examples, the decoding component 545 may be configured or otherwise support components for decoding a memory address associated with a command, wherein the source of the first transistor and the source of the second transistor of the biased second stage are at least partially based on the decoded memory address.

[0082] Figure 6 A flowchart illustrating an example disclosed herein shows a method 600 supporting a decoder architecture for a memory device. Operation of method 600 can be implemented by the memory device or its components described herein. For example, operation of method 600 can be provided by reference to... Figures 1-5 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0083] At 605, the method may include receiving a command associated with a memory cell coupled to an access line. Operation 605 may be performed according to the examples disclosed herein. In some instances, aspects of operation 605 may be referenced... Figure 5 The described receiving component 525 is executed.

[0084] At 610, the method may include, at least in part, based on receiving a command, activating the first transistor by biasing its source to a first voltage exceeding a second voltage at the gate of the first transistor and a first threshold voltage of the first transistor via a first stage of a decoder, wherein the second stage of the decoder includes the first transistor. Operation 610 may be performed according to the examples disclosed herein. In some examples, aspects of operation 610 may be derived from references... Figure 5 The described bias component 530 is executed.

[0085] At 615, the method may include, at least in part, based on receiving a command, biasing the source of the second transistor to a third voltage via a first stage of the decoder to deactivate the second transistor, wherein a fourth voltage at the gate of the second transistor is less than the second voltage and a second threshold voltage of the second transistor, and wherein a second stage of the decoder includes the second transistor. Operation 615 may be performed according to the examples disclosed herein. In some examples, aspects of operation 615 may be referenced from... Figure 5 The described bias component 530 is executed.

[0086] At 620, the method may include supplying a positive voltage to the access line based at least in part on biasing the source of a first transistor and biasing the source of a second transistor. Operation 620 may be performed according to the examples disclosed herein. In some examples, aspects of operation 620 may be referenced from... Figure 5 The described bias component 530 is executed.

[0087] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command associated with a memory cell coupled to an access line; at least in part based on receiving the command, biasing the source of a first transistor to a first voltage exceeding a second voltage at the gate of the first transistor and a first threshold voltage of the first transistor via a first stage of a decoder to activate the first transistor, wherein a second stage of the decoder includes the first transistor; at least in part based on receiving the command, biasing the source of a second transistor to a third voltage via the first stage of the decoder to deactivate the second transistor, wherein a fourth voltage at the gate of the second transistor is less than the second voltage and the second threshold voltage of the second transistor, and wherein a second stage of the decoder includes the second transistor; and at least in part based on biasing the source of the first transistor and biasing the source of the second transistor to supply a positive voltage to the access line.

[0088] Examples of the methods 600 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for: receiving a second command associated with a memory cell coupled to an access line; deactivating a first transistor by biasing the source of a first transistor to a fifth voltage less than a second voltage of the gate of the first transistor and a first threshold voltage of the first transistor, at least in part based on the command, via a first stage of a decoder; activating a second transistor by biasing the source of a second transistor to a sixth voltage, at least in part based on the received command, via a first stage of a decoder, wherein a fourth voltage of the gate of the second transistor exceeds the sixth voltage and the second threshold voltage of the second transistor; and supplying a negative voltage to the access line by biasing the source of the first transistor and the source of the second transistor, at least in part based on biasing the source of the first transistor and biasing the source of the second transistor.

[0089] In some cases of the method 600 and apparatus described herein, after executing a command, the gate of the first transistor is biased to a fifth voltage to deactivate the first transistor, wherein the fifth voltage and a first threshold voltage of the first transistor may be less than a sixth voltage at the source of the first transistor; after executing a command, the gate of the second transistor is biased to a seventh voltage to deactivate the second transistor, wherein the seventh voltage may be less than a third voltage at the source of the second transistor and a second threshold voltage of the second transistor; and the access line is isolated from the positive or negative voltage, at least in part, based on biasing the gate of the first transistor and biasing the gate of the second transistor.

[0090] In some instances of the method 600 and device described herein, after executing a command, the gate of the third transistor is biased to an eighth voltage beyond the source of the third transistor and a fifth voltage greater than the third threshold voltage of the third transistor, wherein the second stage of the decoder includes the third transistor, and the eighth voltage is supplied to the access line at least in part based on the biasing of the gate of the third transistor.

[0091] In some examples of the method 600 and device described herein, the sixth voltage may be the ground voltage associated with the reset operation.

[0092] Some aspects of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: activating a third transistor of a first stage of a decoder, coupled to the first transistor and a fourth transistor of the third stage of the decoder, at least in part based on receiving a command; and activating the fourth transistor of the third stage to couple the third transistor of the first stage to a voltage source supplying a positive voltage, wherein the source of the first transistor may be biased at least in part based on activating the third transistor and activating the fourth transistor.

[0093] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: at least in part based on receiving a command, deactivating a third transistor of a first stage of a decoder, the third transistor being coupled to a second transistor and a fourth transistor of a third stage of the decoder; and deactivating the fourth transistor of the third stage to decouple the third transistor from a voltage source supplying a negative voltage, wherein the source of the second transistor may be biased at least in part based on deactivating the third transistor and deactivating the fourth transistor.

[0094] Examples of the methods 600 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for decoding a memory address associated with a command, wherein the source of the biased first transistor and the source of the second transistor of the second stage may be at least partially based on the decoded memory address.

[0095] In some cases of the method 600 and apparatus described herein, the second voltage of the gate of the first transistor exceeds the sum of the first voltage and the first threshold voltage of the first transistor, and the fourth voltage of the gate of the second transistor may be less than the sum of the second voltage and the second threshold voltage of the second transistor.

[0096] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0097] Describe an apparatus. The apparatus may include: a memory array including memory cells and access lines coupled to the memory cells; a decoder including a first stage and a second stage, the decoder being configured to supply a first voltage to the access lines during a first access operation and to supply a second voltage to the access lines during a second access operation, the second stage of the decoder including: a first transistor configured to supply the first voltage to the access lines during the first access operation based at least in part on a third voltage at the source of the first transistor exceeding a fourth voltage at the gate of the first transistor and a first threshold voltage of the first transistor; and a second transistor configured to supply the second voltage to the access lines during the second access operation based at least in part on a fifth voltage at the gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage of the second transistor.

[0098] In some examples of the device, the second transistor may be configured to isolate the voltage source of the second voltage from the access line during the first access operation, based at least in part on the fact that the fifth voltage at the gate of the second transistor is less than the seventh voltage at the source of the second transistor and the second threshold voltage of the second transistor.

[0099] In some cases of the device, the first transistor may be configured to isolate the voltage source of the first voltage from the access line during the second access operation, based at least in part on the fact that the seventh voltage at the source of the first transistor is less than the fourth voltage at the gate of the first transistor and the first threshold voltage of the first transistor.

[0100] In some instances of the device, the decoder may be further configured to supply a seventh voltage to the access line during a portion of the duration between performing an access operation associated with the access line, the first transistor may be configured to isolate the first voltage supply of the first voltage from the access line during the portion of the duration based at least in part on an eighth voltage at the source of the first transistor being less than a ninth voltage at the gate of the first transistor and a first threshold voltage of the first transistor, and the second transistor may be configured to isolate the second voltage supply of the second voltage from the access line during the portion of the duration based at least in part on a tenth voltage at the gate of the second transistor being less than an eleventh voltage at the source of the second transistor and a second threshold voltage of the second transistor.

[0101] In some examples of the device, the device may further include a third transistor configured to supply a seventh voltage to the access line during said portion of the duration, based at least in part on a ninth voltage at the gate of the third transistor exceeding a seventh voltage at the source of the third transistor and a third threshold voltage of the third transistor.

[0102] In some cases of the device, the first stage of the decoder further includes: a first portion configured to supply a first voltage to an access line, the first portion including a third transistor coupled to a first voltage source and a first node configured to supply the first voltage, and a fourth transistor coupled to the first node and a second stage of the decoder, wherein the third transistor and the fourth transistor are configurable to be activated during a first access operation; and a second portion configured to supply a second voltage to the access line, the second portion including a fifth transistor coupled to a second voltage source and a second node configured to supply the second voltage, and a sixth transistor coupled to the second node and a second stage of the decoder, wherein the fifth transistor and the sixth transistor are configurable to be activated during a second access operation.

[0103] In some instances of the device, the device may further include a plurality of second stages, each coupled to a third transistor of a first stage and a fourth transistor of a second stage, each of the plurality of second stages being coupled to an access line of a plurality of access lines, the plurality of second stages comprising the second stage and the plurality of access lines comprising the access line.

[0104] In some embodiments of the device, the device may further include: a fifth transistor of a third stage of the decoder, the fifth transistor being coupled to a first voltage source configured to supply a first voltage to a third transistor of a first stage of the decoder, wherein the decoder may be configured to activate a first transistor of a second stage, a third transistor of a first stage, and a fifth transistor of a third stage to supply a first voltage to an access line during a first access operation; and a sixth transistor of a third stage of the decoder, the sixth transistor being coupled to a second voltage source configured to supply a second voltage to a fourth transistor of a first stage of the decoder, wherein the decoder may be configured to activate a second transistor of a second stage, a fourth transistor of a first stage, and a sixth transistor of a first stage to supply a second voltage to an access line during a second access operation.

[0105] In some examples of the device, the transistors of the first, second, and third stages of the decoder may be activated at least in part during the first access operation based on the received memory address associated with the memory cell.

[0106] In some instances of the device, the first voltage can be a positive voltage, and the second voltage can be a negative voltage.

[0107] In some cases of the device, the first transistor can be a PMOS transistor and the second transistor can be an NMOS transistor.

[0108] Describe another device. The device may include: a memory array comprising memory cells and access lines coupled to the memory cells; a decoder comprising a first stage and a second stage, the second stage comprising a first transistor and a second transistor; and a controller coupled to the memory array and the decoder and configured to: receive a command associated with the memory cells coupled to the access lines; at least in part based on receiving the command, bias the source of the first transistor through the first stage of the decoder to a first voltage exceeding a second voltage at the gate of the first transistor and a first threshold voltage of the first transistor to activate the first transistor, wherein the second stage of the decoder comprises the first transistor; at least in part based on receiving the command, bias the source of the second transistor through the first stage of the decoder to a third voltage to deactivate the second transistor, wherein a fourth voltage at the gate of the second transistor is less than the second voltage and the second threshold voltage of the second transistor, and wherein the second stage of the decoder comprises the second transistor; and supply a positive voltage to the access lines at least in part based on biasing the source of the first transistor and biasing the source of the second transistor.

[0109] In some instances of the device, the controller may be further configured to receive a second command associated with a memory cell coupled to the access line; at least in part based on the command, bias the source of the first transistor to a fifth voltage less than a second voltage of the gate of the first transistor and a first threshold voltage of the first transistor via a first stage of the decoder to deactivate the first transistor; at least in part based on the received command, bias the source of the second transistor to a sixth voltage via a first stage of the decoder to activate the second transistor, wherein a fourth voltage of the gate of the second transistor exceeds the sixth voltage and the second threshold voltage of the second transistor; and at least in part based on biasing the source of the first transistor and biasing the source of the second transistor, supply a negative voltage to the access line.

[0110] In some cases of the device, the controller may be further configured to: bias the gate of the first transistor to a fifth voltage after executing a command to deactivate the first transistor, wherein the fifth voltage and the first threshold voltage of the first transistor may be less than a sixth voltage at the source of the first transistor; bias the gate of the second transistor to a seventh voltage after executing a command to deactivate the second transistor, wherein the seventh voltage may be less than a third voltage at the source of the second transistor and a second threshold voltage of the second transistor; and isolate the access line from the positive or negative voltage, at least in part based on biasing the gate of the first transistor and biasing the gate of the second transistor.

[0111] In some instances of the device, the controller may be further configured to: bias the gate of the third transistor to a fifth voltage exceeding an eighth voltage at the source of the third transistor and a third threshold voltage of the third transistor after executing a command; and supply the eighth voltage to the access line at least in part based on biasing the gate of the third transistor.

[0112] In some instances of the device, the device may further include a third transistor of a first stage of the decoder, a fourth transistor of the third stage of the decoder, and a voltage source supplying a positive voltage, wherein the controller may be further configured to: activate the third transistor of the first stage of the decoder, coupled to the first transistor and the fourth transistor, at least in part based on receiving the command; and activate the fourth transistor of the third stage of the decoder to couple the third transistor to the voltage source supplying the positive voltage, wherein the controller is configured to bias the source of the first transistor at least in part based on activating the third transistor and activating the fourth transistor.

[0113] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0114] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0115] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When, for example, one component of a controller couples other components together, that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0116] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0117] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure with two dimensions greater than the third, such as a thin film. Layers or levels may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0118] As used in this article, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but is close enough to obtain the advantage of the feature.

[0119] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact for memory cells or other components of a memory array. Electrodes can include traces, wires, conductive lines, conductive layers, etc., that provide conductive paths between elements or components of a memory array.

[0120] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0121] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0122] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0123] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a long dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0124] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0125] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0126] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0127] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these items are also included within the scope of computer-readable media.

[0128] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory array comprising memory cells and access lines coupled to the memory cells; and A decoder, comprising a first stage and a second stage, the decoder being configured to supply a first voltage to the access line during a first access operation and a second voltage to the access line during a second access operation, the first stage of the decoder comprising: First node; A third transistor is coupled to the first node and to a first voltage source configured to supply the first voltage; A fourth transistor, coupled to the first node and to the second stage of the decoder, wherein the third transistor and the fourth transistor are configured to be activated during the first access operation; Second node; A fifth transistor, coupled to the second node and coupled to a second voltage source configured to supply the second voltage; and A sixth transistor, coupled to the second node and to the second stage of the decoder, wherein the fifth and sixth transistors are configured to be activated during the second access operation; and The second stage of the decoder includes: A first transistor, configured to supply the first voltage to the access line during the first access operation based at least in part on a third voltage at the source of the first transistor exceeding a fourth voltage at the gate of the first transistor and a first threshold voltage of the first transistor; and The second transistor is configured to supply the second voltage to the access line during the second access operation, based at least in part on a fifth voltage at the gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage of the second transistor.

2. The device according to claim 1, wherein: The second transistor is configured to isolate the voltage source of the second voltage from the access line during the first access operation, based at least in part on the fact that the fifth voltage at the gate of the second transistor is less than the seventh voltage at the source of the second transistor and the second threshold voltage of the second transistor.

3. The device according to claim 1, wherein: The first transistor is configured to isolate the voltage source of the first voltage from the access line during the second access operation, based at least in part on the fact that the seventh voltage at the source of the first transistor is less than the fourth voltage at the gate of the first transistor and the first threshold voltage of the first transistor.

4. The device according to claim 1, further comprising: A plurality of second stages, each coupled to a corresponding third transistor and a corresponding fourth transistor of the first stage, each of the plurality of second stages being coupled to one of a plurality of access lines, the plurality of second stages comprising the second stage, and the plurality of access lines comprising the access lines.

5. The device according to claim 4, further comprising: The fifth transistor of the third stage of the decoder is coupled to a first voltage source configured to supply the first voltage to the corresponding third transistor of the first stage of the decoder, wherein the decoder is configured to activate the first transistor of the second stage, the third transistor of the first stage, and the fifth transistor of the third stage to supply the first voltage to the access line during the first access operation. as well as The sixth transistor of the third stage of the decoder is coupled to a second voltage source configured to supply the second voltage to the corresponding fourth transistor of the first stage of the decoder, wherein the decoder is configured to activate the second transistor of the second stage, the fourth transistor of the first stage, and the sixth transistor of the first stage to supply the second voltage to the access line during the second access operation.

6. The device of claim 5, wherein the transistors of the first, second, and third stages of the decoder are activated at least in part during the first access operation based on receiving a memory address associated with the memory cell.

7. The device of claim 1, wherein the first transistor is a p-type metal-oxide-semiconductor (PMOS) transistor and the second transistor is an n-type metal-oxide-semiconductor (NMOS) transistor.

8. An apparatus comprising: A memory array comprising memory cells and access lines coupled to the memory cells; as well as A decoder, comprising a first stage and a second stage, the decoder being configured to supply a first voltage to the access line during a first access operation and a second voltage to the access line during a second access operation, the second stage of the decoder comprising: A first transistor is configured to supply the first voltage to the access line during the first access operation based at least in part on a third voltage at the source of the first transistor exceeding a fourth voltage at the gate of the first transistor and a first threshold voltage of the first transistor, wherein the first transistor is configured to isolate the first voltage supply of the first voltage from the access line for a portion of the duration based at least in part on an eighth voltage at the source of the first transistor being less than a ninth voltage at the gate of the first transistor and the first threshold voltage of the first transistor; as well as A second transistor is configured to supply the second voltage to the access line during the second access operation based at least in part on a fifth voltage at the gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage of the second transistor, wherein the second transistor is configured to isolate the second voltage supply of the second voltage from the access line during the portion of the duration based at least in part on a tenth voltage at the gate of the second transistor being less than an eleventh voltage at the source of the second transistor and the second threshold voltage of the second transistor.

9. The device according to claim 8, further comprising: A third transistor is configured to supply the seventh voltage to the access line during the portion of the duration based at least in part on the ninth voltage at the gate of the third transistor exceeding the seventh voltage at the source of the third transistor and the third threshold voltage of the third transistor.

10. An apparatus comprising: A memory array comprising memory cells and access lines coupled to the memory cells; as well as A decoder, comprising a first stage and a second stage, the decoder being configured to supply a first voltage to the access line during a first access operation and a second voltage to the access line during a second access operation, wherein the first voltage is a positive voltage and the second voltage is a negative voltage, the second stage of the decoder comprising: A first transistor, configured to supply the first voltage to the access line during the first access operation based at least in part on a third voltage at the source of the first transistor exceeding a fourth voltage at the gate of the first transistor and a first threshold voltage of the first transistor. as well as The second transistor is configured to supply the second voltage to the access line during the second access operation, based at least in part on a fifth voltage at the gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage of the second transistor.

11. A method comprising: Receive commands associated with memory cells coupled to access lines; Based at least in part on receiving the command, the source of the first transistor is biased to a first voltage exceeding the second voltage of the gate of the first transistor and the first threshold voltage of the first transistor by the first stage of the decoder to activate the first transistor, wherein the second stage of the decoder includes the first transistor; Based at least in part on receiving the command, the source of the second transistor is biased to a third voltage through the first stage of the decoder to deactivate the second transistor, wherein a fourth voltage of the gate of the second transistor is less than the second voltage and a second threshold voltage of the second transistor, and wherein the second stage of the decoder includes the second transistor; as well as A positive voltage is supplied to the access line, at least in part, based on biasing the source of the first transistor and biasing the source of the second transistor.

12. The method of claim 11, further comprising: Receive a second command associated with the memory cell coupled to the access line; Based at least in part on the command, the source of the first transistor is biased to a fifth voltage less than the second voltage of the gate of the first transistor and the first threshold voltage of the first transistor by the first stage of the decoder to deactivate the first transistor; Based at least in part on receiving the command, the source of the second transistor is biased to a sixth voltage by the first stage of the decoder to activate the second transistor, wherein the fourth voltage of the gate of the second transistor exceeds the sixth voltage and the second threshold voltage of the second transistor; as well as A negative voltage is supplied to the access line, at least in part, based on biasing the source of the first transistor and biasing the source of the second transistor.

13. The method of claim 11, further comprising: After the command is executed, the gate of the first transistor is biased to a fifth voltage to deactivate the first transistor, wherein the fifth voltage and the first threshold voltage of the first transistor are less than a sixth voltage at the source of the first transistor. After the command is executed, the gate of the second transistor is biased to a seventh voltage to deactivate the second transistor, wherein the seventh voltage is less than the third voltage at the source of the second transistor and the second threshold voltage of the second transistor; as well as The access line is isolated from the positive or negative voltage, at least in part, by biasing the gate of the first transistor and the gate of the second transistor.

14. The method of claim 13, further comprising: After the command is executed, the gate of the third transistor is biased to a fifth voltage exceeding the eighth voltage at the source of the third transistor and the third threshold voltage of the third transistor, wherein the second stage of the decoder includes the third transistor; as well as The eighth voltage is supplied to the access line at least in part based on the gate of the third transistor being biased.

15. The method of claim 14, wherein the sixth voltage is a ground voltage associated with a reset operation.

16. The method of claim 11, further comprising: At least in part based on receiving the command, the third transistor of the first stage of the decoder is activated, the third transistor being coupled to the first transistor and the fourth transistor of the third stage of the decoder; as well as The fourth transistor of the third stage is activated to couple the third transistor of the first stage to a voltage source supplying the positive voltage, wherein the source of the first transistor is biased at least in part based on activating the third transistor and activating the fourth transistor.

17. The method of claim 11, further comprising: Based at least in part on receiving the command, the third transistor of the first stage of the decoder, which is coupled to the second transistor and the fourth transistor of the third stage of the decoder, is deactivated. as well as The activation of the fourth transistor in the third stage is deactivated to decouple the third transistor from the voltage source supplying the negative voltage, wherein the source of the second transistor is biased at least in part based on the deactivation of the third transistor and the deactivation of the fourth transistor.

18. The method of claim 11, further comprising: Decoding the memory address associated with the command, wherein the source of the first transistor and the source of the second transistor of the second stage are biased at least in part based on decoding the memory address.

19. The method according to claim 11, wherein: The second voltage at the gate of the first transistor exceeds the sum of the first voltage and the first threshold voltage of the first transistor; and The fourth voltage at the gate of the second transistor is less than the sum of the second voltage and the second threshold voltage of the second transistor.

20. An apparatus comprising: A memory array comprising memory cells and access lines coupled to the memory cells; The decoder includes a first stage and a second stage, the second stage including a first transistor and a second transistor; as well as The controller, coupled to the memory array and the decoder, is configured to: Receive commands associated with the memory cell coupled to the access line; Based at least in part on receiving the command, the source of the first transistor is biased to a first voltage exceeding the gate voltage of the first transistor and the first threshold voltage of the first transistor by the first stage of the decoder to activate the first transistor, wherein the second stage of the decoder includes the first transistor; Based at least in part on receiving the command, the source of the second transistor is biased to a third voltage by the first stage of the decoder to deactivate the second transistor, wherein a fourth voltage of the gate of the second transistor is less than the second voltage and a second threshold voltage of the second transistor, and wherein the second stage of the decoder includes the second transistor; as well as A positive voltage is supplied to the access line, at least in part, based on biasing the source of the first transistor and biasing the source of the second transistor.

21. The device of claim 20, wherein the controller is further configured to: Receive a second command associated with the memory cell coupled to the access line; Based at least in part on the command, the source of the first transistor is biased to a fifth voltage less than the second voltage of the gate of the first transistor and the first threshold voltage of the first transistor by the first stage of the decoder to deactivate the first transistor; Based at least in part on receiving the command, the source of the second transistor is biased to a sixth voltage by the first stage of the decoder to activate the second transistor, wherein the fourth voltage of the gate of the second transistor exceeds the sixth voltage and the second threshold voltage of the second transistor; as well as A negative voltage is supplied to the access line, at least in part, based on biasing the source of the first transistor and biasing the source of the second transistor.

22. The device of claim 20, wherein the controller is further configured to: After the command is executed, the gate of the first transistor is biased to a fifth voltage to deactivate the first transistor, wherein the fifth voltage and the first threshold voltage of the first transistor are less than a sixth voltage at the source of the first transistor. After the command is executed, the gate of the second transistor is biased to a seventh voltage to deactivate the second transistor, wherein the seventh voltage is less than the third voltage at the source of the second transistor and the second threshold voltage of the second transistor; as well as The access line is isolated from the positive or negative voltage, at least in part, by biasing the gate of the first transistor and the gate of the second transistor.

23. The device of claim 22, wherein the second stage of the decoder further includes a third transistor, and wherein the controller is further configured to: After executing the command, the gate of the third transistor is biased to a fifth voltage exceeding the eighth voltage at the source of the third transistor and the third threshold voltage of the third transistor; and The eighth voltage is supplied to the access line at least in part based on the gate of the third transistor being biased.

24. The device according to claim 20, further comprising: The third transistor of the first stage of the decoder; The fourth transistor of the third stage of the decoder; as well as A voltage source supplying the positive voltage, wherein the controller is further configured to: At least in part based on receiving the command, the third transistor of the first stage of the decoder is activated, the third transistor being coupled to the first transistor and the fourth transistor; as well as The fourth transistor of the third stage of the decoder is activated to couple the third transistor to the voltage source supplying the positive voltage, wherein the controller is configured to bias the source of the first transistor at least in part based on activating the third transistor and activating the fourth transistor.

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