Digital sensor device and method of operating the same

Abstract

The present invention discloses a digital sensor device and a method for operating the digital sensor device. The working digital sensor of the present invention processes input digital information according to a database of digital content data stored in a content memory array and outputs corresponding digital data stored in a response memory array. Furthermore, the content memory array and the response memory array in the working digital sensor are composed of latch-type memory cells to manage the fast and frequently changing digital processing environment, similar to the information processing function of the working memory area in the human brain.

Description

Technical Field

[0001] The present invention relates to a computation-free digital in-memory processor. That is, the digital in-memory processor processes input digital information based on a database of digital content data stored in a volatile content memory and outputs corresponding digital response data stored in a volatile response memory. In particular, the content memory and response memory in the digital in-memory processor can be quickly updated to respond to new digital processing environments. Background Art

[0002] like Figure 1 In the modern Von Neumann computing architecture shown, a central processing unit (CPU) 10 performs logic operations based on instructions and data from a main memory 11. The CPU 10 includes a main memory 11, an arithmetic and logic unit (ALU) 12, an input / output device 13, and a program control unit 14. Before the computation process, the CPU 10 is set by the program control unit 14 to point to the initial address code of the initial instruction stored in the main memory 11. Thereafter, the ALU 12 processes the digital data according to the sequential instructions of the main memory 11 accessed by the clock-synchronized address pointer in the program control unit 14. Generally speaking, the digital logic operations of the CPU 10 are executed synchronously and driven by a set of sequential instructions that are pre-written and stored in the memory.

[0003] The power consumed by digital computing can be expressed mathematically as P~f×C×V DD 2 , where f represents the clock frequency, C represents the total capacitance of the active circuit, and V DDrepresents the positive supply voltage of the digital circuit. Therefore, the energy required to run an operation program is proportional to the number of clock steps to complete the set of instructions. Each instruction step includes fetching instructions and data from the main memory 11, performing micro-operations in the arithmetic and logic unit 12, and storing the resulting data back to the main memory 11 or outputting it to the input and output device 13. The total computing energy required to complete a set of instructions is proportional to the frequency of memory access and the total capacitance of the charge / discharge buslines and active circuits (registers, logic gates, and multiplexers). The higher the memory access frequency to complete the operation processing step, the more energy and time the digital processor must consume.

[0004] In a biological nerve system, external stimuli such as light, sound, touch, taste, smell, etc. are received by multiple sensory organ fields connected to the nervous system. Neural signals are transmitted in the form of electrical pulses and neural transmitters (molecules) generated in the receptor field to trigger the activation of the next connection layer of the neural network in the nervous system. The neural signal field generated by the connection layer continues to be processed forward through multiple layers of the neural network hardware of the nervous system. Each neural network layer processes and retrieves information in parallel according to its neuromorphic architecture and the receptive field of the neural signal from the previous layer. Unlike the current Van Neumann computing architecture that repeats multiple logical calculations of digital data through pre-written instructions, the neural signals for information processing use its neuromorphic architecture to propagate between layers in a single-step feed-forward manner. Therefore, in terms of information processing efficiency and energy consumption, the parallel processing and data acquisition method of the neural network level of the biological nervous system is superior to the processing and data acquisition method using multiple sequential logical calculations in current computing systems.

[0005] Inspired by the information parallel processing of neural networks, the applicant invented a digital memory processor that processes digital signals in parallel directly through the memory hardware of the processor in a feedforward step, similar to the information processing of neural network systems. The digital symbols of digital information processing are usually represented by a series of bits (binary numbers) mixed with 0 and 1, which are respectively represented by applying positive voltages V DDand ground voltage V SS to provide signals of 0 and 1. An input digital symbol with multiple bits (to represent specific input content information) can be intelligently processed by the memory processor to output another digital symbol representing perception / response information, so the memory processor is given the name of a "digital sensor". The meaning of "intelligently processing" is that the input digital "content" can autonomously generate the perception / response information based on a pool of known digital "content" knowledge. Compared with the above-mentioned "content" processing, the CPU uses logical operations and memory pointing to the address location to process digital information, while the field programmable gate array configures its address multiplexer through connections to retrieve the logical content of its internal look-up table for digital information processing.

[0006] The digital sensor can be programmed to store a group of digital content symbols and their corresponding digital output symbols in a memory unit, similar to built-in neural network hardware. The group of digital content symbols represents different scenarios in the real world, just like the digital content mentioned above. The corresponding digital output symbols can be digital commands to drive an analog device, or input digital symbols of other digital sensors. In the disclosure of Patent Publication No. CN107153872B of the People's Republic of China, the applicant applies a configurable non-volatile memory array to the digital sensor to store digital content symbols and digital perception / response symbols. For different processes, the non-volatile memory array can be programmed multiple times to respond to new information processing environments, such as updated digital information obtained from new input data sets or newly applied algorithms. Summary of the invention

[0007] The present invention provides a digital sensor device and a method of operating the digital sensor device to manage a fast and frequently changing digital processing environment, similar to the information processing function of the working memory area in the human brain.

[0008] In one aspect, the present invention provides a digital sensor device, comprising:

[0009] A volatile content memory array having m rows×n columns of first memory elements for comparing in parallel an n-bit input symbol with m n-bit content symbols, wherein the m n-bit content symbols are pre-stored in the m rows of first memory elements, wherein the first memory element in each row generates an indication signal to indicate whether the n-bit input symbol matches its pre-stored n-bit content symbol;

[0010] a detection and driving circuit, applying m second switching signals to m second word lines of a volatile response memory array respectively according to m indication signals and m first switching signals on m first word lines of the volatile content memory array; and

[0011] The volatile response memory array has m rows×q columns of second memory elements, wherein the m rows of second memory elements respectively pre-store m q-bit response symbols, wherein when the second memory elements of a row receive an activated second switching signal, the second memory elements of the row are turned on to output their pre-stored q-bit response symbols as a q-bit output symbol.

[0012] In one aspect, the present invention provides a method of operating a digital sensor device, the digital sensor device comprising a volatile content memory array and a volatile response memory array, the method comprising:

[0013] Comparing in parallel an n-bit input symbol and m n-bit content symbols, the m n-bit content symbols being pre-stored in a volatile content memory array having m rows×n columns of first memory elements, so that the first memory element in each row generates an indication signal to indicate whether the n-bit input symbol matches its pre-stored n-bit content symbol;

[0014] According to the m indication signals and the m first switching signals on the m first word lines in the volatile content memory array, respectively applying m second switching signals to the m second word lines of a volatile response memory array having m rows×q columns of second memory elements, wherein the m rows of second memory elements respectively pre-store m q-bit response symbols;

[0015] When a second memory element of a row receives an activated second switching signal, the second memory element of the row is turned on to output its pre-stored q-bit response symbol as a q-bit output symbol; and

[0016] When the second memory elements of a row receive a second switching signal that fails, the second memory elements of the row are turned off.

[0017] Utilizing the present invention, a rapidly and frequently changing digital processing environment can be managed, similar to the information processing function of the working memory area in the human brain. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A conventional Van Neumann-type computing architecture of a typical CPU is shown.

[0019] Figure 2 A block diagram of the working digital perceptron (WDP) of the present invention is shown.

[0020] Figure 3 A schematic diagram of a serial CAM array with n columns and m rows is shown according to an embodiment of the present invention.

[0021] Figure 4 According to an embodiment of the present invention, a schematic diagram of a write word line driver unit and a word line decoder is shown.

[0022] Figure 5 According to an embodiment of the present invention, the display Figure 3 Schematic diagram of the n-bit SRAM write driver unit of the CAM array.

[0023] Figure 6 According to an embodiment of the present invention, a schematic diagram of a match detection unit and a write selection and word line driving unit is shown.

[0024] Figure 7 A schematic diagram of a SRAM array is shown according to an embodiment of the present invention.

[0025] Figure 8 According to an embodiment of the present invention, a schematic diagram of a q-bit SRAM write driver unit is shown.

[0026] Fig. 9 A schematic diagram showing a matching logic unit of the WDP according to an embodiment of the present invention.

[0027] Fig.10 A schematic diagram of an n-bit input buffer and a driving unit is shown according to an embodiment of the present invention.

[0028] Fig.11 A schematic diagram of a q-bit output buffer and a driving unit is shown according to an embodiment of the present invention.

[0029] Figure Number:

[0030] 10CPU

[0031] 11 Main Memory

[0032] 12 Arithmetic and logic unit

[0033] 13 Output / Input Devices

[0034] 14Program control unit

[0035] 20n-bit input bus line

[0036] 21 Word line selection node

[0037] 22 Write content bus line

[0038] 23 Write response bus line

[0039] 24, 25, 26, 65, 81 nodes

[0040] 27 External output bus line

[0041] 61 Match Detector

[0042] 62 Flip-flop

[0043] 63 word line selection unit

[0044] 64 Drivers

[0045] 71SRAM cells

[0046] 110q-bit output buffer and driver unit

[0047] 111 Output data flip-flop

[0048] 112 Output drive unit

[0049] 200 Working Digital Sensors

[0050] 300 CAM arrays in series

[0051] 301 Word Line WC i

[0052] 302 2n bit line

[0053] 303 m matching lines

[0054] 310 CAM unit

[0055] 315 6T SRAM cell

[0056] 316, 317 complementary nodes

[0057] 318 Output common electrode

[0058] 319 Access transistor

[0059] 320 Latched Inverter

[0060] 321, 322 Connecting electrodes

[0061] 400 Write word line driver unit

[0062] 410 Two-Stage Inverter Buffer

[0063] 500n-bit SRAM write driver unit

[0064] 510, 751, 920 data flip-flop

[0065] 520, 752 Inverting Driver

[0066] 530, 753 transmission grid

[0067] 610 Matching Detection Unit

[0068] Nodes 611, 621, 622, 811, 812

[0069] 620 write selection and word line driving unit

[0070] 630 NOR gate

[0071] 640 Inverting Buffer

[0072] 700SRAM array

[0073] 701 word line WR i

[0074] 702 2q bit line

[0075] 750q-bit SRAM write driver unit

[0076] 800 matching logic units

[0077] 810PMOSFET

[0078] 820, 830NMOSFET

[0079] 840 Half Latch

[0080] 900n-bit input buffer and driver unit

[0081] 901 2n-bit search line

[0082] 930 Two-stage inverting driver DETAILED DESCRIPTION

[0083] The following detailed description is for illustrative purposes only and is not intended to be limiting. It should be understood that other embodiments may be used, and that various modifications or changes may be made to the structure, all of which shall fall within the scope of the claims of the present invention. Furthermore, it should be understood that the grammar and terminology used in this specification are for illustrative purposes only and shall not be considered limiting. Those familiar with the art shall understand that the embodiments of the methods and schematic diagrams in this specification are for illustrative purposes only and are not intended to be limiting. Those familiar with the art who understand the spirit of the present invention as a result of the disclosure of this specification may use other embodiments, all of which shall fall within the scope of the claims of the present invention.

[0084] Since many digital information processing, such as digital signal processing for video or audio, convolution coefficients calculated from real-time new data sets from different nodes / layers of deep neural network learning models, etc., require fast and frequent updates of the information processing environment, a digital perceptron with fast and frequent update capabilities is urgently needed. It is well known to those skilled in the art that the setup time (conventional floating gate non-volatile memory devices require a setup time of about 10ms to 1μs) and the write endurance (conventional floating gate non-volatile memory devices are about 100k times) of non-volatile memory devices are not as good as volatile memory devices (SRAM and DRAM) used in conventional Van Neumann type computing processor systems. According to the present invention, in order to cope with the fast and frequently changing digital processing environment, the applicant constructs a working digital perceptron (WDP) based on fast write and high endurance latch-type memory cells in volatile content memory and volatile response memory. The function of this WDP is very similar to the function of "working memory" in the human brain processing system. Please note that the concept of "working memory" has been defined and is well known in the field of neuroscience.

[0085] To complete the above functions of the working digital sensor, the applicant uses the following components to form Figure 2 The working digital sensor (WDP) 200 includes an n*m series content addressable memory (CAM) array 300, a q*m static random access memory (SRAM) array 700, an n-bit input buffer and driver unit 900, a q-bit output buffer and driver unit 110, a write wordline driver unit 400, an n-bit SRAM write driver unit 500, a q-bit SRAM write driver unit 750, a matching logic unit 800, a matching detection unit 610 and a write selection and wordline driver unit 620.

[0086] exist Figure 2, WDP 200 is connected to the n-bit input bus line 20 to receive input digital data signals, and is connected to the q-bit output bus line 27 to transmit output digital signals. A write content bus line 22 and a write response bus line 23 are respectively connected to the n-bit SRAM write driver unit 500 and the q-bit SRAM write driver unit 750. When the control signal WDin on the node 24 is turned to a high voltage level state, the two SRAM write driver units 500 and 750 receive and store a row of n-bit SRAM data signals and a row of q-bit SRAM data signals from the write content bus line 22 and the write response bus line 23, respectively. When the write enable signal WEnb on the node 25 is turned to a high voltage level state, a selected word line WC is activated in the write word line driver unit 400. i and successively activate the corresponding word lines WR in the SRAM array 700 i (with the selected word line WC i In the case of the same row), two SRAM write driver units 500 and 750 simultaneously write a row of n-bit content data and a row of q-bit response data to the bit line 302 of the CAM array 300 and the bit line 702 of the SRAM array 700, where 0<=i<=(m-1). By connecting to a word line decoder 40 ( Figure 4 ) is activated as a high voltage level state to complete the selection of the word line 301. Afterwards, the n-bit content data and the q-bit response data are written row by row to the m rows of the CAM array 300 and the m rows of the SRAM array 700, respectively. The m n-bit content data of the CAM array 300 and the m q-bit response data of the SRAM array 700 are adaptively updated to cope with the fast and frequently changing digital processing environment (similar to the information processing function of the "working memory" of the human brain).

[0087] After the CAM array 300 and the SRAM array 700 have finished storing the processed data, the node 26 has a high voltage V DD The enable signal Enb will start the WDP 200. Figure 2As shown. The input data signal from the external n-bit input bus line 20 is transmitted to the input buffer and driver unit 900 to search whether the input digital data matches any row of digital content data in the CAM array 300. When the input digital data matches a row of digital content data in the CAM array 300, its corresponding match line electrically connects its right node to its left node, and the left node 30 is biased to the ground voltage; otherwise, due to the electrical interruption of the match line, the right nodes of all unmatched match lines in the CAM array 300 will remain in a floating state. Then, the voltage signals of the m match lines 303 on the right nodes are fed to the match detection unit 610. The voltage signal on a matched match line is pulled down to the ground voltage level to be fed to the corresponding match detector 61, and then a high voltage signal V is generated through the write selection and word line driver unit 620. DD The corresponding word line of the SRAM array 700 is turned on, while the word lines of the SRAM array 700 corresponding to the other unmatched match lines remain turned off. Then, the voltage signal of the q-bit response code stored in the corresponding row of the SRAM array 700 is transmitted to the q-bit output buffer and driver unit 110 through the 2q bit line 702.

[0088] To eliminate false responses caused by irrelevant input content, the q-bit output buffer and driver unit 110 is connected to the external output bus line 27 if and only if the n-bit input data matches a row of content data in the CAM array 300. Figure 2 and Figure 6 , a high voltage V from the match detection unit 610 and applied to the node 65 DD The match signal MH (representing match) is transmitted to the matching logic unit 800. When the node 26 has a high voltage V DD When the enable signal Enb starts the WDP 200, the matching logic unit 800 outputs a high voltage V DD The OE signal is used to connect the q-bit output buffer and driver unit 110 and the external output bus line 27 to transmit the corresponding response data voltage signal of the relevant digital content to other units.

[0089] In one embodiment, Figure 3A schematic diagram of a CAM array 300 with n columns and m rows is shown. Each CAM cell 310 includes a typical 6T (transistor) SRAM cell 315, a complementary device pair of N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) N1 and N2, and a switching NMOSFET device N3. Each 6T SRAM cell 315 includes two latched inverters 320 and two access transistors 319. The two complementary nodes 316 and 317 of the two latched inverters 320 in the 6TSRAM cell 315 are respectively connected to the gates of the NMOSFET complementary device pair N1 and N2, and the output common electrode 318 of the NMOSFET complementary device pair N1 and N2 is connected to the gate of the switching NMOSFET device N3. Each word line WC i The gates of the access transistors 319 of each 6T SRAM cell 315 in a row of CAM cells 310 form m word lines WC. i 301, such as Figure 3 As shown, i=0~(m-1). 2n bit lines 302, BL i and The complementary bit lines of the CAM array 300 are composed of n columns of 6TSRAM cells 315. Each search line SL i and its complementary search line The 2*n search lines 901 are composed of n rows of search lines SL i and its complementary search line A row of n switching NMOSFET devices N3 connected in series forms a single match line, so a total of m match lines 303 are formed in the CAM array 300 of n columns and m rows.

[0090] The word line WC i 301 is connected to a write word line driver unit 400, such as Figure 4 As shown, i=0~(m-1). The 2n bit lines 302 of the CAM array 300 are connected to an n-bit SRAM write driver unit 500, as shown in FIG. Figure 5 A word line decoder 40 decodes an address code to activate a selected node S in the plurality of lines 21.i The high voltage signal V DD and the selected word line WC in the word line 301 i The high voltage signal V DD Next, select the node S based on the startup i , Figure 4 The two-stage inverter buffer 410 in the write word line driver unit 400 turns on the selected word line WC i . Figure 5 In the embodiment, the n-bit SRAM write driver unit 500 includes n data flip-flop units 510, 2n inverter buffers 520, and 2n transmission gates 530. The data flip-flop unit 510 is used to store the data from a plurality of bus lines DC j 22 receives a row of written content data, and the node 24 has a high voltage V DD The WDin signal starts the data flip-flop unit 510, where j=0~(n-1). The inverting driver 520 is used to drive a row of write data voltage signals into the bit line 302. The node 25 has a high voltage V DD The WEnb signal turns on the transmission gate 530 to connect the write data voltage signal to the 2n bit line 302 of the CAM array 300 .

[0091] From Figure 3 The right nodes of the m match lines 303 and the continuous word line bus lines 301 of the CAM array 300 are connected to the match detection unit 610 and the write selection and word line driving unit 620 respectively. Figure 6 In the embodiment, the match detection unit 610 includes m match detectors 61 and m flip-flops 62. The match detector 61 is used to sense the voltage bias on the node 611 connected to the right node of the m match lines 303, and the flip-flop 62 is used to store the match state data on the match line 303. Each match detector 61 includes a high voltage source PMOSFET device P1, a matching PMOSFET device P2, an inverter I M and a charging capacitor C M When a high voltage signal V DD When the Enb signal of a matching detector 61 is activated, its corresponding high voltage source PMOSFET device P1 is turned off to connect the capacitor node 611 connected to the corresponding matching line to the high voltage source rail V DDBecause the input data matches the data stored in a row of the CAM array 300, the matched match line connected to the match detector 61 is quickly discharged to the ground voltage, and the voltage potential of the capacitor node 611 drops to a level lower than that of the inverter I M At the same time, if the content data of a row of the CAM array 300 matches the input data, one of the PMOSFET devices P2 will charge the voltage of a matching signal MH on the node 65 to a high voltage V DD , then, the inverter I M The output voltage signal of the flip-flop 62 is stored in the corresponding flip-flop 62. For each row, the output of the flip-flop 62 at the node 622 and the continuous word line WC of the same row in the word line 301 are i Both are connected to the two input terminals of the NOR gate 630 in the word line selection unit 63. As for the matched match line and the written row SRAM data, the output terminal of the NOR gate 630 is further connected to the inverter buffer 640 in the driving unit 64 to start Figure 7 The selected word line WR in the response SRAM array 700 i .

[0092] Figure 7 A schematic diagram of an SRAM array 700 with q columns and m rows is shown. Each cell 71 is a typical SRAM cell, including 6 transistors. The word line WR of the SRAM array 700 i 701 are respectively connected to the output of the write selection and word line driver unit 620, where i=0~(m-1). The 2q bit lines / complementary bit lines 702 of the SRAM array 700 are respectively connected to the q-bit SRAM write driver unit 750 to write the response data, and connected to the q-bit output buffer and driver unit 110 to read the response data. Figure 8 The schematic diagram of the q-bit SRAM write driver unit 750 is shown. The q-bit SRAM write driver unit 750 includes q data flip-flops 751, 2*q inverting drivers 752 and 2*q transmission gates 753. DD The data flip-flop 751 stores the WDin signal from the node DR of the bus line 23. j The inverting driver 752 is used to drive the response data to the SRAM bit line 702. The node 25 has a high voltage V DD The WEnb signal of the node 24 activates the transmission gate 753 to write the data voltage signal to the bit line 702 of the SRAM array 700. When the control signal WDin on the node 24 has a high voltage V DD, the SRAM write driver units 500 and 750 receive and store a row of n-bit SRAM data signals and a row of q-bit SRAM data signals from the write content bus line 22 and the write response bus line 23, respectively. DD When a selected word line is activated by the write word line driver unit 400 and the write selection and word line driver unit 620, the SRAM write driver units 500 and 750 simultaneously write a row of n-bit content data and a row of q-bit response data to the bit line 302 of the CAM array 300 and the bit line 702 of the SRAM array 700. i A high voltage signal V is started on a node DD , to select one of the word lines 701, where i=0~(m-1), and the word line selects the node WR i Connected to the output end of the write selection and word line driving unit 620. Then, the n-bit content data and the q-bit response data are written into the m rows of the CAM array 300 and the SRAM array 700 row by row.

[0093] Fig. 9 A schematic diagram of the matching logic unit 800 is shown. When the node 26 is not powered by the voltage V SS When started (i.e., node 26 has a ground voltage), both PMOSFET 810 and NMOSFET 820 are turned on, resulting in output node 811 having a voltage potential V DD , causing the output node 81 of the half latch 840 to have a voltage potential V SS When the node 26 is at voltage V DD When the PMOSFET 810 and the NMOSFET 820 are turned off, only the matching signal MH at the node 65 has a voltage V DD When the NMOSFET 830 is turned on, the voltage potential of the node 811 is pulled down to the ground voltage, so that the output node 81 of the half latch 840 has V DD voltage potential. Therefore, Figure 2 Only the matching signal MH at the node 65 has a voltage V DD When V DD The OE signal with a voltage V can connect the q-bit output buffer and driver unit 110 and the q-bit output bus line 27. Accordingly, if the n-bit input data matches the n-bit content data of one row in the CAM array 300, a signal with a voltage V DD The matching signal MH causes the matching logic unit 800 to output a high voltage V at the node 81. DDThe q-bit output buffer and driver unit 110 is connected to the q-bit output bus line 27 by the OE signal of the CAM array 300. Otherwise, in the case of a "mismatched" content memory array (no row in the CAM array 300 matches), the q-bit output buffer and driver unit 110 will not be connected to the q-bit output bus line 27.

[0094] Fig.10 A schematic diagram of an n-bit input buffer and driver unit 900 is shown. The n-bit input buffer and driver unit 900 includes n data flip-flops 920 and 2n two-stage inverting drivers 930. The data flip-flops 920 are used to store n-bit input data, and the two-stage inverting drivers 930 are used to drive a voltage signal to the search line 901. When a voltage V DD When the Enb signal is supplied to start the WDP 200, the data flip-flop 920 receives the n-bit input data from the n-bit input bus line 20, and the two-stage inverting driver 930 drives the applied voltage signal to the search line 901 connected to the CAM array 300, that is, the SL i and Where j = 0 to (n-1). Figure 3 As shown, whenever an input bit matches a CAM cell 310, a voltage V is applied. DD On search line SL i The upper side represents the input data 1, or the voltage V is applied DD On complementary search lines The upper part represents input data 0, and the applied voltage V is transmitted by the on MOSFET device N2 representing the storage content data 1. DD , or the applied voltage V is passed by the turned-on MOSFET device N1 representing the storage content data 0 DD to their common output node 318 (reference Figure 3 ). Afterwards, the voltage V C <~V DD can be used to turn on the switching transistor N3. i It is composed of switching transistors N3 connected in series in the i-th row. i The left node of the CAM array 300 is connected to the ground node 30, and the right node of the CAM array 300 is connected to the corresponding match detector 61. When the input data string matches the content data of a whole row of the CAM array 300, the match line ML iOn the other hand, if the input data string does not match the content data of a whole row of the CAM array 300, the right node of the unmatched match line will float because any turned-off transistor N3 in the row of the unmatched match line will interrupt the ground voltage electrically connected to the left node.

[0095] When the match detector unit 610 and the write selection and word line driver unit 620 turn on one of the word lines 701 in the SRAM array 700, the voltage V DD The Enb signal transmits the q-bit voltage signal of the corresponding row in the SRAM array 700 to the q output data flip-flops 111, such as Fig.11 As shown. Fig. 9 The node 81 of the matching logic unit 800 has a voltage V DD The OE signal causes the output driver unit 112 to be connected to Figure 2 Output bus line 27Q j , where j=0~(q-1). Afterwards, the q-bit output voltage signal of the WDP 200 in response to the data is transmitted to the q-bit output bus line 27 to be connected to other digital circuit units.

[0096] The preferred embodiments provided above are only used to illustrate the present invention, and are not intended to limit the present invention to a specific type or exemplary embodiment. Therefore, this specification should be regarded as illustrative rather than restrictive. The preferred embodiments provided above are to effectively illustrate the gist of the present invention and its best mode of implementation, so as to allow those familiar with the art to understand the various embodiments and various changes of the present invention to adapt to specific uses or implementation purposes. The scope of the present invention is defined by the claims and their equivalents, in which all terms are intended to have the broadest reasonable meaning unless otherwise specifically indicated. Therefore, "the present invention" and similar terms do not limit the scope of the claims to a specific embodiment, and any reference to a specific preferred embodiment of the present invention does not mean to limit the present invention, and no such limitation will be inferred. The present invention is defined only by the claims and spirit. The abstract of the present invention is provided in accordance with the requirements of the law so that searchers can quickly confirm the subject matter of this technical disclosure from any patent approved by this specification, and is not used to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the present invention. It should be understood that various modifications or changes can be made by the industry, all of which should fall within the scope of the present invention defined by the claims. Furthermore, all elements and components in this specification are not intended to be dedicated to the public, regardless of whether the claims list the elements and components.

Claims

1. A digital sensor device, characterized in that: Include: A volatile content memory array having m rows×n columns of first memory elements for comparing in parallel an n-bit input symbol with m n-bit content symbols, wherein the m n-bit content symbols are pre-stored in the m rows of first memory elements, wherein the first memory element in each row generates an indication signal to indicate whether the n-bit input symbol matches its pre-stored n-bit content symbol; a detection and driving circuit, applying m second switching signals to m second word lines of a volatile response memory array respectively according to m indication signals and m first switching signals on m first word lines of the volatile content memory array; as well as The volatile response memory array has m rows×q columns of second memory elements, wherein the m rows of second memory elements respectively pre-store m q-bit response symbols, wherein when the second memory elements of a row receive an activated second switching signal and an activated first control signal, the second memory elements of the row are turned on to output the pre-stored q-bit response symbols as a q-bit output symbol; wherein the volatile content memory array and the volatile response memory array respectively pre-store the m n-bit content symbols and the m q-bit response symbols in a row-by-row manner; The first memory element and the second memory element located in the same row simultaneously pre-store a corresponding n-bit content symbol and a corresponding q-bit response symbol according to a corresponding activated first switching signal and a corresponding activated second switching signal; and The m first word lines in the volatile content memory array correspond to the m second word lines in the volatile response memory array in sequence.

2. The digital sensor device according to claim 1, characterized in that When all second switching signals are inactive, the volatile response memory array does not output any q-bit response symbol.

3. The digital sensor device according to claim 1, characterized in that The detection and driving circuit is responsive to the first control signal, the m indication signals and the m first switching signals to activate one or zero of the m second switching signals and activate a matching signal, wherein the first control signal is activated to activate the digital sensor device, and wherein the matching signal is activated when the n-bit input symbol matches one of the m n-bit content symbols.

4. The digital sensor device according to claim 3, characterized in that The detection and driving circuit comprises m sensing elements, each sensing element comprising: a matching detector, used for receiving the first control signal and a corresponding indication signal to generate a sensing signal; a flip-flop connected between the matching detector and a driving unit, and used for responding to the first control signal to store the sensing signal; as well as The driving unit is used for responding to the sensing signal and a corresponding first switching signal on a corresponding first word line, and activating a corresponding second switching signal.

5. The digital sensor device according to claim 4, characterized in that Each match detector contains: a first PMOS device connected between a digital voltage rail and a first connection node, wherein the digital voltage rail has a digital voltage and the first connection node receives a corresponding indication signal, wherein a gate of the first PMOS device receives the first control signal; a second PMOS device connected between the digital voltage rail and a second connection node, wherein a gate of the second PMOS device is connected to the first connection node; an inverter connected between the first connection node and the flip-flop, for inverting the corresponding indication signal into the sensing signal; and a capacitor connected between the first connection node and a ground node; The second connection nodes of all the matching detectors are connected to generate the matching signal.

6. The digital sensor device according to claim 3, characterized in that Also includes: an input bus receiving the n-bit input signal; and An input buffer and driving unit is connected between the n complementary search line pairs of the volatile content memory array and the input bus, and is used to temporarily store and drive the n-bit input signal to the n complementary search line pairs according to the first control signal.

7. The digital sensor device according to claim 3, characterized in that Also includes: an output bus; and an output buffer and a driving unit, located between the q complementary second bit line pairs of the volatile response memory array and the output bus, for temporarily storing the q-bit output symbol and driving the q-bit output symbol to the output bus, wherein whether the output buffer and the driving unit are electrically connected to the q complementary second bit line pairs of the volatile response memory array depends on the first control signal, and wherein whether the output buffer and the driving unit are electrically connected to the output bus depends on the matching signal.

8. The digital sensor device according to claim 3, characterized in that Also includes: a word line decoder and driver circuit, decoding an address signal, activating one of the m first switching signals, and applying the m first switching signals to the m first word lines respectively; An n-bit data bus; A q-bit data bus; an n-bit write driver circuit connected to the n-bit data bus according to a second control signal, and writing one of m n-bit content symbols from the n-bit data bus into the volatile content memory array according to a third control signal and the activated first switching signal; as well as a q-bit write driver circuit connected to the q-bit data bus according to the second control signal, and writing one of the m n-bit response symbols from the q-bit data bus into the volatile response memory array according to the third control signal and the activated second switching signal; Wherein, before the first control signal is activated, the second control signal and the third control signal are activated first.

9. The digital sensor device according to claim 1, wherein: The volatile content memory array comprises: m matching lines, each matching line generates a corresponding indication signal and is composed of switching transistors of a plurality of first memory elements in a corresponding row connected in series; n complementary search line pairs, receiving the n-bit input symbol, each complementary search line pair being connected to a plurality of first memory elements in a row; n complementary first bit line pairs, receiving the m n-bit content symbols, each complementary first bit line pair being connected to a plurality of first memory elements in a column; as well as A common source line is used to connect the same-side endpoints of the matching lines to a preset voltage terminal.

10. The digital sensor device according to claim 9, characterized in that Each first memory element comprises: A static random access memory cell comprising: a latch having a first output node and a second output node; and a first access transistor and a second access transistor, wherein the first access transistor is connected between the first output node and a bit line of a corresponding complementary first bit line pair, and the second access transistor is connected between the second output node and another bit line of the corresponding complementary first bit line pair; a first NMOS device, a gate of the first NMOS device connected to the first output node; a second NMOS device having a gate connected to the second output node; and The switching transistor, wherein the first end of the first NMOS device and the first end of the second NMOS device are connected to the gate of the switching transistor, the second end of the first NMOS device is connected to a first search line of a corresponding complementary search line pair, and the second end of the second NMOS device is connected to a second search line of the corresponding complementary search line pair.

11. The digital sensor device according to claim 1, wherein: According to the m n-bit content symbols and the m q-bit response symbols, the n-bit input symbol can independently generate the q-bit output symbol.

12. The digital sensor device of claim 1, wherein: The m n-bit content symbols in the volatile content memory array and the m q-bit response symbols in the volatile response memory array may be adaptively updated.

13. A method of operating a digital sensor device, characterized in that: The digital sensor device includes a volatile content memory array and a volatile response memory array, and the method includes: Pre-storing m n-bit content symbols and m q-bit response symbols in the volatile content memory array and the volatile response memory array, respectively, in a row-by-row manner; Comparing in parallel an n-bit input symbol and the m n-bit content symbols, the m n-bit content symbols being pre-stored in a volatile content memory array having m rows×n columns of first memory elements, so that the first memory element in each row generates an indication signal to indicate whether the n-bit input symbol matches its pre-stored n-bit content symbol; According to the m indication signals and the m first switching signals on the m first word lines in the volatile content memory array, respectively applying m second switching signals to the m second word lines of a volatile response memory array having m rows×q columns of second memory elements, wherein the m rows of second memory elements respectively pre-store m q-bit response symbols; When a second memory element of a row receives an activated second switching signal and an activated first control signal, the second memory element of the row is turned on to output its pre-stored q-bit response symbol as a q-bit output symbol; and When a second memory element of a row receives a second switching signal that fails, turning off the second memory element of the row; The step of pre-storing m n-bit content symbols and m q-bit response symbols into the volatile content memory array and the volatile response memory array respectively comprises: According to a corresponding activated first switching signal and a corresponding activated second switching signal, simultaneously pre-storing a corresponding n-bit content symbol and a corresponding q-bit response symbol into a first memory element and a second memory element located in the same row; The m first word lines in the volatile content memory array correspond to the m second word lines in the volatile response memory array in sequence.

14. The method according to claim 13, characterized in that Also includes: When all second switching signals are inactive, the volatile response memory array does not output any q-bit response symbol.

15. The method according to claim 13, characterized in that Also includes: Before the parallel comparison step and after the steps of pre-storing m n-bit content symbols and m q-bit response symbols in the volatile content memory array and the volatile response memory array, respectively, the first control signal is activated to activate the digital sensor device.

16. The method according to claim 15, characterized in that The respective applying step further comprises: According to the m indication signals and the first control signal, respectively generate m sensing signals and activate a matching signal; storing the m sensing signals respectively according to the first control signal; as well as Activate one or zero of the m second switching signals according to the m sensing signals and the m first switching signals on the m first word lines; Wherein, when the n-bit input symbol matches one of the m n-bit content symbols and the first control signal is activated, the match signal is activated.

17. The method according to claim 15, characterized in that Also includes: Before the parallel comparison step and after the steps of pre-storing the m n-bit content symbols and the m q-bit response symbols in the volatile content memory array and the volatile response memory array, respectively, temporarily storing the n-bit input symbol; as well as According to the first control signal, the n-bit input symbol is driven to n complementary search line pairs of the volatile content memory array.

18. The method according to claim 16, characterized in that Also includes: After the connecting step, temporarily storing the q-bit output symbol according to the first control signal; and The q-bit output symbol is driven to an output bus according to the matching signal.

19. The method of claim 13, wherein: According to the m n-bit content symbols and the m q-bit response symbols, the n-bit input symbol can independently generate the q-bit output symbol.

20. The method of claim 13, wherein: Also includes: Before all steps, the m n-bit content symbols and the m q-bit response symbols are written into the volatile content memory array and the volatile response memory array respectively.

21. The method of claim 13, wherein: The step of pre-storing m n-bit content symbols and m q-bit response symbols into the volatile content memory array and the volatile response memory array respectively comprises: (a) decoding an address signal to activate one of the m first switching signals; (b) applying the m first switching signals to the m first word lines respectively; (c) activating one of the second switching signals according to the activated first switching signal; (d) applying the m second switching signals to the m second word lines respectively; (e) writing an n-bit content symbol into the volatile content memory array according to a second control signal and the activated first switching signal; (f) writing a q-bit response symbol into the volatile response memory array according to the second control signal and the activated second switching signal; as well as (g) Repeating steps (a) to (f) until the m n-bit content symbols and the m q-bit response symbols are all written into the volatile content memory array and the volatile response memory array.

22. The method of claim 13, wherein: Also includes: After the turning on step and the turning off step, m updated n-bit content symbols and m updated q-bit response symbols are adaptively written into the volatile content memory array and the volatile response memory array, respectively.

Images